TPS54561
SLVSBO1G – JULY 2013 – REVISED JUNE 2021
TPS54561 4.5-V to 60-V Input, 5-A, Step-Down DC-DC Converter
with Soft-Start and Eco-mode™
1 Features
3 Description
•
The TPS54561 is a 60-V, 5-A, step down regulator
with an integrated high side MOSFET. The device
survives load dump pulses up to 65V per ISO
7637. Current mode control provides simple external
compensation and flexible component selection. A
low ripple pulse skip mode reduces the no load
supply current to 152 μA. Shutdown supply current
is reduced to 2 μA when the enable pin is pulled low.
•
•
•
•
•
•
•
•
•
•
2 Applications
•
•
•
•
Industrial automation and motor control
Vehicle accessories: GPS (see SLVA412),
entertainment
USB dedicated charging ports and battery
chargers (see SLVA464)
12-V, 24-V, and 48-V industrial, automotive, and
communications power systems
Undervoltage lockout is internally set at 4.3 V but
can increase using an external resistor divider at
the enable pin. The output voltage start up ramp
is controlled by the soft start pin that can also be
configured for sequencing/tracking. An open drain
power good signal indicates the output is within 93%
to 106% of its nominal voltage.
A wide adjustable switching-frequency range allows
for optimization of either efficiency or external
component size. Cycle-by-cycle current limit,
frequency foldback and thermal shutdown protects
internal and external components during an overload
condition.
The TPS54561 is available in an 10-pin 4-mm × 4-mm
WSON package.
Device Information
PACKAGE(1)
PART NUMBER
TPS54561
(1)
VIN
BODY SIZE (NOM)
WSON (10)
4.00 mm × 4.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100
VIN
36 V to 12 V
PWRGD
95
TPS54561
90
BOOT
EN
RT/CLK
SS/TR
VOUT
SW
Efficiency (%)
•
•
High efficiency at light loads with pulse skipping
Eco-mode™
87-mΩ high-side MOSFET
152-μA operating quiescent current and
2-μA shutdown current
100-kHz to 2.5-MHz adjustable switching
frequency
Synchronizes to external clock
Low dropout at light loads with integrated BOOT
recharge FET
Adjustable UVLO voltage and hysteresis
UV and OV power-good output
Adjustable soft start and sequencing
0.8-V 1% internal voltage reference
10-pin WSON with thermal pad package
–40°C to 150°C TJ operating range
Create a custom design using the TPS54561 with
the WEBENCH® Power Designer
85
12 V to 3.3 V
80
12 V to 5 V
75
70
VOUT = 12 V, fsw = 620kHz,
VOUT = 5 V and 3.3 V, f sw = 400 kHz
65
COMP
FB
60
0
1
2
3
IO - Output Current (A)
GND
4
5
C024
Efficiency vs Load Current
Copyright © 2017, Texas Instruments Incorporated
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54561
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SLVSBO1G – JULY 2013 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements.................................................. 8
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................ 9
7 Detailed Description......................................................14
7.1 Overview................................................................... 14
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................29
8 Application and Implementation.................................. 30
8.1 Application Information............................................. 30
8.2 Typical Applications.................................................. 30
9 Power Supply Recommendations................................44
10 Layout...........................................................................45
10.1 Layout Guidelines................................................... 45
10.2 Layout Example...................................................... 45
10.3 Estimated Circuit Area............................................ 45
11 Device and Documentation Support..........................46
11.1 Device Support........................................................46
11.2 Documentation Support.......................................... 46
11.3 Receiving Notification of Documentation Updates.. 46
11.4 Support Resources................................................. 46
11.5 Trademarks............................................................. 46
11.6 Electrostatic Discharge Caution.............................. 46
11.7 Glossary.................................................................. 47
12 Mechanical, Packaging, and Orderable
Information.................................................................... 47
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (January 2017) to Revision G (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Added VIN - SW 5-ns and 10-ns transient .........................................................................................................5
• Changed SW - GND 5-ns and 10-ns transient max values to 67 V ...................................................................5
Changes from Revision E (February 2016) to Revision F (January 2017)
Page
• Added the WEBENCH information in the Features, Detailed Design Procedure, and Device Support sections
............................................................................................................................................................................1
• Changed Equation 10 and Equation 11 ........................................................................................................... 21
• Changed Equation 30 ...................................................................................................................................... 31
• Changed From: "power pad" To: "thermal pad" in the Layout Guidelines section............................................ 45
Changes from Revision C (November 2013) to Revision D (February 2016)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
Changes from Revision B (November 2013) to Revision C (November 2013)
Page
• Changed the device from : Product Preview To: Production.............................................................................. 1
Changes from Revision A (October 2013) to Revision B (November 2013)
Page
• Changed PowerPAD to Thermal Pad in FEATURES list item............................................................................ 1
• Deleted reference to PowerPAD from the DESCRIPTION section.....................................................................1
• Deleted ORDERING INFORMATION table before DEVICE INFORMATION section........................................ 4
Changes from Revision * (July 2013) to Revision A (October 2013)
Page
• Changed the Efficiency vs Load Current graph, fSW = 630 KhZ To: fSW = 620 kHz............................................1
• Added the APPLICATION INFORMATION section...........................................................................................31
2
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•
SLVSBO1G – JULY 2013 – REVISED JUNE 2021
Added the Power Dissipation Estimate section................................................................................................ 37
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5 Pin Configuration and Functions
BOOT
1
10
PWRGD
VIN
2
9
SW
EN
3
8
GND
SS/TR
4
7
COMP
RT/CLK
5
6
FB
Figure 5-1. DPR Package 10-Pin WSON Top View
Table 5-1. Pin Functions
PIN
NAME
4
NO.
I/O
DESCRIPTION
BOOT
1
O
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
VIN
2
I
Input supply voltage with 4.5-V to 60-V operating range.
EN
3
I
Enable pin, with internal pull-up current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
undervoltage lockout with two resistors. See Section 7.3.7.
SS/TR
4
I
Soft-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
RT/CLK
5
I
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using
an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal
amplifier is re-enabled and the operating mode returns to resistor frequency programming.
FB
6
I
Inverting input of the transconductance (gm) error amplifier.
COMP
7
O
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
compensation components to this pin.
GND
8
–
Ground
SW
9
I
The source of the internal high-side power MOSFET and switching node of the converter.
PWRGD
10
O
Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal
shutdown, dropout, over-voltage or EN shut down
Thermal Pad
11
–
GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
–0.3
65
VIN - SW, 5-ns Transient
-7
67
VIN - SW, 10-ns Transient
-2
67
EN
–0.3
8.4
BOOT–SW
–0.3
8
FB
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
6
SS/TR
–0.3
3
RT/CLK
–0.3
3.6
SW - GND, 5-ns Transient
–7
67
SW - GND, 10-ns Transient
–2
67
VIN
Voltage
SW
UNIT
V
–0.6
65
Operating junction temperature, TJ
–40
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply input voltage, VVIN
4.5
60
V
Output voltage, VO
0.8
58.8
V
Output current, IO
Operating junction temperature, TJ
0
5
A
-40
150
°C
6.4 Thermal Information
TPS54561
THERMAL METRIC(1) (2)
DPR (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance (standard board)
35.1
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
34.1
°C/W
RθJB
Junction-to-board thermal resistance
12.3
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
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TPS54561
THERMAL METRIC(1) (2)
DPR (WSON)
UNIT
10 PINS
ψJB
Junction-to-board characterization parameter
12.5
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
2.2
°C/W
(1)
(2)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See Section 8.2.1.2.12 for more information.
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout
threshold
4.5
Rising
4.1
Internal undervoltage lockout
threshold hysteresis
4.3
60
V
4.48
V
325
mV
Shutdown supply current
EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V
2.25
4.5
Operating: nonswitching supply
current
FB = 0.9 V, TA = 25°C
152
200
1.2
1.3
μA
ENABLE AND UVLO (EN PIN)
Enable threshold voltage
Input current
No voltage hysteresis, rising and falling
–4.6
Enable threshold –50 mV
Hysteresis current
Enable to COMP active
1.1
Enable threshold +50 mV
–0.58
–1.2
-1.8
–2.2
–3.4
-4.5
VIN = 12 V, TA = 25°C
540
V
μA
μA
µs
VOLTAGE REFERENCE
Voltage reference
0.792
0.8
0.808
87
185
V
HIGH-SIDE MOSFET
On-resistance
VIN = 12 V, BOOT-SW = 6 V
mΩ
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V
Error amplifier transconductance (gM)
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V
during soft-start
Error amplifier dc gain
VFB = 0.8 V
Min unity gain bandwidth
Error amplifier source/sink
V(COMP) = 1 V, 100 mV overdrive
COMP to SW current
transconductance
50
nA
350
μMhos
77
μMhos
10,000
V/V
2500
kHz
±30
μA
17
A/V
CURRENT LIMIT
Current limit threshold
All VIN and temperatures, Open Loop(1)
6.3
7.5
8.8
All temperatures, VIN = 12 V, Open Loop(1)
6.3
7.5
8.3
7.1
7.5
7.9
VIN = 12 V, TA = 25°C, Open
Loop(1)
Current limit threshold delay
A
60
ns
176
°C
12
°C
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold
1.55
RT/CLK low threshold
0.5
2
V
1.2
V
1.7
µA
42
mV
SOFT START AND TRACKING (SS/TR PIN)
Charge current
VSS/TR = 0.4 V
SS/TR-to-FB matching
VSS/TR = 0.4 V
SS/TR-to-reference crossover
98% nominal
1.16
V
SS/TR discharge current (overload)
FB = 0 V, VSS/TR = 0.4 V
354
µA
SS/TR discharge voltage
FB = 0 V
54
mV
FB threshold for PWRGD low
FB falling
90
%
FB threshold for PWRGD high
FB rising
93
%
FB threshold for PWRGD low
FB rising
108
%
POWER GOOD (PWRGD PIN)
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TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FB threshold for PWRGD high
FB falling
106
Hysteresis
FB falling
2.5
%
%
Output high leakage
VPWRGD = 5.5 V, TA = 25°C
10
nA
On resistance
IPWRGD = 3 mA, VFB < 0.79 V
45
Minimum VIN for defined output
VPWRGD < 0.5 V, IPWRGD = 100 µA
0.9
Ω
2
V
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
6.6 Timing Requirements
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
MIN
NOM
MAX
UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum CLK input pulse width
15
ns
RT/CLK falling edge to SW rising edge delay – Measured at 500 kHz with
RT resistor in series
55
ns
6.7 Switching Characteristics
TJ = –40°C to 150°C, VIN = 4.5 V to 60 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
450
500
550
kHz
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
fSW
Switching frequency
Switching frequency range using RT
mode
100
2500
kHz
Switching frequency range using
CLK mode
160
2300
kHz
PLL lock in time
8
RT = 200 kΩ
Measured at 500 kHz
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6.8 Typical Characteristics
0.814
VFB - Voltage Reference (V)
RDSON - Static Drain-Source
On-State Resistance ( )
0.25
0.2
0.15
0.1
0.05
BOOT-SW = 3 V
0.809
0.804
0.799
0.794
0.789
V
VIN
12VV
IN ==12
BOOT-SW = 6 V
0
0.784
±50
±25
0
25
50
75
100
125
150
TJ ± Junction Temperature (ƒC)
±50
Figure 6-1. ON Resistance vs Junction
Temperature
0
25
50
75
100
125
C002
Figure 6-2. Voltage Reference vs Junction
Temperature
High Slide Switch Current (A)
9
8.5
8
7.5
7
6.5
8.5
8
7.5
7
-40 °C
25 °C
150 °C
6.5
V
VIN
12VV
IN ==12
6
6
±50
±25
0
25
50
75
100
125
0
150
TJ ± Junction Temperature (ƒC)
10
20
30
40
50
VI - Input Voltage (V)
C003
Figure 6-3. Switch Current Limit vs Junction
Temperature
60
C004
Figure 6-4. Switch Current Limit vs Input Voltage
550
500
540
FSW - Switching Frequency (kHz)
FS - Switching Frequency (kHz)
150
TJ ± Junction Temperature (ƒC)
9
High Slide Switch Current (A)
±25
C001
530
520
510
500
490
480
470
460
RT = 200 k,
k VIN
, VIN==12
12VV
450
450
400
350
300
250
200
150
100
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
125
150
200
Figure 6-5. Switching Frequency vs Junction
Temperature
300
400
500
600
700
RT/CLK - Resistance (k )
C005
800
900
1000
C006
Figure 6-6. Switching Frequency vs RT/CLK
Resistance Low Frequency Range
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500
450
2000
400
1500
gm - uA/V
FSW - Switching Frequency (kHz)
2500
1000
350
300
500
250
VIN
12VV
VIN ==12
0
200
0
50
100
150
200
RT/CLK - Resistance (k )
±50
±25
Figure 6-7. Switching Frequency vs RT/CLK
Resistance High Frequency Range
0
25
50
75
100
125
150
TJ ± Junction Temperature (ƒC)
C007
C008
Figure 6-8. EA Transconductance vs Junction
Temperature
120
1.3
110
1.27
EN - Threshold (V)
100
gm - uA/V
90
80
70
60
50
40
VIN
12VV
VIN ==12
VIN
12VV
VIN ==12
20
1.15
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
150
±50
±25
±0.7
±3.9
±0.9
±4.1
±1.1
Current IEN (uA)
±0.5
±3.7
±4.5
±4.7
±4.9
±5.1
25
50
75
100
125
150
C010
Figure 6-10. EN Pin Voltage vs Junction
Temperature
±3.5
±4.3
0
TJ ± Junction Temperature (ƒC)
C009
Figure 6-9. EA Transconductance During Soft-Start
vs Junction Temperature
Current IEN (uA)
1.21
1.18
30
±1.3
±1.5
±1.7
±1.9
±2.1
±5.3
VIN
12V,
V,IEN
IEN
= Threshold
+ 50
mV
V
= Threshold
+ 50
mV
IN ==12
±5.5
±2.3
VIN
12V,
V,IEN
IEN
Threshold
+ 50
VIN ==12
==
Threshold
- 50
mVmV
±2.5
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
C011
Figure 6-11. EN Pin Current vs Junction
Temperature
10
1.24
150
C012
Figure 6-12. EN Pin Current vs Junction
Temperature
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100.0
±2.5
Nominal Switching Frequency (%)
±2.7
IEN Hysteresis (uA)
±2.9
±3.1
±3.3
±3.5
±3.7
±3.9
±4.1
±4.3
12VV
VVIN
IN ==12
75.0
50.0
25.0
V
Vsense
Falling
SENSE Falling
0.0
±4.5
±50
±25
0
25
50
75
100
125
0.0
150
TJ ± Junction Temperature (ƒC)
0.1
0.2
0.3
2.5
2.5
Supply Current IVIN (uA)
3
1.5
1
0.5
0.7
0.8
C014
2
1.5
1
0.5
0.5
= 12
TVIN
°CV
J = 25
VIN
12VV
V
IN ==12
0
0
±50
±25
0
25
50
75
100
125
0
150
TJ ± Junction Temperature (ƒC)
10
190
190
Supply Current IVIN (uA)
210
150
130
110
30
40
50
60
C016
Figure 6-16. Shutdown Supply Current vs Input
Voltage (VIN)
210
170
20
VIN - Input Voltage (ƒC)
C015
Figure 6-15. Shutdown Supply Current vs Junction
Temperature
Supply Current IVIN (uA)
0.6
Figure 6-14. Switching Frequency vs FB
3
2
0.4
VSENSE (V)
C013
Figure 6-13. EN Pin Current Hysteresis vs Junction
Temperature
Supply Current IVIN (uA)
Vsense
Falling
V
SENSE Rising
170
150
130
110
90
90
VIN
T
2512
°CV
J==
VIN
12VV
V
IN ==12
70
70
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
125
150
0
Figure 6-17. VIN Supply Current vs Junction
Temperature
10
20
30
40
VIN - Input Voltage (ƒC)
C017
50
60
C018
Figure 6-18. VIN Supply Current vs Input Voltage
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2.6
4.5
2.5
4.4
2.4
4.3
2.3
4.2
VIN (V)
VI(BOOT-PH) (V)
SLVSBO1G – JULY 2013 – REVISED JUNE 2021
2.2
4.1
4
2.1
3.9
2
UVLO Start Switching
BOOT-PH UVLO Falling
3.8
1.9
UVLO Stop Switching
BOOT-PH UVLO Rising
3.7
1.8
±50
±25
0
25
50
75
100
125
150
TJ ± Junction Temperature (ƒC)
±50
50
75
100
125
150
C020
FB
108
Power Good Threshold (%)
70
Power Good Resistance ( )
25
110
80
60
50
40
30
20
10
106
FB Falling
104
102
100
VIN = 12 V
98
96
FB Rising
94
92
90
VIN
12VV
VIN ==12
0
FB Falling
88
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
TJ ± Junction Temperature (ƒC)
C021
Figure 6-21. PWRGD ON Resistance vs Junction
Temperature
150
C022
Figure 6-22. PWRGD Threshold vs Junction
Temperature
60
900
VVIN
1212V,V,2525°C°C
IN = =
55
SS/TR to FB Offset (mV)
800
700
Offset (mV)
0
TJ ± Junction Temperature (ƒC)
Figure 6-20. Input Voltage UVLO vs Junction
Temperature
Figure 6-19. BOOT-SW UVLO vs Junction
Temperature
600
500
400
300
200
50
45
40
35
30
100
25
0
20
0
100
200
300
400
500
600
700
SS/TR (mV)
800
VIN
12V,
V,FB
FB==0.4
0.4VV
V
IN ==12
±50
±25
0
25
50
75
100
TJ ± Junction Temperature (ƒC)
C024
Figure 6-23. SS/TR to FB Offset vs FB
12
±25
C019
125
150
C025
Figure 6-24. SS/TR to FB Offset vs Temperature
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5.6
Start
Stop
5.5
5.4
VIN (V)
5.3
5.2
5.1
Dropout
Voltage
5.0
4.9
Dropout
Voltage
4.8
4.7
4.6
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
C026
Figure 6-25. 5-V Start and Stop Voltage (see )
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7 Detailed Description
7.1 Overview
The TPS54561 is a 60-V, 5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. The
device implements constant frequency, current mode control which reduces output capacitance and simplifies
external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz allows either
efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted
using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL)
connected to the RT/CLK pin that will synchronize the power switch turn on to a falling edge of an external clock
signal.
The TPS54561 has a default input start-up voltage of 4.3 V typical. The EN pin can be used to adjust the input
voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pull up current source
enables operation when the EN pin is floating. The operating current is 152 μA under no load condition when not
switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩ high side MOSFET supports high efficiency power supply designs capable of delivering 5
A of continuous current to a load. The gate drive bias voltage for the integrated high side MOSFET is supplied
by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54561 reduces the external component
count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a UVLO
circuit which turns off the high side MOSFET when the BOOT to SW voltage falls below a preset threshold.
An automatic BOOT capacitor recharge circuit allows the TPS54561 to operate at high duty cycles approaching
100%. Therefore, the maximum output voltage is near the minimum input supply voltage of the application. The
minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be connected to the pin to adjust the soft start time. A resistor
divider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature
fault, UVLO fault or a disabled condition. When the overload condition is removed, the soft start circuit controls
the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces
the switching frequency during start up and overcurrent fault conditions to help maintain control of the inductor
current.
14
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7.2 Functional Block Diagram
EN
PWRGD
VDD
Shutdown
UV
Enable
Comparator
Logic
Thermal
Shutdown
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Voltage
Reference
Boot
Charge
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Boot
UVLO
PWM
Comparator
FB
SS/TR
Current
Sense
BOOT
Logic
Shutdown
S
Slope
Compensation
SW
COMP
Frequency
Shift
Overload
Recovery
Maximum
Clamp
GND
Oscillator
With PLL
RT/CLK
Thermal Pad
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54561 uses fixed frequency, peak current mode control with adjustable switching frequency. The output
voltage is compared through external resistors connected to the FB pin to an internal voltage reference by an
error amplifier. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
at the COMP pin controls the high side power switch current. When the high side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will
increase and decrease as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.
7.3.2 Slope Compensation Output Current
The TPS54561 adds a compensating ramp to the MOSFET switch current sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of
the high side switch is not affected by the slope compensation and remains constant over the full duty cycle
range.
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7.3.3 Pulse Skip Eco-mode
The TPS54561 operates in a pulse skipping Eco-mode at light load currents to improve efficiency by reducing
switching and gate drive losses. If the output voltage is within regulation and the peak switch current at the end
of any switching cycle is below the pulse skipping current threshold, the device enters Eco-mode. The pulse
skipping current threshold is the peak switch current level corresponding to a nominal COMP voltage of 600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high side MOSFET is inhibited. Since
the device is not switching, the output voltage begins to decay. The voltage control loop responds to the falling
output voltage by increasing the COMP pin voltage. The high side MOSFET is enabled and switching resumes
when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to the
regulated value, and COMP eventually falls below the Eco-mode pulse skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54561 senses and controls peak switch current, not the average load
current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. As the load current approaches zero, the device enters a pulse skip mode during which it draws only
152-μA input quiescent current. The circuit in Figure 8-1 enters Eco-mode at 25-mA output current and with no
external load has an average input current of 280 µA.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
The TPS54561 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and SW
pins provides the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high
side MOSFET is off and the external low side diode conducts. The recommended value of the BOOT capacitor
is 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is
recommended for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high side MOSFET of the TPS54561 will
operate at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1V. When the voltage from
BOOT to SW drops below 2.1 V, the high side MOSFET is turned off and an integrated low side MOSFET pulls
SW low to recharge the BOOT capacitor. To reduce the losses of the small low side MOSFET at high output
voltages, it is disabled at 24 V output and re-enabled when the output reaches 21.5 V.
Since the gate drive current sourced from the BOOT capacitor is small, the high side MOSFET can remain on for
many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycle of
the switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout
is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low side diode
voltage and the printed circuit board resistance.
The start and stop voltage for a typical 5-V output application is shown in Figure 6-25 where the input voltage
is plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output
within 1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty cycle (low dropout) conditions, inductor current ripple increases when the BOOT capacitor
is being recharged resulting in an increase in output voltage ripple. Increased ripple occurs when the off time
required to recharge the BOOT capacitor is longer than the high side off time associated with cycle by cycle
PWM control.
At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1 can be
used to calculate the minimum input voltage for this condition.
VOmax = Dmax × (VVINmin – IOmax × RDS(on) + Vd) – Vd – IOmax × Rdc
(1)
Where:
•
•
•
16
Dmax ≥ 0.9
Vd = Forward Drop of the Catch Diode
Rdc = DC resistance of output inductor
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•
•
•
•
•
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RDS(on) = 1 / (-0.3 × VB2SW2 + 3.577 × VB2SW - 4.246)
VB2SW = VBOOT + Vd
VBOOT = (1.41 × VVIN - 0.554 - Vd × fsw - 1.847 × 103 × IB2SW) / (1.41 + fsw)
fsw = Operating frequency in MHz
IB2SW = 100 × 10-6 A
spacer
7.3.5 Error Amplifier
The TPS54561 voltage regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor and capacitor) are connected between the
error amplifier output COMP pin and GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistor
divider from the output node to the FB pin. Using 1% tolerance or better divider resistors is recommended.
Select the low side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve
efficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator
will be more susceptible to noise and voltage errors from the FB input current may become noticeable.
æ Vout - 0.8V ö
RHS = RLS ´ ç
÷
0.8 V
è
ø
(2)
7.3.7 Enable and Adjusting Undervoltage Lockout
The TPS54561 is enabled when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54561 is disabled when the VIN pin voltage falls below 4 V or when the EN
pin voltage is below 1.2 V. The EN pin has an internal pull-up current source, I1, of 1.2 μA that enables operation
of the TPS54561 when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 7-1 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional
3.4 μA of hysteresis current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the
3.4-μA Ihys current is removed. This additional current facilitates adjustable input voltage UVLO hysteresis. Use
Equation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for
the desired VIN start voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand high
input voltages (that is, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute
maximum voltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using
the EN resistors, the EN pin is clamped internally with a 5.8-V zener diode that will sink up to 150 μA.
- VSTOP
V
RUVLO1 = START
IHYS
RUVLO2 =
(3)
VENA
VSTART - VENA
+ I1
RUVLO1
(4)
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VIN
TPS54561
TPS54561
i1
VIN
ihys
RUVLO1
RUVLO1
EN
EN
10 kW
Node
VEN
5.8 V
RUVLO2
RUVLO2
Copyright © 2017, Texas Instruments Incorporated
Figure 7-1. Adjustable Undervoltage Lockout
(UVLO)
Copyright © 2017, Texas Instruments Incorporated
Figure 7-2. Internal EN Pin Clamp
7.3.8 Soft Start/Tracking Pin (SS/TR)
The TPS54561 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage
as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to
ground implements a soft start time. The TPS54561 has an internal pull-up current source of 1.7 μA that charges
the external soft start capacitor. The calculations for the soft start time (10% to 90%) are shown in Equation 5.
The voltage reference (VREF) is 0.8 V and the soft start current (ISS) is 1.7 μA. The soft start capacitor should
remain lower than 0.47 μF and greater than 0.47 nF.
Css(nF) =
Tss(ms) ´ Iss(m A)
Vref (V) ´ 0.8
(5)
At power up, the TPS54561 will not start switching until the soft start pin is discharged to less than 54 mV to
ensure a proper power up, see Figure 7-3.
Also, during normal operation, the TPS54561 will stop switching and the SS/TR must be discharged to 54 mV,
when the VIN UVLO is exceeded, EN pin pulled below 1.2 V, or a thermal shutdown event occurs.
The FB voltage will follow the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 6-23).
The SS/TR voltage will ramp linearly until clamped at 2.7 V typically as shown in Figure 7-3.
Figure 7-3. Operation of SS/TR Pin when Starting
18
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7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and
PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin
of another device. The sequential method is illustrated in Figure 7-4 using two TPS54561 devices. The power
good is Connected to the EN pin on the TPS54561 which will enable the second power supply once the primary
supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will
provide a 1-ms start up delay. Figure 7-5 shows the results of Figure 7-4.
TPS54561
EN
TPS54561
PWRGD
EN
SS /TR
SS /TR
PWRGD
Copyright © 2017, Texas Instruments Incorporated
Figure 7-4. Schematic for Sequential Start-Up
Sequence
Figure 7-5. Sequential Startup using EN and
PWRGD
TPS54160
TPS54561
3
EN
4
SS/TR
6
PWRGD
TPS54561
TPS54160
3
EN
4
SS/TR
6
PWRGD
Figure 7-7. Ratio-Metric Startup using Coupled
SS/TR pins
Copyright © 2017, Texas Instruments Incorporated
Figure 7-6. Schematic for Ratio-Metric Start-Up
Sequence
Figure 7-6 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the soft start time the pull
up current source must be doubled in Equation 5. Figure 7-7 shows the results of Figure 7-6.
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TPS54561
EN
VOUT 1
SS/TR
PWRGD
TPS54561
VOUT 2
EN
R1
SS/ TR
R2
PWRGD
R3
R4
Copyright © 2017, Texas Instruments Incorporated
Figure 7-8. Schematic for Ratio-Metric and Simultaneous Start-Up Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 7-8 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2
slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and Vout2
at the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
FB offset (VSSOFFSET) in the soft start circuit and the offset created by the pullup current source (Iss) and tracking
resistors, the VSSOFFSET and ISS are included as variables in the equations.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when
Vout2 reaches regulation, use a negative number in Equation 6 through Equation 8 for deltaV. Equation 8 will
result in a positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is
achieved.
Since the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors ensures that the device will restart after a fault. The calculated R1 value
from Equation 6 must be greater than the value calculated in Equation 9 to ensure the device recovers from a
fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSSOFFSET becomes larger
as the soft start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR
pin voltage needs to be greater than 1.5 V for a complete handoff to the internal voltage reference.
20
R1 =
Vout2 + deltaV
Vssoffset
´
VREF
Iss
(6)
R2 =
VREF ´ R1
Vout2 + deltaV - VREF
(7)
deltaV = Vout1 - Vout2
(8)
R1 > 2800 ´ Vout1 - 180 ´ deltaV
(9)
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Figure 7-9. Ratio-Metric Startup with Tracking
Resistors
Figure 7-10. Ratio-Metric Startup with Tracking
Resistors
Figure 7-11. Simultaneous Startup with Tracking Resistor
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54561 is adjustable over a wide range from 100 kHz to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and
must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given
switching frequency, use Equation 10 or Equation 11 or the curves in Figure 6-5 and Figure 6-6. To reduce
the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the
conversion efficiency, maximum input voltage and minimum controllable on time should be considered. The
minimum controllable on time is typically 135 ns which limits the maximum operating frequency in applications
with high input to output step down ratios. The maximum switching frequency is also limited by the frequency
foldback circuit. A more detailed discussion of the maximum switching frequency is provided in the next section.
RT (kW) =
101756
f sw (kHz)1.008
f sw (kHz) =
(10)
92417
RT (kW)0.991
(11)
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7.3.11 Maximum Switching Frequency
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54561
implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin voltage
falls from 0.8 V to 0 V. The TPS54561 uses a digital frequency foldback to enable synchronization to an external
clock during normal start-up and fault conditions. During short-circuit events, the inductor current may exceed
the peak current limit because of the high input voltage and the minimum controllable on time. When the output
voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off time. The
frequency foldback effectively increases the off time by increasing the period of the switching cycle providing
more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current
can be controlled by frequency foldback protection. Equation 13 calculates the maximum switching frequency
at which the inductor current will remain under control when VOUT is forced to VOUT(SC). The selected operating
frequency should not exceed the calculated value.
Equation 12 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value will cause the regulator to
skip switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
æ I ´R + V
dc
OUT + Vd
´ç O
ç VIN - IO ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(12)
fDIV æç ICL ´ Rdc + VOUT(sc ) + Vd
´
tON ç VIN - ICL ´ RDS(on ) + Vd
è
ö
÷
÷
ø
(13)
fSW (max skip ) =
fSW(shift) =
1
tON
IO
Output current
ICL
Current limit
Rdc
Inductor resistance
VIN
Maximum input voltage
VOUT
Output voltage
VOUT(SC)
Output voltage during short
Vd
Diode voltage drop
RDS(on)
Switch on resistance
tON
Controllable on time
ƒDIV
Frequency divide equals (1, 2, 4, or 8)
22
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7.3.12 Synchronization to RT/CLK Pin
The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 7-12. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V
and have a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The
rising edge of the SW will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization
circuit should be designed such that the default frequency set resistor is connected from the RT/CLK pin to
ground when the synchronization signal is off. When using a low impedance signal source, the frequency set
resistor is connected in parallel with an ac coupling capacitor to a termination resistor (that is, 50 Ω) as shown in
Figure 7-12. The two resistors in series provide the default frequency setting resistance when the signal source
is turned off. The sum of the resistance should set the switching frequency close to the external CLK frequency.
AC coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold the TPS54561 switches from the RT resistor
free-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 microseconds. During
the transition from the PLL mode to the resistor programmed mode, the switching frequency will fall to 150 kHz
and then increase or decrease to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to
the RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback to enable synchronizing to an external clock during normal start-up
and fault conditions. Figure 7-13, Figure 7-14, and Figure 7-15 show the device synchronized to an external
system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode
(Eco-Mode).
SPACER
TPS54561
TPS54561
RT/CLK
RT/CLK
PLL
PLL
RT
Clock
Source
Hi-Z
Clock
Source
RT
Copyright © 2017, Texas Instruments Incorporated
Figure 7-12. Synchronizing to a System Clock
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Figure 7-13. Plot of Synchronizing in CCM
Figure 7-14. Plot of Synchronizing in DCM
Figure 7-15. Plot of Synchronizing in Eco-mode
7.3.13 Accurate Current Limit Operation
The TPS54561 implements peak current mode control in which the COMP pin voltage controls the peak current
of the high side MOSFET. A signal proportional to the high side switch current and the COMP pin voltage are
compared each cycle. When the peak switch current intersects the COMP control voltage, the high side switch
is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increases switch
current by driving the COMP pin high. The error amplifier output is clamped internally at a level which sets
the peak switch current limit. The TPS54561 provides an accurate current limit threshold with a typical current
limit delay of 60 ns. With smaller inductor values, the delay will result in a higher peak inductor current. The
relationship between the inductor value and the peak inductor current is shown in Figure 7-16.
24
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Inductor Current (A)
Peak Inductor Current
ΔCLPeak
Open Loop Current Limit
ΔCLPeak = VIN/L x tCLdelay
tCLdelay
tON
Figure 7-16. Current Limit Delay
7.3.14 Power Good (PWRGD Pin)
The PWRGD pin is an open drain output. Once the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is
5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull-up
voltage source when the PWRGD pin is asserted low. A lower pull-up resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V
but with reduced current sinking capability. The PWRGD will achieve full current sinking capability as VIN input
voltage approaches 3 V.
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. Also, PWRGD is pulled low, if UVLO or thermal shutdown are asserted or the EN pin pulled
low.
7.3.15 Overvoltage Protection
The TPS54561 incorporates an output overvoltage protection (OVP) circuit to minimize voltage overshoot when
recovering from output fault conditions or strong unload transients in designs with low output capacitance. For
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable
time, the output of the error amplifier will increase to a maximum voltage corresponding to the peak current
limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier output
transitions to the normal operating level. In some applications, the power supply output voltage can increase
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB
pin voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high side MOSFET is immediately disabled to minimize
output overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the
internal voltage reference, the high side MOSFET resumes normal operation.
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7.3.16 Thermal Shutdown
The TPS54561 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 176°C. The high side MOSFET stops switching when the junction temperature exceeds the thermal trip
threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequence controlled
by discharging the SS/TR pin.
7.3.17 Small Signal Model for Loop Response
Figure 7-17 shows a simplified equivalent model for the TPS54561 control loop which can be simulated to check
the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a
gmEA of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The
resistor Ro and capacitor Co model the open loop gain and frequency response of the amplifier. The 1-mV
ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response
measurements. Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b
provides the small signal response of the overall loop. The dynamic loop response can be evaluated by
replacing RL with a current source with the appropriate load step amplitude and step rate in a time domain
analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation.
SW
VO
Power Stage
gmps 17 A/V
a
b
RESR
R1
RL
COMP
c
0.8 V
R3
C2
CO
RO
FB
COUT
gmea
R2
350 mA/V
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 7-17. Small Signal Model for Loop Response
7.3.18 Simple Small Signal Model for Peak Current Mode Control
Figure 7-18 describes a simple small signal model that can be used to design the frequency compensation.
The TPS54561 power stage can be approximated by a voltage-controlled current source (duty cycle modulator)
supplying current to the output capacitor and load resistor. The control to output transfer function is shown
in Equation 14 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the
change in switch current and the change in COMP pin voltage (node c in Figure 7-17) is the power stage
transconductance, gmPS. The gmPS for the TPS54561 is 17 A/V. The low-frequency gain of the power stage is
the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively.
This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with
the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 7-18. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same with varying load conditions. The type of output capacitor chosen determines
whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum
electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the
overall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 17).
26
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VO
Adc
VC
RESR
fp
RL
gmps
COUT
fz
Figure 7-18. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
VOUT
VC
æ
s ö
ç1 +
÷
2
p
´ fZ ø
= Adc ´ è
æ
s ö
ç1 +
÷
2p ´ fP ø
è
(14)
Adc = gmps ´ RL
fP =
fZ =
(15)
1
COUT ´ RL ´ 2p
(16)
1
COUT ´ RESR ´ 2p
(17)
7.3.19 Small Signal Model for Frequency Compensation
The TPS54561 uses a transconductance amplifier for the error amplifier and supports three of the commonlyused frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in
Figure 7-19. Type 2 circuits are typically implemented in high bandwidth power-supply designs using low ESR
output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small
signal model in Figure 7-19. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 7-19. See the application section for a design example using a Type 2A network with a low ESR output
capacitor.
Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software tools
to create a design based on the power supply requirements.
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VO
R1
FB
gmea
Type 2A
COMP
Type 2B
Type 1
Vref
R2
RO
R3
CO
C2
R3
C2
C1
C1
Copyright © 2016, Texas Instruments Incorporated
Figure 7-19. Types of Frequency Compensation
Aol
P1
A0
Z1
P2
A1
BW
Figure 7-20. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Ro =
CO =
Aol(V/V)
gmea
(18)
gmea
2p ´ BW (Hz)
(19)
æ
ö
s
ç1 +
÷
2p ´ fZ1 ø
è
EA = A0 ´
æ
ö æ
ö
s
s
ç1 +
÷ ´ ç1 +
÷
2p ´ fP1 ø è
2p ´ fP2 ø
è
A0 = gmea ´ Ro ´
R2
R1 + R2
A1 = gmea ´ Ro| | R3 ´
28
(20)
(21)
R2
R1 + R2
(22)
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P1 =
Z1 =
P2 =
P2 =
P2 =
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1
2p ´ Ro ´ C1
(23)
1
2p ´ R3 ´ C1
(24)
1
type 2a
2p ´ R3 | | RO ´ (C2 + CO )
(25)
1
type 2b
2p ´ R3 | | RO ´ CO
(26)
1
type 1
2 p ´ R O ´ (C2 + C O )
(27)
7.4 Device Functional Modes
The TPS54561 is designed to operate with input voltages above 4.5 V. When the VIN voltage is above the 4.3 V
typical rising UVLO threshold and the EN voltage is above the 1.2 V typical threshold the device is active. If the
VIN voltage falls below the typical 4-V UVLO turn off threshold the device stops switching. If the EN voltage falls
below the 1.2-V threshold the device stops switching and enters a shutdown mode with low supply current of 2
µA typical.
The TPS54561 will operate in CCM when the output current is enough to keep the inductor current above 0 A
at the end of each switching period. As a non-synchronous converter it will enter DCM at low output currents
when the inductor current falls to 0 A before the end of a switching period. At very low output current the COMP
voltage will drop to the pulse skipping threshold and the device operates in a pulse-skipping Eco-mode. In this
mode the high-side MOSFET does not switch every switching period. This operating mode reduces power loss
while keeping the output voltage regulated. For more information on Eco-mode see Section 7.3.3.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS54561 device is a 60-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher dc voltage to a lower dc voltage with a maximum available output current of 5 A.
Example applications are: 12-V, 24-V, and 48-V industrial, automotive and communication power systems. Use
the following design procedure to select component values for the TPS54561 device. The Excel® spreadsheet
(SLVC452) located on the product page can help on all calculations. Alternatively, use the WEBENCH software
to generate a complete design. The WEBENCH software uses an interactive design procedure and accesses a
comprehensive database of components when generating a design.
8.2 Typical Applications
8.2.1 Buck Converter for 7-V to 60-V Input to 5-V at 5-A Output
PWRGD
PWRGD PULL UP
R8
3
C10
2.2µF
C3
2.2µF
C1
2.2µF
C2
2.2µF
R1
442k
5
SS/TR
2
J2
C11
4
R3
243k
TP2
7
GND
C13
0.01µF
2
1
GND
R2
90.9k
2
1
EN
GND
PWRGD
EN
BOOT
RT/CLK
SW
SS/TR
COMP
FB
GND
PAD
TPS54561DPR
C8
47pF
10
TP9
C4
1
L1
5V@5A
0.1µF
9
6
TP5
FB
TP6
7447798720
7.2µH
8
D1
PDS760-13
C6
47µF
C7
47µF
GND
C9
47µF
TP7
R7
49.9
+
C12
DNP
TP8
1
VOUT
2
GND
J1
GND
TP4
R5
53.6k
C5
4700pF
J4
GND
R4
16.9k
VIN
1
+
DNP
2
2
TP1
3
1
TP10 1.00k
2
2
1
VIN
GND
U1
1
7 V to 60 V
GND
J3
FB
R6
10.2k
TP3
GND
GND
2 SS/TR
1
SS/TR
GND
J5
Copyright © 2017, Texas Instruments Incorporated
GND
Figure 8-1. 5-V Output TPS54561 Design Example
8.2.1.1 Design Requirements
Figure 8-1 illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined
at the system level. Calculations can be done with the aid of WEBENCH or the excel spreadsheet (SLVC452)
located on the product page. This example is designed to the following known parameters:
Table 8-1. Design Parameters
PARAMETER
30
VALUE
Output Voltage
5V
Transient response 1.25 A to 3.75 A load step
ΔVOUT = 4 %
Maximum output current
5A
Input voltage
12 V nom. 7 V to 60 V
Output voltage ripple
0.5% of VOUT
Start input voltage (rising VIN)
6.5 V
Stop input voltage (falling VIN)
5V
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Selecting the Switching Frequency
The first step is to choose a switching frequency for the regulator. Typically, the designer uses the highest
switching frequency possible since this produces the smallest solution size. High switching frequency allows
for lower value inductors and smaller output capacitors compared to a power supply that switches at a lower
frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power
switch, the input voltage, the output voltage and the frequency foldback protection.
Equation 12 and Equation 13 should be used to calculate the upper limit of the switching frequency for the
regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values
results in pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54561. For this example, the output voltage is 5 V and
the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 708 kHz to avoid pulse
skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits use Equation 13
to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage
of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 11 mΩ, switch resistance of 87 mΩ, a current
limit value of 6 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 855 kHz.
For this design, a lower switching frequency of 400 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in
Figure 6-6. The switching frequency is set by resistor R3 shown in Figure 8-1. For 400-kHz operation, the closest
standard value resistor is 243 kΩ.
fSW(max skip) =
fSW(shift) =
RT (kW) =
1
æ 5 A x 11 mW + 5 V + 0.7 V ö
´ ç
÷ = 708 kHz
135 ns
è 60 V - 5 A x 87 mW + 0.7 V ø
8
æ 6 A x 11 mW + 0.1 V + 0.7 V ö
´ ç
÷ = 855 kHz
135 ns
è 60 V - 6 A x 87 mW + 0.7 V ø
101756
400 (kHz)1.008
(28)
(29)
= 242 kW
(30)
8.2.1.2.3 Output Inductor Selection (LO)
To calculate the minimum value of the output inductor, use Equation 31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents
impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to
or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer,
however, the following guidelines may be used.
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For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA
for stable PWM operation. In a wide input voltage regulator, it is best to choose relatively large inductor ripple
current. This provides sufficienct ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 7.6 μH. The nearest standard
value is 7.2 μH. It is important that the RMS current and saturation current ratings of the inductor not be
exceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this
design, the RMS inductor current is 5 A and the peak inductor current is 5.8 A. The chosen inductor is a WE
7447798720, which has a saturation current rating of 7.9 A and an RMS current rating of 6 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power
up, faults or transient load conditions, the inductor current can increase above the peak inductor current level
calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the
device. For this reason, the most conservative design approach is to choose an inductor with a saturation current
rating equal to or greater than the switch current limit of the TPS54561 which is nominally 7.5 A.
LO(min ) =
VIN(max ) - VOUT
IOUT ´ KIND
´
VOUT
60 V - 5 V
5V
=
´
= 7.6 mH
VIN(max ) ´ fSW
5 A x 0.3
60 V ´ 400 kHz
(31)
spacer
IRIPPLE =
VOUT ´ (VIN(max ) - VOUT )
VIN(max ) ´ LO ´ fSW
=
5 V x (60 V - 5 V)
= 1.591 A
60 V x 7.2 mH x 400 kHz
(32)
spacer
(
æ
1 ç VOUT ´ VIN(max ) - VOUT
2
IL(rms ) = (IOUT ) +
´ç
12 ç
VIN(max ) ´ LO ´ fSW
è
)÷ö
2
÷ =
÷
ø
2
(5 A ) +
2
æ
5 V ´ (60 V - 5 V ) ö
1
´ ç
÷ =5A
ç 60 V ´ 7.2 mH ´ 400 kHz ÷
12
è
ø
spacer
IL(peak ) = IOUT +
IRIPPLE
1.591 A
= 5A +
= 5.797 A
2
2
(34)
8.2.1.2.4 Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the increased load current until the regulator responds to the load step. The regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough
to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current,
ƒsw is the regulators switching frequency and ΔVOUT is the allowable change in the output voltage. For this
32
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example, the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75
A. Therefore, ΔIOUT is 3.75 A - 1.25 A = 2.5 A and ΔVOUT = 0.04 × 5 = 0.2 V. Using these numbers gives
a minimum capacitance of 62.5 μF. This value does not take the ESR of the output capacitor into account in
the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum
electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high
to low load current. The catch diode of the regulator cannot sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. A typical load step response
is shown in Figure 8-6. The excess energy absorbed in the output capacitor will increase the voltage on the
capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods.
Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired
value, where LO is the value of the inductor, IOH is the output current under heavy load, IOL is the output under
light load, Vf is the peak output voltage, and Vi is the initial voltage. For this example, the worst case load step
will be from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum
in our specification is 4 % of the output voltage. This makes Vf = 1.04 × 5 = 5.2. Vi is the initial capacitor voltage
which is the nominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of
44.1 μF.
Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is
the inductor ripple current. Equation 37 yields 19.9 μF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the ESR should be less than 15.7 mΩ.
The most stringent criteria for the output capacitor is 62.5 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, 3 x
47 μF, 10-V ceramic capacitors with 5 mΩ of ESR will be used. The derated capacitance is 87.4 µF, well above
the minimum required capacitance of 62.5 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple
current. Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For
this example, Equation 39 yields 459 mA.
COUT >
2 ´ DIOUT
2 ´ 2.5 A
=
= 62.5 mF
fSW ´ DVOUT 400 kHz x 0.2 V
((I ) - (I ) ) = 7.2 mH x (3.75 A - 1.25 A ) = 44.1 mF
x
(5.2 V - 5 V )
((V ) - (V ) )
2
OH
COUT > LO
2
2
2
OL
2
f
COUT >
(35)
2
2
2
I
(36)
1
1
1
1
´
=
= 19.9 mF
x
8 ´ fSW æ VORIPPLE ö 8 x 400 kHz
æ 25 mV ö
ç 1.591 A ÷
ç
÷
è
ø
è IRIPPLE ø
(37)
V
25 mV
RESR < ORIPPLE =
= 15.7 mW
IRIPPLE
1.591 A
ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT
)=
12 ´ VIN(max ) ´ LO ´ fSW
(38)
5V ´
(60 V
- 5 V)
12 ´ 60 V ´ 7.2 mH ´ 400 kHz
= 459 mA
(39)
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8.2.1.2.5 Catch Diode
The TPS54561 requires an external catch diode between the SW pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be greater than
the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low
forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum
of 60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54561.
For the example design, the PDS760 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the PDS760 is 0.52 V at 5 A.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied
by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are
due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 is
used to calculate the total power dissipation, including conduction losses and ac losses of the diode.
The PDS760 diode has a junction capacitance of 180 pF. Using Equation 40, the total loss in the diode at the
nominal input voltage is 1.65 Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode which has a low leakage current and slightly higher forward voltage drop.
PD =
(VIN(max ) - VOUT ) ´ IOUT ´ Vf d
VIN(max )
(12 V
- 5 V ) ´ 5 A x 0.52 V
12 V
2
+
+
C j ´ fSW ´ (VIN + Vf d)
2
=
180 pF x 400 kHz x (12 V + 0.52 V)2
= 1.65 W
2
(40)
8.2.1.2.6 Input Capacitor
The TPS54561 requires a high quality ceramic type X5R or X7R input decoupling capacitor with at least 3 μF of
effective capacitance. Some applications will benefit from additional bulk capacitance. The effective capacitance
includes any loss of capacitance due to dc bias effects. The voltage rating of the input capacitor must be greater
than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum
input current ripple of the TPS54561. The input ripple current can be calculated using Equation 41.
The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the dc bias. The effective value of a capacitor decreases as the dc
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V. For this example, four 2.2 μF, 100 V capacitors in parallel are used. Table 8-2 shows several
choices of high voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 42. Using the design example values, IOUT = 5 A, CIN = 8.8 μF, ƒsw = 400 kHz, yields
an input voltage ripple of 355 mV and a rms input ripple current of 2.26 A.
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ICI(rms ) = IOUT x
VOUT
x
VIN(min )
(V
IN(min ) - VOUT
VIN(min )
) = 5A
5V
´
7V
(7 V
- 5 V)
7V
= 2.26 A
(41)
I
´ 0.25
5 A ´ 0.25
DVIN = OUT
=
= 355 mV
CIN ´ fSW
8.8 mF ´ 400 kHz
(42)
Table 8-2. Capacitor Types
VENDOR
VALUE (μF)
1 to 2.2
Murata
1 to 4.7
1
1 to 2.2
1 to 1.8
Vishay
1 to 1.2
1 to 3.9
1 to 1.8
1 to 2.2
TDK
1.5 to 6.8
1 to 2.2
1 to 3.3
1 to 4.7
AVX
1
1 to 4.7
1 to 2.2
EIA Size
1210
1206
2220
2225
1812
1210
1210
1812
VOLTAGE
DIALECTRIC
100 V
COMMENTS
GRM32 series
50 V
100 V
GRM31 series
50 V
50 V
100 V
VJ X7R series
50 V
100 V
100 V
50 V
100 V
50 V
X7R
C series C4532
C series C3225
50 V
100 V
50 V
X7R dielectric series
100 V
8.2.1.2.7 Slow Start Capacitor
The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54561 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 43 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the effective output capacitance of 87 µF up to 5 V with an
average current of 1 A requires a 0.3 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 5. For the
example circuit, the slow start time is not too critical since the output capacitor value is 3 x 47 μF which does
not require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value
of 3.5 ms which requires a 9.3-nF slow start capacitor calculated by Equation 44. For this design, the next larger
standard value of 10 nF is used.
tss >
Cout ´ Vout ´ 0.8
Issavg
Css(nF) =
(43)
Tss(ms) ´ Iss(μA)
3.5 ms ´ 1.7 μA
=
= 9.3 nF
Vref (V) ´ 0.8
(0.8 V x 0.8)
(44)
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8.2.1.2.8 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 10 V or higher
voltage rating.
8.2.1.2.9 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54561. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and
start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5 V (UVLO stop).
Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between Vin
and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary.
For the example application, a 442 kΩ between VIN and EN (RUVLO1) and a 90.9 kΩ between EN and ground
(RUVLO2) are required to produce the 6.5 V and 5 V start and stop voltages.
(45)
RUVLO2 =
VENA
1.2 V
=
= 90.9 kW
VSTART - VENA
6.5 V - 1.2 V
+
m
1.2
A
+ I1
442 kW
RUVLO1
(46)
8.2.1.2.10 Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network should be greater than 1 μA to maintain
the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ. Choosing
higher resistor values decreases quiescent current and improves efficiency at low output currents but may also
introduce noise immunity problems.
RHS = RLS x
VOUT - 0.8 V
æ 5 V - 0.8 V ö
= 10.2 kW x ç
÷ = 53.5 kW
0.8 V
0.8 V
è
ø
(47)
8.2.1.2.11 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy
to calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual crossover frequency will be lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least 10 times greater the modulator pole.
To get started, the modulator pole, ƒp(mod), and the ESR zero, ƒz1 must be calculated using Equation 48 and
Equation 49. For COUT, use a derated value of 87.4 μF. Use equations Equation 50 and Equation 51 to estimate
a starting point for the crossover frequency, ƒco. For the example design, ƒp(mod) is 1821 Hz and ƒz(mod) is
1100 kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the
mean of modulator pole and half of the switching frequency. Equation 50 yields 44.6 kHz and Equation 51 gives
19.1 kHz. Use the geometric mean value of Equation 50 and Equation 51 for an initial crossover frequency. For
this example, after lab measurement, the crossover frequency target was increased to 30 kHz for an improved
transient response.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
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fP(mod) =
f Z(mod) =
IOUT(max )
=
2 ´ p ´ VOUT ´ COUT
1
=
2 ´ p ´ RESR ´ COUT
fco1 =
fp(mod) x f z(mod) =
fco2 =
fp(mod) x
fSW
2
=
5A
= 1821 Hz
2 ´ p ´ 5 V ´ 87.4 mF
1
= 1100 kHz
2 ´ p ´ 1.67 mW ´ 87.4 mF
1821 Hz x 1100 kHz
1821 Hz x
400 kHz
2
= 44.6 kHz
= 19.1 kHz
(48)
(49)
(50)
(51)
To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance,
gmps, is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5
V, 0.8 V, and 350 μA/V, respectively. R4 is calculated to be 16.8 kΩ and a standard value of 16.9 kΩ is selected.
Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5172 pF for
compensating capacitor C5. 4700 pF is used for this design.
ö
VOUT
æ 2 ´ p ´ fco ´ COUT ö æ
ö
5V
æ 2 ´ p ´ 29.2 kHz ´ 87.4 mF ö æ
R4 = ç
÷ = ç
÷ x ç
÷ x ç 0.8 V x 350 mA / V ÷ = 16.8 kW
gmps
V
x
gmea
17
A
/
V
è
ø è
ø
è
ø è REF
ø
(52)
C5 =
1
1
=
= 5172 pF
2 ´ p ´ R4 x fp(mod)
2 ´ p ´ 16.9 kW x 1821 Hz
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set
the compensation pole. The selected value of C8 is 47 pF for this design example.
C8 =
COUT x RESR
87.4 mF x 1.67 mW
=
= 8.64 pF
R4
16.9 kW
(54)
C8 =
1
1
=
= 47.1 pF
R4 x f sw x p
16.9 kW x 400 kHz x p
(55)
8.2.1.2.12 Power Dissipation Estimate
The following formulas show how to estimate the TPS54561 power dissipation under continuous conduction
mode (CCM) operation. These equations should not be used if the device is operating in discontinuous
conduction mode (DCM).
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD)
and supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design
example.
æV
ö
5V
2
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 87 mW ´
= 0.958 W
12 V
è VIN ø
(56)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W
(57)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W
(58)
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spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W
(59)
Where:
IOUT is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
VOUT is the output voltage (V).
VIN is the input voltage (V).
fsw is the switching frequency (Hz).
trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
QG is the total gate charge of the internal MOSFET
IQ is the operating nonswitching supply current
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W
(60)
For given TA,
TJ = TA + RTH ´ PTOT
(61)
For given TJMAX = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT
(62)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
RTH is the thermal resistance from junction to ambient for a given PCB layout (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).
There will be additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode
and PCB trace resistance impacting the overall efficiency of the regulator.
8.2.1.2.13 Safe Operating Area
The safe operating area (SOA) of a typical design is shown in Figure 8-2, through Figure 8-5 for 3.3-V, 5-V and
12-V outputs and varying amounts of forced air flow. The temperature derating curves represent the conditions
at which the internal components and external components are at or below the manufacturer’s maximum
operating temperatures. Derating limits apply to devices soldered directly to a double-sided PCB with 2 oz.
copper, similar to the EVM. Careful attention must be paid to the other components chosen for the design,
especially the catch diode. In most applications the thermal performance will be limited by the catch diode. When
operating with high duty cycles, higher input voltage or at higher switching frequency the TPS54561's thermal
performance can become the limiting factor.
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90
90
80
80
70
70
60
60
TA (ƒC)
TA (ƒC)
www.ti.com
50
6V
12 V
24 V
36 V
48 V
60 V
40
30
20
0.0
0.5
1.0
30
20
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
80
70
70
60
60
TA (ƒC)
80
50
18 V
24 V
36 V
48 V
60 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
C048
Figure 8-3. 5-V Output with 400-kHz Switching
Frequency
90
20
1.0
IOUT (Amps)
90
30
0.5
C047
Figure 8-2. 3.3-V Output with 400-kHz Switching
Frequency
40
8V
12 V
24 V
36 V
48 V
60 V
40
IOUT (Amps)
TA (ƒC)
50
50
400 LFM
40
200 LFM
30
100 LFM
Nat Conv
20
1.5
2.0
2.5
3.0
IOUT (Amps)
3.5
4.0
4.5
0.0
5.0
0.5
Figure 8-4. 12-V Output with 800-kHz Switching
Frequency
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
IOUT (Amps)
C048
VIN = 36 V
VO = 12 V
C048
fsw = 800 kHz
Figure 8-5. Air Flow Conditions
8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 410 mA. The power supply enters Eco-mode when the output current is lower than 25 mA. The input
current draw is 280 μA with no load.
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8.2.1.3 Application Curves
1 A/div
10 V/div
Measurements are taken with standard EVM using a 12-V input, 5-V output, and 5-A load unless otherwise
noted.
VIN
10 mV/div
200 mV/div
IOUT
VOUT ±5V offset
VOUT ±5V offset
Time = 4 ms/div
Time = 100 Ps/div
Figure 8-7. Line Transient (8 V to 40 V)
Figure 8-6. Load Transient
1 V/div
VIN
VOUT
2 V/div
EN
SS/TR
VOUT
PGOOD
5 V/div
4 V/div
1 V/div
5 V/div
2 V/div
EN
Time = 2 ms/div
Time = 2 ms/div
Figure 8-9. Start-up With EN
Figure 8-8. Start-up With VIN
10 V/div
500 mA/div
IL
SW
IL
10 mV/div
10 mV/div
1 A/div
10 V/div
SW
VOUT ± AC Coupled
VOUT ± AC Coupled
Time = 4 Ps/div
Time = 4 Ps/div
Figure 8-10. Output Ripple CCM
40
Figure 8-11. Output Ripple DCM
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10 V/div
1 m\A/div
10 V/div
IL
IL
200 mV/div
10 mV/div
200 mA/div
SW
SW
VOUT ± AC Coupled
VIN ± AC Coupled
Time = 1 ms/div
Time = 4 Ps/div
Figure 8-12. Output Ripple PSM
10 V/div
2 V/div
SW
Figure 8-13. Input Ripple CCM
SW
IL
VOUT
20 mV/div
10 mV/div
200 mA/div
500 mA/div
IL
VIN ± AC Coupled
Time = 4 Ps/div
Time = 40 Ps/div
Figure 8-14. Input Ripple DCM
Figure 8-15. Low Dropout Operation
IOUT = 1 A
EN Floating
2 V/div
2 V/div
IOUT = 100 mA
EN Floating
VIN
VOUT
VIN
VOUT
Time = 40 ms/div
Time = 40 ms/div
Figure 8-16. Low Dropout Operation
Figure 8-17. Low Dropout Operation
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100
100
95
90
80
70
Efficiency (%)
Efficiency (%)
90
85
80
75
60
50
40
30
VOUT = 5 V, fsw = 400 kHz
70
65
60
0
VIN =7V
7V
VIN =12V
12 V
VIN =24V
24 V
VIN =36V
36 V
VIN =48V
48 V
VIN =60V
60 V
1
2
3
4
10
0
0.001
0.00
5
IO - Output Current (A)
VIN = 7V
7V
VIN = 12
V
12V
VIN = 24V
24 V
VIN = 36
V
36V
VIN = 48
V
48V
VIN = 60V
60 V
0.01
0.10
1.00
IO - Output Current (A)
C024
Figure 8-18. Efficiency vs Load Current
C024
Figure 8-19. Light Load Efficiency
100
100
95
90
80
90
70
Efficiency (%)
Efficiency (%)
VOUT = 5 V, fsw = 400 kHz
20
85
80
75
60
50
VIN = 6V
6V
VIN =12V
12 V
VIN =24v
24 V
VIN =36v
36 V
VIN =48V
48 V
VIN =60V
60 V
40
30
70
VOUT = 3.3 V, fsw = 400 kHz
65
60
0
VIN = 6V
6V
VIN = 12V
12 V
VIN = 24V
24 V
VIN = 36V
36 V
VIN = 48V
48 V
VIN = 60V
60 V
1
2
3
4
20
10
5
IO - Output Current (A)
VOUT = 3.3 V, fsw = 400 kHz
0
0.001
0.00
0.01
0.10
IO - Output Current (A)
C024
1.00
C024
Figure 8-21. Light Load Efficiency
Figure 8-20. Efficiency vs Load Current
100
60
180
95
Phase
40
120
75
VIN 18in
= 18 V
VINSeries1
= 24 V
VINSeries3
= 36 V
VINSeries6
= 48 V
VINSeries8
= 60 V
65
60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
IO - Output Current (A)
VOUT = 12 V
60
0
0
±20
±60
±40
±120
VIN = 12 V, VOUT = 5 V, IOUT = 5 A, fSW = 400 kHz
5
C024
±60
10
100
1k
10k
±180
100k
Frequency (Hz)
fsw = 800 kHz
Figure 8-22. Efficiency vs Output Current
Phase (£)
80
70
42
Gain
20
85
Gain (dB)
Efficiency (%)
90
C053
Figure 8-23. Overall Loop Frequency Response
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0.10
0.10
0.08
0.08
Output Voltage Deviation (%)
Output Voltage Deviation (%)
www.ti.com
0.06
0.04
0.02
0.00
±0.02
±0.04
±0.06
±0.08
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.04
0.02
0.00
±0.02
±0.04
±0.06
±0.08
VIN = 12 V, VOUT = 5 V, fsw = 400 kHz
±0.10
0.06
VOUT = 5 V, IOUT = 2.5 A, fsw = 400 kHz
±0.10
4.0
4.5
IO - Output Current (A)
5.0
5
Figure 8-24. Regulation vs Load Current
10
15
20
25
30
35
40
45
50
55
VI - Input Voltage (V)
C024
60
C024
Figure 8-25. Regulation vs Input Voltage
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8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output
VIN
+
Cin
Cboot
Lo
BOOT
VIN
Cd
SW
GND
R1
+
GND
Co
R2
TPS54561
FB
VOUT
EN
COMP
SS/TR
Rcomp
RT/CLK
Css
Czero
RT
Cpole
Copyright © 2017, Texas Instruments Incorporated
Figure 8-26. TPS54561 Inverting Power Supply From Application Note
8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
VOPOS
+
VIN
Copos
+
Cin
Cboot
BOOT
VIN
GND
SW
Lo
Cd
R1
GND
+
Coneg
R2
TPS54561
VONEG
FB
EN
COMP
SS/TR
Rcomp
RT/CLK
Css
RT
Czero
Cpole
Copyright © 2017, Texas Instruments Incorporated
Figure 8-27. TPS54561 Split Rail Power Supply Based on the Application Note
9 Power Supply Recommendations
The design of the device is for operation from an power supply range between 4.5 V and 60 V. Good regulation
of this power supply is essential. If the power supply is more distant than a few inches from the TPS54561
converter, the circuit may require additional bulk capacitance besides the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 µF is a typical choice.
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10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR
ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed
by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 10-1 for a PCB
layout example. The GND pin should be tied directly to the thermal pad under the IC.
The thermal pad should be connected to internal PCB ground planes using multiple vias directly under the
IC. The SW pin should be routed to the cathode of the catch diode and to the output inductor. Since the SW
connection is the switching node, the catch diode and output inductor should be located close to the SW pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full
rated load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive
to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths
of trace. The additional external components can be placed approximately as shown. It may be possible to
obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce
good results and is meant as a guideline.
10.2 Layout Example
VOUT
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Route Boot Capacitor
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
VIN
UVLO
Adjust
Resistors
BOOT
Catch
Diode
PWRGD
VIN
SW
EN
GND
SS/TR
RT/CLK
COMP
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Soft-Start
Capacitor
Frequency
Set Resistor
Signal VIA
Figure 10-1. PCB Layout Example
10.3 Estimated Circuit Area
Boxing in the components in the design of Figure 8-1 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the TPS54560, TPS54561, and TPS54561-Q1 family Excel design tool, see SLVC452.
11.1.1.1 Custom Design with WEBENCH® Tools
Click here to create a custom design using the TPS54561 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT, and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with
real time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand the thermal performance of your board
• Export your customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
• Evaluation Module for the TPS54561 Step-Down Converter, SLVU993
• Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511, SLVA464
• Creating GSM /GPRS Power Supply from TPS54260, SLVA412)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
Eco-mode™ and TI E2E™ are trademarks of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation.
WEBENCH® are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
46
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Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54561
TPS54561
www.ti.com
SLVSBO1G – JULY 2013 – REVISED JUNE 2021
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS54561
47
PACKAGE OPTION ADDENDUM
www.ti.com
10-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54561DPRR
ACTIVE
WSON
DPR
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54561
TPS54561DPRT
ACTIVE
WSON
DPR
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54561
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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