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TPS54610
SLVS398H – JUNE 2001 – REVISED OCTOBER 2015
TPS54610 3-V to 6-V Input, 6-A Output Synchronous Buck PWM Switcher with Integrated
FETs
1 Features
3 Description
•
The TPS54610 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the
substrate with the listed features are a true, high
performance, voltage error amplifier that enables
maximum performance and flexibility in choosing the
output filter L and C components; an undervoltagelockout circuit to prevent start-up until the input
voltage reaches 3 V; an internally or externally set
slow-start circuit to limit inrush currents; and a power
good output useful for processor/logic reset, fault
signaling, and supply sequencing.
1
•
•
•
•
•
•
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source or
Sink Current
Adjustable Output Voltage Down to 0.9 V With
1.0% Accuracy
Wide PWM Frequency: Fixed 350 kHz, 550 kHz
or Adjustable 280 kHz to 700 kHz
Synchronizable to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
SWIFT Documentation, Application Notes, and
Design Software: www.ti.com/swift
2 Applications
•
•
•
•
Low-Voltage, High-Density Distributed Power
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
The TPS54610 is available in a thermally enhanced
28-pin HTSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules to aid in quickly achieving high-performance
power supply designs to meet aggressive equipment
development cycles.
Device Information (1)
DEVICE NAME
(1)
Efficiency at 350 kHz
100
PH
95
TPS54610
BOOT
90
85
VBIAS
AGND COMP
Efficiency − %
PGND
VSENSE
9.70 mm x 6.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Output
VIN
BODY SIZE (NOM)
HTSSOP (28)
Simplified Schematic
Input
PACKAGE
TPS54610
80
75
70
65
VI = 5 V,
VO = 3.3 V
60
55
50
0
1
2
3
4
5
6
Load Current − A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54610
SLVS398H – JUNE 2001 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
5
5
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 20
11.3 Thermal Considerations ........................................ 21
12 Device and Documentation Support ................. 22
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (October 2015) to Revision H
•
Editorial changes only; no technical changes ....................................................................................................................... 1
Changes from Revision F (April 2007) to Revision G
•
2
Page
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLVS398H – JUNE 2001 – REVISED OCTOBER 2015
5 Device Comparison Table
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
TPS54611
0.9 V
TPS54614
1.8 V
TPS54672
DDR
Memory/Adjustable
TPS54612
1.2 V
TPS54615
2.5 V
TPS54673
Pre-bias/Adjustable
TPS54613
1.5 V
TPS54616
3.3 V
TPS54680
Sequencing/Adjustable
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
Pin Functions
PIN
TYPE (1)
DESCRIPTION
1
G
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS
capacitor, RT resistor and SYNC pin. Connect PowerPAD™ to AGND.
BOOT
5
S
Bootstrap output. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH
generates floating drive for the high-side FET driver.
COMP
3
PGND
15-19
G
Power ground. High current return for the low-side driver and power MOSFET. Connect
PGND with large copper areas to the input and output supply returns, and negative pins of
the input and output capacitors. A single point connection to AGND is recommended.
PH
6-14
O
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output
inductor.
PWRGD
4
O
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low.
Note that output is low when SS/ENA is low or the internal shutdown signal is active.
RT
28
I
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching
frequency. When using the SYNC pin, set the RT value for a frequency at or slightly lower
than the external oscillator frequency.
SS/ENA
26
I/O
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable
device operation and capacitor input to externally set the start-up time.
SYNC
27
I/O
Synchronization input. Dual function pin which provides logic input to synchronize to an
external oscillator or pin select between two internally set switching frequencies. When used
to synchronize to an external signal, a resistor must be connected to the RT pin.
VBIAS
25
S
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS
pin to AGND pin with a high quality, low-ESR 0.1-μF to 1.0-μF ceramic capacitor.
NAME
NO.
AGND
(1)
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
I = Input, O = Output, S = Supply, G = Ground Return
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Pin Functions (continued)
PIN
NAME
TYPE (1)
DESCRIPTION
20-24
I
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to
PGND pins close to device package with a high quality, low-ESR 10-μF ceramic capacitor.
2
I
Error amplifier inverting input. Connect to output voltage through compensation
network/output divider.
NO.
VIN
VSENSE
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1)
VI
Input voltage
VO
Output voltage
MIN
MAX
UNIT
VIN, SS/ENA, SYNC
–0.3
7
V
RT
–0.3
6
V
VSENSE
–0.3
4
V
BOOT
–0.3
17
V
VBIAS, COMP, PWRGD
–0.3
7
V
PH
–0.6
10
V
–2
V
PH (transient < 10 ns)
IO
Source current
IS
Sink current
PH
Internally Limited
COMP, VBIAS
6
PH
12
A
COMP
6
mA
10
mA
SS/ENA, PWRGD
Voltage differential
AGND to PGND
mA
–0.3
0.3
V
TJ
Operating virtual junction temperature
–40
125
°C
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
Human body model (HBM) per ANSI/ESDA/JEDEC JS001, all pins (1)
–2000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
–1500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Input voltage, VI
Operating junction temperature, TJ
4
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NOM
MAX
UNIT
3
6
V
–40
125
°C
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7.4 Thermal Information
TPS54610
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
31.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.3
°C/W
RθJB
Junction-to-board thermal resistance
15.1
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
7.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
Quiescent current
3
6
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
11
15.8
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
16
23.5
Shutdown, SS/ENA = 0 V
1
1.4
2.95
3.0
V
mA
UNDERVOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
μs
Rising and falling edge deglitch, UVLO (1)
V
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS) = 0
2.70
2.80
(2)
2.90
V
100
μA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (2)
Load regulation (1)
(3)
(3)
IL = 3 A, fs = 350 kHz, TJ = 85°C
0.04
IL = 3 A, fs = 550 kHz, TJ = 85°C
0.04
IL = 0 A to 6 A, fs = 350 kHz, TJ = 85°C
0.03
IL = 0 A to 6 A, fs = 550 kHz, TJ = 85°C
0.03
%/V
%/A
OSCILLATOR
Internally set—free running frequency
SYNC ≤ 0.8 V, RT open
280
350
420
SYNC ≥ 2.5 V, RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
460
500
540
663
700
762
Externally set—free running frequency range RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND) (1)
High level threshold, SYNC
2.5
Low level threshold, SYNC
50
Frequency range, SYNC (1)
(1)
(2)
(3)
330
kHz
V
0.8
Pulse duration, external synchronization,
SYNC (1)
kHz
V
ns
700
kHz
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 10
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Electrical Characteristics (continued)
over operating free-air temperature range unless otherwise noted
PARAMETER
Ramp valley
TEST CONDITIONS
MIN
TYP
MAX
0.75
(1)
Ramp amplitude (peak-to-peak) (1)
V
1
Minimum controllable on time (1)
V
200
Maximum duty cycle
UNIT
ns
90%
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND (1)
90
110
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (1)
3
5
Error amplifier common mode input voltage
range
Powered by internal LDO (1)
0
Input bias current, VSENSE
VSENSE = Vref
60
Output voltage slew rate (symmetric), COMP
1
dB
MHz
VBIAS
V
250
nA
1.4
V/μs
PWM COMPARATOR
PWM comparator propagation delay
time,PWM comparator input to PH pin
(excluding deadtime)
10-mV overdrive (1)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA (1)
Internal slow-start time
0.03
V
2.5
μs
2.6
3.35
4.1
ms
Charge current, SS/ENA
SS/ENA = 0 V
3
5
8
μA
Discharge current, SS/ENA
SS/ENA = 1.2 V, VI = 2.7 V
2
2.3
4
mA
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
VSENSE falling
(1)
Power good falling edge deglitch (1)
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI= 5.5 V
0.18
μs
0.3
V
1
μA
CURRENT LIMIT
Current limit trip point
VI = 3 V Output shorted (1)
7.2
10
VI= 6 V Output shorted (1)
10
12
A
Current limit leading edge blanking time (1)
100
ns
Current limit total response time (1)
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point (1)
135
Thermal shutdown hysteresis (1)
150
165
10
°C
°C
OUTPUT POWER MOSFETS
rDS(on)
(4)
6
Power MOSFET switches
VI = 6 V (4)
26
47
VI = 3 V (4)
36
65
mΩ
Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
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7.6 Dissipation Ratings (1) (2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28 Pin PWP with solder
18.2 °C/W
5.49 (3) W
3.02 W
2.20 W
28 Pin PWP without
solder
40.5 °C/W
2.48 W
1.36 W
0.99 W
(1)
(2)
(3)
Test board conditions:
(a) 3 inch × 3 inch, 4 layers, thickness: 0.062 in
(b) 1.5 oz. copper traces located on the top of the PCB
(c) 1.5 oz. copper plane located on the bottom of the PCB
(d) 0.5 oz. copper planes on the 2 inner layers
(e) 12 thermal vias. See Figure 23
Thermal metrics shown in Thermal Information refer to JEDEC High K board. Metrics in this table refer to the test board conditions listed
below.
Maximum power dissipation may be limited by overcurrent protection
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7.7 Typical Characteristics
60
Drain Source On-State Reststance − m W
Drain Source On-State Reststance − m W
60
IO = 6 A
50
40
30
20
10
0
−40
0
25
85
TJ − Junction Temperature − °C
50
IO = 6 A
40
30
20
10
0
−40
125
VIN = 3.3 V
25
85
TJ − Junction Temperature − °C
125
VIN = 5 V
Figure 1. Drain-Source On-State Resistance vs
Junction Temperature
Figure 2. Drain-Source On-State Resistance vs
Junction Temperature
800
f − Externally Set Oscillator Frequency − kHz
750
f − Internally Set Oscillator Frequency − kHz
0
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
0
25
85
TJ − Junction Temperature − °C
125
700
RT = 68 k
600
500
RT = 100 k
400
300
RT = 180 k
200
−40
Figure 3. Internally Set Oscillator Frequency vs
Junction Temperature
0
25
85
TJ − Junction Temperature − °C
125
Figure 4. Externally Set Oscillator Frequency vs
Junction Temperature
0.895
5
4.5
4
Device Power Losses − W
V ref − Voltage Reference − V
0.893
0.891
0.889
0.887
3.5
3
VI = 3.3 V
2.5
2
1.5
VI = 5 V
1
0.5
0.885
−40
0
0
25
85
TJ − Junction Temperature − °C
125
0
1
2
TJ = 125°C
Figure 5. Voltage Reference vs Junction Temperature
8
3
4
5
6
7
8
IL − Load Current − A
fs = 700 kHz
Figure 6. Device Power Losses at TJ = 125°C vs
Load Current
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Typical Characteristics (continued)
140
0
120
−20
0.893
−40
−60
80
0.891
fs = 550 kHz
0.889
Phase
−80
−100
60
−120
40
Gain
Phase − Degrees
100
Gain − dB
VO − Output Voltage Regulation − V
0.895
−140
20
0.887
−160
0
0.885
−180
−20
3
3.5
4
4.5
5
5.5
6
1
10
100
VI − Input Voltage − V
TJ = 85°C
1k
10 k
100 k
1M
−200
10 M
f − Frequency − Hz
IO = 3 A
RL= 10 kΩ
Figure 7. Output Voltage Regulation vs Input Voltage
CL = 160 pF
TA = 25°C
Figure 8. Error Amplifier Open Loop Response
3.80
Internal Slow-Start Time − ms
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
TJ − Junction Temperature − °C
125
Figure 9. Internal Slow-Start Time vs Junction Temperature
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8 Detailed Description
8.1 Overview
The TPS54610 low-input voltage high-output current synchronous buck PWM converter integrates all required
active components. Included on the substrate with the listed features are a true, high performance, voltage error
amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally or externally set
slow-start circuit to limit inrush currents; and a power good output useful for processor/logic reset, fault signaling,
and supply sequencing.
8.2 Functional Block Diagram
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
3−6V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
30 mW
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
−
R Q
S
Error
Amplifier
Reference
VREF = 0.891 V
PWM
Comparator
LOUT
VO
CO
Adaptive Dead-Time
and
Control Logic
VIN
30 mW
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54610
Hysteresis: 0.03 Vref
VSENSE
10
COMP
RT
SHUTDOWN
35 µs
SYNC
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8.3 Feature Description
8.3.1 Undervoltage Lockout (UVLO)
The TPS54610 incorporates an UVLO to keep the device disabled when the input voltage (VIN) is insufficient.
During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95
V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below
the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-μs rising and falling
edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN.
8.3.2 Slow Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-μs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a lowvalue capacitor connected between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:
1.2 V
t d = C(SS) ´
5 mA
(1)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t(SS) = C(SS) ´
5 mA
(2)
The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the
internal rate.
8.3.3 VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
8.3.4 Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54610, since it cancels offset errors in the scale and error amplifier circuits.
8.3.5 Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 to 700 kHz by connecting a resistor between the RT pin and AGND and floating
the SYNC pin. The switching frequency is approximated by the following equation, where R is the resistance
from RT to AGND:
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Feature Description (continued)
Switching Frequency =
100 kW
´ 500 [kHz]
R
(3)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to 80% of the synchronization signal. Table 1 summarizes
the frequency selection configurations:
Table 1. Switching Frequency/Synchronization Configuration
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 180 kΩ to 68 kΩ
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external
synchronization frequency
8.3.6 Error Amplifier
The high performance, wide bandwidth, voltage error amplifier sets the TPS54610 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the
particular application needs. Type 2 or type 3 compensation can be employed using external compensation
components.
8.3.7 PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is reset, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54610 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
8.3.8 Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver
does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.
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The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and
reduces external component count.
8.3.9 Overcurrent Protection
The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter.
Load protection during current sink operation is provided by thermal shutdown.
8.3.10 Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up
due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
8.3.11 Power-Good (PWRGD)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low, or a thermal shutdown occurs. When VIN ≥ UVLO threshold,
SS/ENA ≥ enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-μs falling edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
8.4 Device Functional Modes
8.4.1 Continuous Conduction Mode
The TPS54610 devices operate in continuous conduction mode, that is, the low-side MOSFET runs fully
complimentary to the high-side MOSFET regardless of output current.
8.4.2 Switching Frequency Selection/Synchronization
Depending on the configuration of the RT and SYNC pins, the TPS54610 can be configured to switch at 350
kHz, or 550 kHz without external components, or any frequency between 280 kHz and 700 kHz as configured by
a resistor from the RT pin to ground. The TPS54610 can also be synchronized to an external clock using the
SYNC pin. See Table 1 for more information.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS54610 is a 3 V to 6 V input, 6 A output synchronous buck PWM switcher. Ideal applications are:
broadband, networking and optical communications infrastructure, and portable computing/notebook PCs.
9.2 Typical Applications
9.2.1 High Frequency Switching Regulator Using Ceramic Output Capacitors
Figure 10 shows the schematic diagram for a typical TPS54610 application. The TPS54610 (U1) can provide
greater than 6 A of output current at a nominal output voltage of 3.3 V.
VI
+
C2
220 µF
10 V
U1
TPS54610PWP
28
R2
10 kW
VIN
VIN
27
26
25
C1
0.047 µF
RT
VIN
SYNC
VIN
VIN
SS/ENA
PH
PH
VBIAS
PH
PWRGD
4
C4
0.1 µF
3
PH
PWRGD
PH
PH
COMP
PH
PH
2
PH
VSENSE
BOOT
PGND
PGND
1
C3
120 pF
C5
5600 pF
PGND
AGND
PGND
PGND
POWERPAD
C8
10 µF
24
23
22
21
L1
4.7 µH
20
14
13
+
12
11
C9
+
470 µF
4V
C10
470 mF
4V
C11
100 pF
VO
10
9
8
7
6
C7
5
19
0.047 µF
18
17
16
15
R1
9.09 kW
C6
R3
3.74 kW
R5
8200 pF
1.74 kW
R4
10 kW
Figure 10. Application Circuit
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Typical Applications (continued)
9.2.1.1 Design Requirements
This guide illustrates the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These requirements are typically determined at
the system level. For this example, start with the following known parameters:
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Output Voltage
3.3 V
Maximum Output Current
6A
Input Voltage
6V
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Component Selection
The values for the components used in this design example were selected using the SWIFT designer software
tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the
TPS54610.
9.2.1.2.2 Input Filter
The input to the circuit is a nominal 5 VDC. The input filter C2 is a 220-μF POSCAP capacitor, with a maximum
allowable ripple current of 3 A. C8 provides high frequency decoupling of the TPS54610 from the input supply
and must be located as close as possible to the device. Ripple current is carried in both C2 and C8, and the
return path to PGND must avoid the current circulating in the output capacitors C9 and C10.
9.2.1.2.3 Feedback Circuit
The resistor divider network of R3 and R4 sets the output voltage for the circuit at 3.3 V. R4, along with R1, R5,
C3, C5, and C6 form the loop compensation network for the circuit. For this design, a Type 3 topology is used.
9.2.1.2.4 Operating Frequency
In the application circuit, the 350 kHz operation is selected by leaving RT and SYNC open. Connecting a 180 kΩ
to 68 kΩ resistor between RT (pin 28) and analog ground can be used to set the switching frequency to 280 kHz
to 700 kHz. To calculate the RT resistor, use the equation below:
500 kHz
R=
´ 100[kW]
Switching Frequency
(4)
9.2.1.2.5 Output Filter
The output filter is composed of a 4.7-μH inductor and two 470-μF capacitors. The inductor is a low dc resistance
(12 mΩ) type, Coiltronics UP3B-4R7. The capacitors used are 4-V POSCAP types with a maximum ESR of
0.040 Ω. The feedback loop is compensated so that the unity gain frequency is approximately 25 kHz.
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9.2.1.3 Application Curves
100
100
95
95
90
90
85
VO = 2.5 V
80
Efficiency − %
Efficiency − %
85
VO = 1.8 V
75
70
VO = 1.2 V
VO = 3.3 V
80
VO = 1.8 V
75
70
VO = 1.2 V
65
65
60
60
55
55
50
50
0
1
2
3
4
5
6
7
0
1
2
3
IO − Output Current − A
VI = 3.3 V
TA = 25°C
4
5
6
7
IO − Output Current − A
f = 550 kHz
L = 4.7 µH
VI = 5 V
TA = 25°C
Figure 11. Efficiency vs Output Current
f = 550 kHz
L = 4.7 µH
Figure 12. Efficiency vs Output Current
1.004
1.002
1.003
1.0015
1.002
1.001
Load Regulation
Load Regulation
IO = 6 A
1.001
1
0.999
1.0005
IO = 3 A
1
0.9995
No Load
0.998
0.999
0.997
0.9985
0.996
0.998
0
1
2
3
4
5
6
4
4.5
IO − Output Current − A
VI = 5 V
TA = 25°C
f = 550 kHz
VO = 3.3 V
VI = 5 V
TA = 25°C
Figure 13. Load Regulation vs Output Current
60
5
5.5
6
VI − Input Voltage − V
f = 550 kHz
VO = 3.3 V
Figure 14. Line Regulation vs Input Voltage
125
180
115
Gain − dB
20
90
Phase
Phase −Degrees
135
40
Gain
45
0
Ambient Temperature − °C
105
95
VI = 5 V
Safe Operating
Area
85
75
VI = 3.3 V
65
55
45
35
−20
100
1k
10 k
100 k
0
1M
25
0
1
2
VI = 5 V
TA = 25°C
f = 550 kHz
IO = 6A
Figure 15. Loop Response
16
3
84
5
6
7
IO − Output Current − A
f − Frequency − Hz
VO = 3.3 V
TJ = 125°C
fs = 700 kHz
Figure 16. Ambient Temperature vs Load Current
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Output Current - 2 A/div
Output Ripple Voltage - 10 mV/div
Output Voltage - 50 mV/div
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t - Time = 100 ms/div
t - Time = 1 ms/div
VI = 5 V
VO = 3.3 V
VI = 5 V
6 A, 350 kHz
1 A to 5 A
Figure 18. Load Transient Response
Output Voltage - 2 V/div
Input Voltage - 2 V/div
Figure 17. Output Ripple Voltage
t - Time = 2 ms/div
VI = 5 V
No Slow-Start Cap
Figure 19. Slow-Start Timing
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9.2.2 High Frequency Application
Figure 20 shows the schematic diagram for a reduced size, high frequency application using the TPS54610. The
TPS54610 (U1) can provide up to 6 A of output current at a nominal outputvoltage of 1.8 V. A small size 0.56 uH
inductor is used and the switching frequency is set to 680 kHz by R1. The compensation network is optimized for
fast transient response as shown in Figure 20.
VI
C1
10 µF
U1
TPS54610PWP
C2
10 µF
R1
28
RT
VIN
71.5 kW
VIN
27
C3
0.047 µF
26
C4
1 µF
25
SYNC
VIN
VIN
SS/ENA
VIN
PH
VBIAS
PH
PH
4
PWRGD
C5
R2
3
10 kW
C6
PH
PH
COMP
PH
PH
470 pF
PH
470 pF
2
PH
VSENSE
BOOT
PGND
R5
1.47 kW
PGND
R3
39 W
R6
1.5 kW
1
PGND
AGND
PGND
PGND
POWERPAD
24
23
22
21
20
14
13
12
11
10
9
8
L1
0.56 µH
7
6
5
19
VO
C7
+
0.047 µF
C8
+
150 µF
C9
150 µF
C10
1 pF
18
17
16
R4
2.4 W
15
C11
3300 pF
C12
0.012 µF
Figure 20. Small Size, High Frequency Design
9.2.2.1 Design Requirements
Refer to Design Requirements for the High Frequency Application Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure for the High Frequency Application Detailed Design Procedure.
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2 A/div
50 mV/div
9.2.2.3 Application Curve
10 µs/div
Figure 21. Transient Response, 1.5-A to 4.5-A Step
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 3 V and 6 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS54610 converter
additional bulk capacitance may be required.
11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
•
•
•
For proper thermal performance, the exposed thermal PowerPAD underneath the integrated circuit package
must be soldered to the printed-circuit board.
For good thermal performance, the PowerPAD underneath the integrated circuit TPS54610 needs to be
soldered well to the printed-circuit board.
The VIN pins are connected together on the printed-circuit board (PCB) and bypassed with a low-ESR
ceramic-bypass capacitor.
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins,
and the TPS54610 ground pins.
The minimum recommended bypass capacitance is 10-mF ceramic capacitor with a X5R or X7R dielectric
and the optimum placement is closest to the VIN pins and the PGND pins.
The TPS54610 has two internal grounds (analog and power). Inside the TPS54610, the analog ground ties to
all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected
between the two grounds can degrade the performance of the TPS54610, particularly at higher output
currents.
However, ground noise on an analog ground plane can also cause problems with some of the control and
bias signals. Therefore, separate analog and power ground traces are recommended.
There is an area of ground on the top layer directly under the IC, with an exposed area for connection to the
PowerPAD. Use vias to connect this ground area to any internal ground planes.
Additional vias are also used at the ground side of the input and output filter capacitors. The AGND and
PGND pins are tied to the PCB ground by connecting them to the ground area under the device as shown.
The only components that tie directly to the power ground plane are the input capacitors, the output
capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54610.
Use a separate wide trace for the analog ground signal path. The analog ground is used for the voltage set
point divider, timing resistor RT, slow-start capacitor and bias capacitor grounds. Connect this trace directly to
AGND (Pin 1).
Since the PH connection is the switching node, the inductor is located close to the PH pins. The area of
theThe PH pins are tied together and routed to the output inductor. PCB conductor is minimized to prevent
excessive capacitive coupling.
Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor
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Layout Guidelines (continued)
•
•
•
•
close to the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep
the loop formed by the PH pins, LOUT, COUT and PGND as small as practical.
Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to the size of the IC package and the device pin-out, they
must be routed close, but maintain as much separation as possible while still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace.
If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating
frequency, connect them to this trace.
11.2 Layout Example
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
SYNC
VSENSE
COMPENSATION
NETWORK
COMP
SLOW START
CAPACITOR
SS/ENA
BIAS CAPACITOR
PWRGD
BOOT
CAPACITOR
BOOT
PH
VOUT
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
VBIAS
VIN
EXPOSED
POWERPAD
AREA
VIN
PH
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
PH
PGND
PH
PGND
VIN
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 22. Recommended Land Pattern for 28-Pin PWP PowerPAD
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11.3 Thermal Considerations
For operation at full rated load current, the analog ground plane must provide an adequate heat dissipating area.
A 3-inch by 3-inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD™ must be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available must be used when 6 A or greater operation is desired. Connection
from the exposed area of the PowerPAD™ to the analog ground plane layer must be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Eight vias must be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance
thermal performance must be included in areas not under the device package.
8 PL q 0.0130
4 PL
q 0.0180
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
Larger Area
0.0630
0.0400
Figure 23. Recommended Land Pattern for 28-Pin PWP PowerPAD
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Related DC/DC Products
• TPS40000—dc/dc controller
• TPS759xx—7.5 A low dropout regulator
• PT6440 series—6 A plugin modules
Application information is available in Designing for Small-Size, High-Frequency Applications With Swift™Family
of Synchronous Buck Regulators.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54610PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54610
TPS54610PWPG4
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54610
TPS54610PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54610
TPS54610PWPRG4
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54610
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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