TPS54680-EP
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SGLS212A – OCTOBER 2003 – REVISED OCTOBER 2012
3-V TO 6-V INPUT, 6-A OUTPUT TRACKING SYNCHRONOUS BUCK
PWM SWITCHER WITH INTEGRATED FETs (SWIFT™) FOR SEQUENCING
Check for Samples: TPS54680-EP
FEATURES
1
•
•
2
•
•
•
•
Power Up/Down Tracking For Sequencing
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source or
Sink Current
Wide PWM Frequency: Fixed 350 kHz or
Adjustable 280 kHz to 700 kHz
Power Good and Enable
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
•
•
•
Low-Voltage, High-Density Distributed Power
Systems
Point of Load Regulation for High Performance
DSPs, FPGAs, ASICs and Microprocessors
Requiring Sequencing
Broadband, Networking and Optical
Communications Infrastructure
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Rated From –55°C to 125°C
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DESCRIPTION
As a member of the SWIFT™ family of dc/dc regulators, the TPS54680 low-input voltage high-output current
synchronous buck PWM converter integrates all required active components. Using the TRACKIN pin with other
regulators, simultaneous power up and down are easily implemented. Included on the substrate with the listed
features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in
choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input
voltage reaches 3 V; an internally or externally set slow-start circuit to limit inrush currents; and a power good
output useful for processor/logic reset.
The TPS54680 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT™ designer software tool to aid in
quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.
ORDERING INFORMATION (1)
TJ
(1)
(2)
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
VID NUMBER
–40°C to 125°C
0.9 V to 3.3 V
Plastic HTSSOP
(PWP) (2)
TPS54680QPWPREP
V62/04641-01XE
–55°C to 125C
0.9 V to 3.3 V
TPS54680MPWPREP
V62/04641-02XE
TPS54680MPWPEP
V62/04641-02XE-T
Plastic HTSSOP
(PWP) (2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
See the application section of the data sheet for PowerPAD drawing and layout information.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2012, Texas Instruments Incorporated
TPS54680-EP
SGLS212A – OCTOBER 2003 – REVISED OCTOBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED SCHEMATIC
Core Supply
VIN H
P
TPS54680
BOOT
TRACKIN PGND
VBIAS VSENSE
AGND COMP
I/O
VI = 5 V
fs = 700 kHz
CORE
PWRGD(I/O)
PWRGD(CORE)
power Good – 5 V/div
Input
STARTUP TIMING
VO – Output Voltage –1 V/div
I/O Supply
t – Time – 500 μs/div
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
TPS54680-EP
Input voltage range, VI
Output voltage range, VO
Source curren, IO
Sink current, IS
Voltage differential
VIN, ENA
–0.3 V to 7 V
RT
–0.3 V to 6 V
VSENSE, TRACKIN
–0.3 V to 4V
BOOT
–0.3 V to 17 V
VBIAS, COMP, PWRGD
–0.3 V to 7 V
PH
–0.6 V to 10 V
PH
UNIT
V
V
Internally Limited
COMP, VBIAS
6
mA
PH
12
A
COMP
6
ENA, PWRGD
10
AGND to PGND
mA
±0.3
V
Operating virtual junction temperature range, TJ
–55 to 150
°C
Storage temperature, Tstg (2)
–65 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage, VI
2
3
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NOM
MAX
6
UNIT
V
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THERMAL INFORMATION
TPS54680
THERMAL METRIC (1)
PWP
UNITS
28 PINS
Junction-to-ambient thermal resistance (2)
θJA
36.1
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
13.1
ψJT
Junction-to-top characterization parameter (5)
0.4
ψJB
Junction-to-board characterization parameter (6)
12.9
θJCbot
Junction-to-case (bottom) thermal resistance (7)
1.3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
15.5
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS54680Q
MIN
TYP
TPS54680M
MAX
MIN
6.0
3.0
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
Quiescent current
3.0
6.0
fs = 350 kHz, RT open,
PH pin open
11
15.8
11
15.8
fs = 500 kHz, RT = 100 kΩ,
PH pin open
16
23.5
16
23.5
1
1.4
1
1.4
2.95
3.0
2.95
3.0
Shutdown, ENA = 0 V
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
2.70
2.80
V
Hysteresis voltage, UVLO
0.14
0.16
0.093
0.16
V
2.5
µs
Rising and falling edge deglitch,
UVLO (1)
2.5
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS) = 0
2.70
2.80
(2)
2.90
2.70
2.80
100
2.90
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
0.900
0.879
0.891
REGULATION
Line regulation (1) (3)
Load regulation (1) (3)
(1)
(2)
(3)
IL = 3 A, fs = 350 kHz, TJ = 85°C
0.04
0.04
IL = 3 A, fs = 550 kHz, TJ = 85°C
0.04
0.04
IL = 0 A to 6 A, fs = 350 kHz,
TJ = 85°C
0.03
0.03
IL = 0 A to 6 A, fs = 550 kHz,
TJ = 85°C
0.03
0.03
%/V
%/A
Specified by design from -40°C to 85°C.
Static resistive loads only
Specified by the circuit used in Figure 10
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TPS54680Q
TPS54680M
MIN
TYP
MAX
MIN
TYP
MAX
RT open
280
350
450
244
350
450
RT = 180 kΩ (1% resistor to
AGND)
252
280
308
252
280
320
RT = 100 kΩ (1% resistor to
AGND)
460
500
540
432
500
540
RT = 68 kΩ (1% resistor to AGND)
663
700
762
656
700
762
UNIT
SUPPLY VOLTAGE, VIN
OSCILLATOR
Internally set – free running
frequency
Externally set – free running
frequency range
Ramp valley (4)
Ramp amplitude (peak-topeak) (4)
kHz
0.75
0.75
V
1
1
V
Minimum controllable on time (4)
200
Maximum duty cycle
kHz
90
230
90
ns
%
ERROR AMPLIFIER
Error amplifier open loop
voltage gain
1 kΩ COMP to AGND (4)
Error amplifier unity gain
bandwidth
90
110
90
110
Parallel 10 kΩ, 160 pF COMP to
AGND (4)
3
5
3
5
Error amplifier common mode
input voltage range
Powered by internal LDO (4)
0
Input bias current, VSENSE
VSENSE = Vref
VBIAS
60
Output voltage slew rate
(symmetric), COMP
1
0
250
60
1.4
dB
MHz
VBIAS
V
300
nA
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation
delay time, PWM comparator
input to PH pin (excluding
deadtime)
10-mV overdrive (4)
70
85
1.20
1.40
70
85
ns
1.20
1.40
V
ENABLE
Enable threshold voltage, ENA
0.82
Enable hysteresis voltage, ENA
Falling edge deglitch, ENA (4)
Leakage current, ENA
0.82
0.03
0.03
V
2.5
2.5
µs
VI = 5.5 V
1
1.6
µA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis
voltage (4)
Power good falling edge
deglitch (4)
Output saturation voltage,
PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
90
90
%Vref
3
3
%Vref
35
35
µs
0.18
0.3
0.18
1
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V Output shorted (4)
7.2
10
6.5
10
VI = 6 V Output shorted (4)
10
12
6.6
12
A
Current limit leading edge
blanking time
100
100
ns
Current limit total response time
200
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point (4)
Thermal shutdown hysteresis (4)
(4)
4
135
150
10
165
135
150
10
165
°C
°C
Specified by design from -40°C to 85°C.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TPS54680Q
TEST CONDITIONS
MIN
TPS54680M
TYP
MAX
VI = 6 V (5)
26
VI = 3 V (5)
36
MIN
TYP
MAX
47
26
47
65
36
65
UNIT
SUPPLY VOLTAGE, VIN
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
mΩ
TRACKIN
(5)
(6)
Input offset, TRACKIN
VSENSE = TRACKIN = 0.75 V
Input voltage range, TRACKIN
See
(6)
–2.5
2.5
–2.5
2.5
mV
0
Vref
0
Vref
V
Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
Specified by design from -40°C to 85°C.
Estimated Life (Hours)
1000000
100000
10000
1000
125
130
135
140
145
150
TJ (°C)
A.
See datasheet for absolute maximum and minimum recommended operating conditions.
B.
Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. TPS54680-EP Wirebond Life Derating Chart
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PWP PACKAGE
(TOP VIEW)
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
ENA
TRACKIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor,
RT resistor. Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-μF to 0.1-μF low-ESR capacitor connected from BOOT to PH generates
floating drive for the high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA
27
Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low
disables operation and places device in low quiescent current state.
PGND
15–19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with
large copper areas to the input and output supply returns, and negative terminals of the input and
output capacitors. A single point connection to AGND is recommended.
PH
6–14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
TRACKIN
26
External reference input. High impedance input to internal reference/multiplexer and error amplifier
circuits.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to
AGND pin with a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
20–24
VSENSE
6
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND
pins close to device package with a high quality, low-ESR 10-µF ceramic capacitor.
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
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INTERNAL BLOCK DIAGRAM
VBIAS
AGND
Enable
Comparator
Falling
Edge
Deglitch
ENA
1.2 V
Hysteresis: 0.03 V
2.5 μs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
I/O
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
sense Fet
30 mΩ
2.5 μs
SS_DIS
SHUTDOWN
PH
TRACKIN
Multiplexer
+
ï
R Q
Error
Amplifier
Reference
S
PWM
Comparator
Core
CO
Adaptive Dead-Time
and
Control Logic
25 ns Adaptive
Dead Time
LOUT
VIN
30 mΩ
PGND
OSC
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54680
Hysteresis: 0.03 Vref
VSENSE
COMP
SHUTDOWN
35 μs
RT
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TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
750
60
50
IO = 6 A
40
30
20
10
0
−55
−10
35
80
Junction Temperature (°C)
VIN = 5 V
Internally Set Oscillator Frequency (kHz)
VIN = 3.3 V
Drain Source On−State Resistance (mΩ)
50
IO = 6 A
40
30
20
10
0
−55
125
−10
35
80
Junction Temperature (°C)
350
−10
35
80
Junction Temperature (°C)
125
G002
G003
Figure 3.
Figure 4.
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
AT TJ = 125°C
vs
LOAD CURRENT
0.895
5
TJ = 125°C
fs = 700 kHz
4.5
700
RT = 68 k
600
500
RT = 100 k
400
Device Power Losses – W
0.893
Voltage Reference (V)
Internally Set Oscillator Frequency (kHz)
450
Figure 2.
800
0.891
0.889
0.887
300
−10
35
80
Junction Temperature (°C)
0.885
−55
125
VI = 3.3 V
3
2.5
2
1.5
VI = 5 V
1
0
−10
35
80
Junction Temperature (°C)
125
0
1
2
3
4
5
6
7
8
IL – Load Current – A
G004
G005
Figure 5.
Figure 6.
Figure 7.
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
0.895
ERROR AMPLIFIER
vs
OPEN LOOP RESPONSE
0
140
TA = 85°C,
IO = 3 A
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
–20
–40
100
–60
0.891
Gain – dB
VO – Output Voltage Regulation – V
4
3.5
0.5
RT = 180 k
200
−55
fs = 550 kHz
0.889
80
Phase
–80
–100
60
–120
40
Gain
20
–140
–160
0.887
0
0.885
–180
–20
3
3.5
4
4.5
5
VI – Input Voltage – V
5.5
6
1
10
100
1k
10 k 100 k 1 M
–200
10 M
f – Frequency – Hz
Figure 8.
8
550
250
−55
125
G001
650
Phase – Degrees
Drain Source On−State Resistance (mΩ)
60
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
Figure 9.
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APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54680 application. The TPS54680 (U1) can provide
greater than 6 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the
exposed thermal PowerPAD underneath the integrated circuit package must be soldered to the printed-circuit
board. To provide power up tracking, the enable of the I/O supply should be used. If the I/O enable is not used to
power up, then devices with similar undervoltage lockout thresholds need to be implemented to ensure power up
tracking. To ensure power down tracking, the enable pin should be used.
TPS54610
I/O Power Supply
R2
R4
10 kΩ
71.5 kΩ
C2
1 μF
R6
9.76 kΩ
VIN
C6
10 μF
C7
10 μF
VOUT_I/O
R1
10 kΩ
U1
28
27
RT
AGND
ENA
VSENSE
TRACKIN COMP
VBIAS PWRGD
BOOT
VIN
VIN
PH
26
25
24
23
22
VIN
21
VIN
20 VIN
19
PGND
18
PGND
17 PGND
16 PGND
15 PGND
PwrPad
1
2
3
4
5
6
7
PH
8
PH
9
PH
10
PH
11
PH
12
PH
13
PH
14
PH
R3
R5
C1
470 pF
C4
C5
10 kΩ
C3
301 Ω 470 pF
R8
12 pF
0.047 μF
10 kΩ
R7
9.76 kΩ
L1
R9
0.65 μH
2.2 Ω
VOUT_CORE
C8
22 μF
C9
22 μF
C10
22 μF
C11
3300 pF
Analog and Power Grounds are Tied at
the Power Pad Under the Package of IC
Figure 10. Application Circuit
COMPONENT SELECTION
The values for the components used in this design example were selected for low output ripple voltage and small
PCB area. Additional design information is available at www.ti.com.
INPUT FILTER
The input voltage is a nominal 5 Vdc. The input filter C6 is a 10-µF ceramic capacitor (Taiyo Yuden). C7 also a
10-µF ceramic capacitor (Taiyo Yuden) provides high frequency decoupling of the TPS54680 from the input
supply and must be located as close as possible to the device. Ripple current is carried in both C6 and C7, and
the return path to PGND must avoid the current circulating in the output capacitors C8, C9, and C10.
FEEDBACK CIRCUIT
The values for these components have been selected to provide low output ripple voltage. The resistor divider
network of R3 and R8 sets the output voltage for the circuit at 1.8 V. R3, along with R7, R5, C1, C3, and C4 form
the loop compensation network for the circuit. For this design, a Type 3 topology is used.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is selected by leaving RT open. Connecting a 180 kΩ to 68 kΩ
resistor between RT (pin 28) and analog ground can be used to set the switching frequency to 280 kHz to 700
kHz. To calculate the RT resistor, use the equation below:
500 kHz
R=
´ 100 [kΩ ]
Switching Frequency
(1)
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OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and 3 x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0227. The capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the unity gain frequency is approximately 75 kHz.
GROUNDING AND POWERPAD LAYOUT
The TPS54680 has two internal grounds (analog and power). Inside the TPS54680, the analog ground ties to all
of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be
tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54680,
particularly at higher output currents. However, ground noise on an analog ground plane can also cause
problems with some of the control and bias signals. Therefore, separate analog and power ground planes are
recommended. These two planes must tie together directly at the IC to reduce noise between the two grounds.
The only components that must tie directly to the power ground plane are the input capacitor, the output
capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54680. The layout of the
TPS54680 evaluation module is representative of a recommended layout for a 4-layer board. Documentation for
the TPS54680 evaluation module can be found on the Texas Instruments web site under the TPS54680 product
folder. See the TPS54680 EVM user’s guide.
LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE
For operation at full rated load current, the analog ground plane must provide an adequate heat dissipating area.
A 3-inch by 3-inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available must be used when 6 A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the analog ground plane layer must be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Eight vias must be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance
thermal performance must be included in areas not under the device package.
8 PL Ø 0. 0 1 3 0
4 PL
Ø 0.0180
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Exposed
Copper Area for Powerpad. 5mil
Stencils May Require 10 Percent
Larger Area
0.0630
0.0400
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
10
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(1)
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
VO = 1.2 V
VO = 0.9 V
70
VI = 3.3 V,
FS = 700 kHz,
VO = 0.9 V, 1.8 V and 2.5 V
VO = 1.8 V
0.05
0
–0.05
TA = 25°C,
VI = 3.3 V,
FS = 700 kHz,
VO = 0.9 V, 1.2 V and 1.8 V
–0.10
–0.15
–0.20
60
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
IO – Output Current – A
115
120
60
30
Gain
0
–30
–20
–60
VI = 5 V,
IO = 0 A,
fS = 700 kHz
1k
10 k
100 k
f – Frequency – Hz
–90
–120
105
65
45
–150
35
–180
1M
25
0
1
2
3
4
5
6
7
8
IO – Output Current – A
Figure 17.
VO – Output Voltage –1 V/div
STARTUP TIMING
Load Current 2A/div
6
t – Time – 1 μs/div
Figure 16.
VI = 5 V,
VO = 1.8 V
5.5
VI = 3.3 V
55
LOAD TRANSIENT RESPONSE
VO – Output Voltage –100 mV/div
Safe Operating Area (1)
75
Figure 15.
(1)
VI = 5 V
95
POWER DOWN TIMING
I/O
VI = 5 V
fs = 700 kHz
CORE
PWRGD(I/O)
PWRGD(CORE)
t – Time –20 μs/div
t – Time – 500 μs/div
Figure 18.
Figure 19.
– Output Voltage –1 V/div
10
5
OUTPUT AND INPUT RIPPLE
TJ = 125°C
fs = 700 kHz
85
4.5
Figure 14.
I/O
CORE
PWRGD(I/O)
VO
Gain – dB
20
–60
100
90
Phase – Degrees
Phase
4
VI – Input Voltage – V
Output Ripple – 20 mV/div
150
40
–50
3.5
Input Ripple – 100 mV/div
50
–40
3
Phase Pin – 2 V/div
125
Ambient Temperature – ° C
180
–30
IO = 0 A
ï 0.10
AMBIENT TEMPERATURE
vs
LOAD CURRENT
LOOP RESPONSE
0
–10
0
ï 0.05
Figure 13.
60
30
IO = 6 A
0.05
ï 0.20
0 .05 1 1.5 2 2 .5 3 3.5 4 4.5 5 5.5 6
IO – Output Current – A
Figure 12.
0.10
ï 0.15
Power Good – 5 V/div
65
VO = 1.2 V
0.10
TA = 25°C,
FS = 700 kHz,
VO = 1.8 V
0.15
Line Regulation – %
Load Regulation – %
85
75
VO = 0.9 V
0.15
VO = 1.8 V
90
Efficiency – %
0.20
0.20
95
80
LINE REGULATION
vs
INPUT VOLTAGE
PWRGD(CORE)
Power Good – 5 V/div
PERFORMANCE GRAPHS
t – Time –20 μs/div
Figure 20.
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
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Figure 21 shows the schematic diagram for a power supply tracking design using a TPS2034 high side power
switch and a TPS54680 device. The TPS2034 power switch ensures the I/O voltage is not applied to the load
before U1 has enough bias voltage to operate and generate the core voltage.
TPS2034
Distribution Switch
R2
R4
10 kΩ
71.5 kΩ
R6
9.76 kΩ
C2
1 μF
VIN
C6
10 μF
C7
10 μF
VOUT_I/O
R1
10 kΩ
U1
28
27
RT
AGND
ENA
VSENSE
TRACKIN COMP
VBIAS PWRGD
BOOT
VIN
VIN
PH
26
25
24
23
22
VIN
21
VIN
20 VIN
19
PGND
18
PGND
17 PGND
16 PGND
15 PGND
PwrPad
1
2
3
4
5
6
7
PH
8
PH
9
PH
10
PH
11
PH
12
PH
13
PH
14
PH
R3
R5
C1
470 pF
C4
C5
10 kΩ
C3
301 Ω 470 pF
R8
12 pF
0.047 μF
10 kΩ
R7
9.76 kΩ
L1
R9
0.65 μH
2.2 Ω
VOUT_CORE
C8
22 μF
C9
22 μF
C10
22 μF
C11
3300 pF
Analog and Power Grounds are Tied at
the Power Pad Under the Package of IC
Figure 21. 3.3-V Small Size, High Frequency Design
12
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VO – Output Voltage –100 mV/div
LOAD TRANSIENT RESPONSE
I O – Output Current – 2 A/div
VI = 3.3 V,
VO = 1.8 V
t – Time – 20 μs/div
Figure 22.
EFFICIENCY
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
VI = 5 V,
VO = 1.8 V,
TA = 25°C,
FS = 700 kHz
0.15
80
VO = 0.9 V
VO = 1.2 V
70
65
VI = 5 V,
TA = 25°C,
FS = 700 kHz
60
55
0.05
0
–0.05
–0.15
1
50
150
115
40
120
60
Gain – dB
30
10
Gain
–60
100
0
–30
–20
–50
90
–60
VI = 3.3 V,
IO = 0 A,
fS = 700 kHz
1k
10 k
100 k
f – Frequency – Hz
Phase ï Degrees
Phase
–90
–120
Ambient Temperature – ° C
125
–40
3
4
5
6
IO – Output Current – A
7
4
8
Safe Operating Area (1)
75
VI = 3.3 V
55
45
–150
35
–180
1M
25
Figure 26.
VI = 5 V
65
5.5
0
1
6
OUTPUT AND INPUT RIPPLE
105
85
5
Figure 25.
TJ = 125°C
fs = 700 kHz
95
4.5
VI – Input Voltage – V
AMBIENT TEMPERATURE
vs
LOAD CURRENT
LOOP RESPONSE
0
–10
2
Figure 24.
180
IO = 0 A
–0.20
0
Figure 23.
20
0
–0.15
60
IO = 6 A
–0.05
–0.10
IO – Output Current – A
30
0.05
–0.10
–0.20
50
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8
0.10
Input Ripple – 100 mV/div
75
0.10
Output Ripple – 20 mV/div
85
VO = 1.8 V,
TA 25°C,
FS = 700 kHz
0.15
2
3
4
5
6
IO – Output Current – A
7
Figure 27.
8
Phase Pin – 2 V/div
90
Load Regulation – %
VO = 1.8 V
Line Regulation – %
95
Efficiency – %
0.20
0.20
100
–30
LINE REGULATION
vs
INPUT VOLTAGE
t – Time – 1 μs/div
Figure 28.
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14
SLOW-START TIMING
VI = 5 V,
0.04 μF
Slow-start Cap
Output Voltage – 2 V/div
Input Voltage – 2 V/div
Output Voltage – 2 V/div
Input Voltage – 2 V/div
SLOW-START TIMING
VI = 5 V,
0.04 μF
Slow-start Cap
4.0 ms/div
4.0 ms/div
Figure 29.
Figure 30.
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SGLS212A – OCTOBER 2003 – REVISED OCTOBER 2012
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54680 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-μs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN.
TRACKIN/INTERNAL SLOW-START
The internal slow-start circuit provides start-up slope control of the output voltage. The nominal internal slow-start
rate is 25 V/ms. When the voltage on TRACKIN rises faster than the internal slope or is present when device
operation is enabled, the output rises at the internal rate. If the reference voltage on TRACKIN rises more slowly,
then the output rises at about the same rate as TRACKIN.
Once the voltage on the TRACKIN pin is greater than the internal reference of 0.891 V, the multiplexer switches
the noninverting node to the high precision reference.
ENABLE (ENA)
The enable pin, ENA, provides a digital control enable or disable (shut down) for the TPS54680. An input voltage
of 1.4 V or greater ensures that the TPS54680 is enabled. An input of 0.82 V or less ensures that device
operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL
outputs.
When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output
starting from 0 V.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54680, since it cancels offset errors in the scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency is set internally to 350 kHz. If a different frequency of operation is required for the
application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor
between the RT pin and AGND. The switching frequency is approximated by the following equation, where R is
the resistance from RT to AGND:
100 kW
Switching Frequency =
´ 500[kHz]
R
(2)
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SWITCHING FREQUENCY
RT PIN
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 180 kΩ to 68 kΩ
ERROR AMPLIFIER
The high performance, wide bandwidth, voltage error amplifier sets the TPS54680 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the
particular application needs. Type 2 or type 3 compensation can be employed using external compensation
components.
PWM CONTROL
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch.
Once the PWM latch is reset, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54680 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the
output inductor and consequently the output current. This process is repeated each cycle in which the current
limit comparator is tripped.
DEAD-TIME CONTROL AND MOSFET DRIVERS
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver
does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.
The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and
reduces external component count.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents the current limit from false
tripping. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the
output filter. Load protection during current sink operation is provided by thermal shutdown.
16
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THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up
due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
POWER-GOOD (PWRDG)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or ENA is low, or a thermal shutdown occurs. When VIN ≥ UVLO threshold, ENA ≥
enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis
voltage equal to 3% of Vref and a 35 µs falling edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54680MPWPEP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
54680M
TPS54680MPWPREP
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
54680M
TPS54680QPWPREP
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54680EP
V62/04641-01XE
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
54680EP
V62/04641-02XE
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
54680M
V62/04641-02XE-T
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
54680M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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