TPS54719
SLVSB69C – JUNE 2012 – REVISED SEPTEMBER 2021
TPS54719 2.95-V To 6-V Input, 7-A Synchronous Step Down Converter
1 Features
•
•
•
•
•
•
•
•
•
Two 30-mΩ (typical) MOSFETs for high efficiency
at 7-A loads
200-kHz to 2-MHz switching frequency
0.6 V ± 1.5% voltage reference over temperature
Adjustable slow start/sequencing
UV and OV power-good output
Low operating and shutdown quiescent current
Safe start-up into pre-biased output
Cycle-by-cycle current limit, thermal and frequency
foldback protection
–40°C to 140°C operating junction temperature
range
Thermally enhanced 3-mm × 3-mm 16-pin QFN
2 Applications
•
•
•
Low-voltage, high-density power systems
Point-of-load regulation for high performance
DSPs, FPGAs, ASICs, and microprocessors
Broadband, networking, and optical
communications infrastructure
Efficiency is maximized through the integrated 30-mΩ
MOSFETs and 455-μA typical supply current. Using
the enable pin, shutdown supply current is reduced to
1 μA by entering a shutdown mode.
Undervoltage lockout is internally set at 2.4 V, but can
be increased by programming the threshold with a
resistor network on the enable pin. The output voltage
start-up ramp is controlled by the slow-start pin. An
open-drain power-good signal indicates the output is
within 93% to 108% of its nominal voltage.
Frequency foldback and thermal shutdown protects
the device during an overcurrent condition.
The TPS54719 is supported in the WEBENCH™
Software Tool at www.ti.com/webench.
3 Description
The TPS54719 device is a full featured 6-V, 7-A,
synchronous step down current mode converter with
two integrated MOSFETs.
The TPS54719 enables small designs by integrating
the MOSFETs, implementing current mode control to
VIN
The TPS54719 provides accurate regulation for a
variety of loads with an accurate ±1.5% Voltage
Reference (VREF) over temperature.
Device Information
TPS54719
(1)
QFN (16)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
100
CBOOT
VIN
PACKAGE(1)
PART NUMBER
3.3 VIN / 1.8 VOUT
90
BOOT
R4
CI
TPS54719
EN
LO
80
VOUT
PH
CO
R5
R1
PWRGD
VSENSE
C ss
RT
R3
C1
5 VIN / 1.8 VOUT
70
5 VIN / 3.3 VOUT
60
5 VIN / 1.2 VOUT
50
40
SS/TR
RT
COMP
GND
AGND
POWERPAD
Efficiency (%)
•
reduce external component count, reducing inductor
size by enabling up to 2-MHz switching frequency,
and minimizing the IC footprint with a small 3-mm ×
3-mm thermally enhanced QFN package.
3.3 VIN / 1.2 VOUT
30
R2
20
10
100
1k
Load Current (mA)
10k
G022
Efficiency Versus Output Current
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54719
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SLVSB69C – JUNE 2012 – REVISED SEPTEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Typical Characteristics................................................ 7
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................16
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................30
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................34
11.1 Receiving Notification of Documentation Updates.. 34
11.2 Support Resources................................................. 34
11.3 Trademarks............................................................. 34
11.4 Electrostatic Discharge Caution.............................. 34
11.5 Glossary.................................................................. 34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
Changes from Revision B (February 2016) to Revision C (September 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Added I/O column to Table 5-1 .......................................................................................................................... 3
Changes from Revision A (July 2014) to Revision B (February 2016)
Page
• Deleted SWIFT™ from the data sheet title......................................................................................................... 1
• Moved Storage temperature to the Section 6.1 ................................................................................................. 4
• Changed Handling Ratings to Section 6.2 .........................................................................................................4
2
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5 Pin Configuration and Functions
VIN
1
VIN
2
VIN
EN
PWRGD
BOOT
QFN16
RTE Package
(Top View)
16
15
14
13
12
PH
11
PH
PowerPAD
(17)
GND
4
9
SS/TR
5
6
7
8
RT
PH
COMP
10
VSENSE
3
AGND
GND
Figure 5-1. 16-Pin RTE QFN Package (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
AGND
5
BOOT
13
I
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
COMP
7
O
Error amplifier output and input to the output switch current comparator. Connect frequency
compensation components to this pin.
EN
15
I
Enable pin, internal pullup current source. Pull below 1.18 V to disable. Float to enable. Can be used to
set the on/off threshold (adjust UVLO) with two additional resistors.
GND
PH
Analog Ground should be electrically connected to GND close to the device.
3, 4
Power Ground. This pin should be electrically connected directly to the power pad under the IC.
10, 11,
12
O
The source of the internal high-side power MOSFET and drain of the internal low-side (synchronous)
rectifier MOSFET.
PWRGD
14
O
An open-drain output. Asserts low if output voltage is low due to thermal shutdown, overcurrent,
overvoltage/undervoltage, or EN shut down.
RT
8
I
Resistor timing
SS/TR
9
I/O
Thermal
Pad
17
VIN
VSENSE
Slow start. An external capacitor connected to this pin sets the output voltage rise time. This pin can also
be used for tracking.
GND pin should be connected to the exposed power pad for proper operation. This thermal pad should
be connected to any internal PCB ground plane using multiple vias for good thermal performance.
1, 2, 16
I
Input supply voltage: 2.95 V to 6 V
6
I
Inverting node of the transconductance (gm) error amplifier
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VIN
–0.3
7
EN
–0.3
BOOT
Input voltage
7
PH + 8
VSENSE
–0.3
3
COMP
–0.3
3
PWRGD
–0.3
7
SS/TR
–0.3
3
RT
–0.3
6
BOOT-PH
Output voltage
–0.6
PH 10 ns Transient
Sink current
V
8
PH
Source current
UNIT
7
–2
V
7
EN
100
RT
100
COMP
100
μA
PWRGD
10
mA
SS/TR
100
μA
μA
Operating Junction temperature, Tj
–40
140
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
Electrostatic discharge
pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
UNIT
±2000
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply voltage
Input voltage
TA
4
NOM
MAX
2.95
6
EN
0
6
PWRGD
0
6
SS/RT
0
2.7
RT
0
5.5
–40
85
Operating free-air temperature
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UNIT
V
V
°C
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6.4 Thermal Information
TPS54719
THERMAL METRIC (1)
RTE (16 PINS)
RθJA
Junction-to-ambient thermal resistance (standard board)
49.1
RθJA
Junction-to-ambient thermal resistance (custom
board)(2)
37.0
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
21.8
RθJC(top)
Junction-to-case(top) thermal resistance
50.7
RθJC(bot)
Junction-to-case(bottom) thermal resistance
7.5
RθJB
Junction-to-board thermal resistance
21.8
(1)
(2)
UNITS
°C/W
Power rating at a specific ambient temperature TA should be determined with a junction temperature of 140°C. This is the point
where distortion starts to substantially increase. See power dissipation estimate in the application section of this data sheet for more
information.
Test boards conditions:
a.
b.
c.
d.
2 inches x 2 inches, 4 layers, thickness: 0.062 inch
2 oz. copper traces located on the top of the PCB
2 oz. copper ground planes on the 2 internal layers and bottom layer
4 thermal vias (10mil) located under the device package
6.5 Electrical Characteristics
TJ = –40°C to 140°C, VIN = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
6
V
2.4
2.8
V
1
5
μA
455
550
μA
1.25
1.37
V
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage
Internal undervoltage lockout threshold
2.95
Rising VIN
Internal UVLO hysteresis
0.2
Shutdown supply current
EN = 0 V, 2.95 V ≤ VIN ≤ 6 V
Quiescent current – Iq
VSENSE = 620 mV, RT = 84 kΩ
V
ENABLE AND UVLO (EN PIN)
Enable threshold
Input current
Rising
1.16
Falling
1.18
Enable threshold + 50 mV
-3.6
Enable threshold – 50 mV
-0.7
μA
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference
2.95 V ≤ VIN ≤ 6 V, –40°C
FCO
Co >
DIOUT
´ DVOUT
1
´
8 ´ ¦ sw
(25)
1
Voripple
Iripple
(26)
where:
•
•
•
•
•
ΔIout is the change in output current
Fsw is the regulators switching frequency
ΔVout is the allowable change in the output voltage
Vripple is the maximum allowable output voltage ripple
Iripple is the inductor ripple current
Equation 27 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 27 indicates the ESR should be less than 28.6 mΩ. In this case, the ESR of the ceramic
capacitor is much less than 17.9 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
minimum value. For this example, two 22-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 28 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 28 yields
485 mA.
Resr <
Voripple
Iripple
Icorm s =
(27)
Vout ´ (Vinm ax - Vout)
12 ´ Vinm ax ´ L1 ´ ¦ sw
(28)
8.2.3.4 Input Capacitor
The TPS54719 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 10 μF
of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any
DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54719.
The input ripple current can be calculated using Equation 29.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to
the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material
that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator
capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The
output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, ceramic capacitors with at least a 10-V voltage rating are required to support the
maximum input voltage. For this example, two 10-μF and one 0.1-μF, 10-V capacitors in parallel have been
selected. The input capacitance value determines the input ripple voltage of the regulator. The input voltage
ripple can be calculated using Equation 30. Using the design example values, Ioutmax = 7 A, Cin = 20 μF, and
Fsw = 500 kHz, yields an input voltage ripple of 174 mV and a rms input ripple current of 3.43 A.
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Icirms = Iout ´
DVin =
Vout
´
Vinmin
(Vinmin
- Vout )
Vinmin
(29)
Ioutmax ´ 0.25
Cin ´ ¦ sw
(30)
8.2.3.5 Slow-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor can make the
TPS54719 reach the current limit or excessive current draw from the input power supply can cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start capacitor value can be calculated using Equation 4. For the example circuit, the slow-start time
is not too critical since the output capacitor value is 2 × 22 μF, which does not require much current to charge
to 1.8 V. The example circuit has the slow start time set to an arbitrary value of 2.5 ms, which requires a 10-nF
capacitor. In TPS54719, Iss is 2.4 μA and Vref is 0.6 V.
8.2.3.6 Bootstrap Capacitor Selection
A 0.1-μF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10-V or
higher voltage rating.
8.2.3.7 Undervoltage Lockout Set Point
The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54719. The UVLO has two thresholds: one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 2.794 V (VSTART). After the regulator starts switching, it should
continue to do so until the input voltage falls below 2.595 V (VSTOP).
The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN
pin. Equation 2 and Equation 3 can be used to calculate the resistance values necessary. From Equation 2 and
Equation 3, a 14.3 kΩ between VIN and EN and a 11.5 kΩ between EN and ground are required to produce the
2.794 and 2.595 volt start and stop voltages.
8.2.3.8 Output Voltage And Feedback Resistors Selection
For the example design, 20.0 kΩ was selected for R6. Using Equation 31, R7 is calculated as 10.0 kΩ.
R7 =
Vref
R6
Vo - Vref
(31)
Due to the internal design of the TPS54719, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by
Equation 32.
æt
ö
t
VOUT(MIN) = VIN ç ON ÷ - IOUT (RDS + RL ) - 0.7V - (IOUT ´ RDS ) DEAD
t
tS
è S ø
(
)
(32)
where:
•
•
24
VOUT(MIN) = minimum achievable output voltage
tON = minimum controllable on time (64 ns - 100 nsec typical)
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•
•
•
•
•
•
SLVSB69C – JUNE 2012 – REVISED SEPTEMBER 2021
tS = 1/fSW (switching frequency)
tDEAD = dead time (70 nsec typical)
VIN = maximum input voltage
RDS = minimum high side MOSFET on resistance (26 - 35 mΩ)
IOUT = minimum load current
RL = series resistance of output inductor
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 33
æ
ö
t
t
VOUT(MAX) = VIN ç 1 - OFF ÷ - IOUT (RDS + RL ) - VIN + 0.7V - (IOUT ´ RDS ) DEAD
t
tS
S ø
è
(
)
(33)
where:
•
•
•
•
•
•
•
•
VOUT(MAX) = maximum achievable output voltage
tS = 1/fSW (switching frequency)
tOFF = minimum off time (0 nsec typical)
tDEAD = dead time (70 nsec typical)
VIN = minimum input voltage
IOUT = maximum load current
RDS = maximum high side MOSFET on resistance (60 - 70 mΩ)
RL = series resistance of output inductor
8.2.3.9 Compensation
There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at -20 dB/decade above the modulator pole frequency. The power stage phase is
0 degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of -90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole
shown in Equation 34.
¦ p m od =
Iout m ax
2 p ´ Vout ´ Cout
(34)
For the TPS54719, most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will now approach -180 degrees, making compensation more difficult. The power
stage transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple
approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that
a reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the
pspice model of (insert link here). Apply the values calculated previously to the output filter components of L1,
C9 and C10. Set Rload to the appropriate value. For this design, L1 = 1.5 µH. C9 and C10 are set to 22 µF
each, and the ESR is set to 3 mΩ. The Rload resistor is 1.8 V / 3.5 A = 514 mΩ for one half rated load. Now the
power stage characteristic can be plotted as shown in Figure 8-1.
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60
180
Gain
Phase
40
30
Gain = 2.04 dB @ 50 kHz
Gain (dB)
20
150
120
90
60
10
30
0
−10
0
−30
−20
−60
−30
−90
−40
−120
−50
−60
100
1000
10000
Frequency (Hz)
100000
Phase (°)
50
−150
−180
1000000
G006
Figure 8-1. Power Stage Gain And Phase Characteristics
For this design, the intended crossover frequency is 50 kHz. From the power stage gain and phase plots, the
gain at 50 kHz is 2.04 dB and the phase is about –135 degrees. For 60 degrees of phase margin, additional
phase boost from a feedforward capacitor in parallel with the upper resistor of the voltage set point divider will be
required. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at
crossover. The required value of R3 can be calculated from Equation 35.
R3 =
-GPWRSTG
10 20
×
gmEA
Vout
VREF
(35)
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 50 kHz.
The required value for C6 is given by Equation 36.
C6 =
1
2 × p × R3 ×
FCO
10
(36)
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 50 kHz.
The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. The value for C5 can
be calculated from Equation 37.
C5 =
1
2 × p × R3 × FP
(37)
For maximum phase boost, the pole frequency FP will typically be one decade above the intended crossover
frequency FCO.
The feedforward capacitor, C11, is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair located at Equation 38 and Equation
39.
FZ =
26
1
2 × p × C11× R6
(38)
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FP =
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1
2 × p × C11× R6 P R7
(39)
This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well.
For optimum performance, the zero and pole should be located symmetrically about the intended crossover
frequency. The required value for C10 can calculated from Equation 40.
1
C11 =
2 × p × R6 × FCO ×
VREF
VOUT
(40)
For this design the calculated values for the compensation components are R3 = 5.49 kΩ, C6 = 5600 pF, C5 =
56 pF, and C11 = 270 pF.
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
8.2.4 Application Curves
60
50
40
30
50
40
30
20
20
VIN = 3.3 V
VIN = 5 V
10
0
60
0
1
2
3
4
Output Current (A)
5
6
7
0
0.01
G002
Figure 8-2. Efficiency vs Load Current
VIN = 3.3 V
VIN = 5 V
10
0.1
1
Output Current (A)
10
G003
Figure 8-3. Efficiency vs Load Current
VIN = 5 V / div
VOUT = 100 mV / div (ac coupled)
EN = 2 V / div
PWRGD = 5 V / div
IOUT = 2 A / div
VOUT = 1 V / div
Load step = 1.75 - 5.25 A, slew rate = 30 mA / µsec
Time = 500 µsec / div
Time = 2 msec / div
Figure 8-4. Transient Response, 3.5 A Step
Figure 8-5. Power Up Relative To VIN
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VIN = 5 V / div
VIN = 5 V / div
EN = 2 V / div
EN = 2 V / div
PWRGD = 5 V / div
PWRGD = 5 V / div
VOUT = 1 V / div
VOUT = 1 V / div
Time = 2 msec / div
Time = 2 msec / div
Figure 8-6. Power Down Relative To VIN
Figure 8-7. Power Up Relative To EN
VIN = 5 V / div
VOUT = 20 mV / div (ac coupled)
EN = 2 V / div
PWRGD = 5 V / div
PH = 2 V / div
VOUT = 1 V / div
Time = 1 µsec / div
Time = 200 µsec / div
Figure 8-9. Output Ripple, IOUT = 7 A
Gain (dB)
VIN = 100 mV / div (ac coupled)
PH = 2 V / div
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
100
180
150
120
90
60
30
0
−30
−60
−90
−120
−150
−180
1000000
Gain
Phase
1000
10000
Frequency (Hz)
100000
Phase (°)
Figure 8-8. Power Down Relative To EN
G001
Figure 8-11. Closed Loop Response, VIN = 5 V, IOUT
= 3.5 A
Time = 1 µsec / div
Figure 8-10. Input Ripple, IOUT = 7 A
28
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0.5
0.1
VIN = 3.3 V
VIN = 5 V
0.08
Output Voltage Deviation (%)
Output Voltage Deviation (%)
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.4
−0.08
−0.5
−0.1
0
1
2
3
4
Output Current (A)
5
6
7
IOUT = 3 A
3
G005
Figure 8-12. Output Voltage Regulation vs Load
Current
3.5
4
4.5
5
Input Voltage (V)
5.5
6
G004
IOUT = 3 A
Figure 8-13. Output Voltage Regulation vs Input
Voltage
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9 Power Supply Recommendations
The input voltage for VIN pin should be well controlled to avoid exceeding the maximum voltage rating of 7 V;
otherwise, the device can have risk of damage.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 10-1 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect
the top side ground area to the internal planes near the input and output capacitors. For operation at full rated
load, the top side ground area along with any additional internal ground planes must provide adequate heat
dissipating area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located very close to
the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected
to a separate analog ground trace as shown. The RT pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
30
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10.2 Layout Example
VIA to
Ground
Plane
UVLO SET
RESISTORS
VIN
INPUT
BYPASS
CAPACITOR
BOOT
PWRGD
EN
VIN
VIN
BOOT
CAPACITOR
VIN
OUTPUT
INDUCTOR
PH
VIN
PH
EXPOSED
POWERPAD
AREA
GND
PH
GND
PH
VOUT
OUTPUT
FILTER
CAPACITOR
SLOW START
CAPACITOR
RT
COMP
VSENSE
AGND
SS/TR
FEEDBACK
RESISTORS
ANALOG
GROUND
TRACE
FREQUENCY
SET
RESISTOR
TOPSIDE
GROUND
AREA
COMPENSATION
NETWORK
VIA to Ground Plane
Figure 10-1. PCB Layout Example
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10.2.1 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode
(CCM) operation. The power dissipation of the IC (Ptot) includes the following:
•
•
•
•
•
Conduction loss (Pcon)
Dead time loss (Pd)
Switching loss (Psw)
Gate drive loss (Pgd)
Supply current loss (Pq)
Pcon = Io2 × Rdson_temp
Pd = ƒsw × Iout × 0.7 × 70 × 10-9
Psw = 0.5 × Vin × Io × ƒsw × 9 × 10-9
Pgd = 2 × Vin × 6 × 10-9 × ƒsw
Pq = 455 × 10-6 × Vin
where:
•
•
•
•
IOUT is the output current (A)
Rdson is the on-resistance of the high-side MOSFET (Ω)
VIN is the input voltage (V)
ƒsw is the switching frequency (Hz)
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 140°C
TAmax = TJMAX – Rth × Ptot
where:
•
•
•
•
•
•
Ptot is the total device power dissipation (W)
TA is the ambient temperature (°C)
TJ is the junction temperature (°C)
Rth is the thermal resistance of the package (°C/W)
TJMAX is maximum junction temperature (°C)
TAMAX is maximum ambient temperature (°C)
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
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Scale
60 °C
TPS54719
25 °C
Maximum Case
Temp = 72.8 °C
Figure 10-2. Thermal Image, IOUT = 7 A
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
WEBENCH™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54719RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
54719
TPS54719RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 140
54719
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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