6,4 mm X 9,7 mm
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
4-V TO 6-V INPUT, 8-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETS (SWIFT™)
FEATURES
D 30-mΩ MOSFET Switches for High Efficiency
D
D
D
D
D
D
at 8-A Continuous Output
0.9-V to 3.3-V Adjustable Output Voltage
Range With 1% Accuracy
Externally Compensated
Fast Transient Response
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
D Low-Voltage, High-Density Systems With
Power Distributed at 5 V
D Point of Load Regulation for High
D
D
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
DESCRIPTION
As a member of the SWIFT™ family of dc/dc regulators,
the TPS54810 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance under transient conditions and flexibility in
choosing the output filter L and C components; an
under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3.8 V; an internally or
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
The TPS54810 is available in a thermally enhanced
28-pin TSSOP (PWP) PowerPAD™ package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT™ designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
SIMPLIFIED SCHEMATIC
Input
VIN
Output
PH
VI = 5 V
VO = 3.3 V
95
90
TPS54810
BOOT
PGND
85
Efficiency − %
VBIAS
EFFICIENCY AT 700 HZ
100
VSENSE
COMP
80
75
70
65
60
AGND VSENSE
55
Compensation Network
50
0
1
2
3
4
5
6
7
8
9
10
IL − Load Current − A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
OUTPUT VOLTAGE
PACKAGE
PART NUMBER
−40°C to 85°C
0.9 V to 3.3 V
PLASTIC HTSSOP (PWP)(1)
TPS54810PWP
(1)
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54810PWPR). See the application section
of the data sheet for PowerPAD™ drawing and layout information.
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54810
I
Input
t voltage
lta range,
a
VI
O t t voltage
Output
lta range,
a
VO
VIN, SS/ENA, SYNC
−0.3 to 7
RT
−0.3 to 6
VSENSE
−0.3 to 4
BOOT
−0.3 to 17
VBIAS, COMP, PWRGD
−0.3 to 7
PH
−0.6 to 10
PH
S
Source
current,
t IO
Sink current, IS
Voltage differential
UNIT
V
V
Internally Limited
COMP, VBIAS
6
mA
PH
12
A
COMP
6
SS/ENA, PWRGD
10
AGND to PGND
mA
A
±0.3
V
Operating virtual junction temperature range, TJ
−40 to 125
°C
Storage temperature, Tstg
−65 to 150
°C
300
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage range, VI
Operating junction temperature, TJ
NOM
MAX
UNIT
4
6
V
−40
125
°C
DISSIPATION RATINGS(1) (2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28-Pin PWP with solder
18.2 °C/W
5.49 W(2)
3.02 W
2.20 W
28-Pin PWP without solder
40.5 °C/W
2.48 W
1.36 W
0.99 W
(1)
For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2)
Test Board Conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3)
Maximum power dissipation may be limited by over current protection.
2
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
Quiescent current
4.0
6.0
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
11
15.8
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
16
23.5
Shutdown, SS/ENA = 0 V
1.0
1.4
3.8
3.85
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
3.40
3.50
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO (1)
V
BIAS VOLTAGE
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS) = 0
2.70
2.80
(2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
0.900
V
REGULATION
Line regulation(1) (3)
Load regulation(1) (3)
IL = 4 A, fs = 350 kHz, TJ = 85°C
0.04
IL = 4 A, fs = 550 kHz, TJ = 85°C
0.04
IL = 0 A to 8 A, fs = 350 kHz, TJ = 85°C
0.03
IL = 0 A to 8 A, fs = 550 kHz, TJ = 85°C
0.03
%/V
%/A
OSCILLATOR
Internally set—free
set free running frequency range
Externally set
set—free
free running frequency range
High level threshold, SYNC
SYNC ≤ 0.8 V,
RT open
280
350
420
SYNC ≥ 2.5 V,
RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 68 kΩ (1% resistor to AGND)
663
700
762
2.5
Frequency range, SYNC (1)
0.8
50
(1)
Specified by design
(2)
Static resistive loads only
(3)
Specified by the circuit used in Figure 9
kHz
V
1
Minimum controllable on time (1)
Maximum duty cycle (1)
700
0.75
Ramp amplitude (peak-to-peak) (1)
V
ns
330
Ramp valley (1)
kHz
V
Low level threshold, SYNC
Pulse duration, external sychronization, SYNC (1)
kHz
V
200
ns
90%
3
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS CONTINUED
TJ = −40°C to 125°C, VI = 4 V to 6 V unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND(1)
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to
Error amplifier common mode input voltage
range
Powered by internal LDO(1)
Input bias current, VSENSE
VSENSE = Vref
AGND(1)
90
110
3
5
0
60
Output voltage slew rate (symmetric), COMP
1.0
dB
MHz
VBIAS
V
250
nA
1.4
V/µs
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding deadtime)
10-mV overdrive(1)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
0.82
(1)
Falling edge deglitch, SS/ENA (1)
Internal slow-start time
2.6
Charge current, SS/ENA
SS/ENA = 0V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
0.03
V
2.5
µs
3.35
4.1
ms
3
5
8
µA
1.5
2.3
4.0
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis voltage(1)
Power good falling edge
deglitch(1)
90
%Vref
3
%Vref
35
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 3.6 V
0.18
µs
0.3
V
1
µA
CURRENT LIMIT
VI = 4.5 V(1), output shorted
Current limit
VI = 6
V(1), output
shorted
9
11
10
12
A
Current limit leading edge blanking time
100
ns
Current limit total response time
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown
135
hysteresis(1)
150
165
10
_C
_C
OUTPUT POWER MOSFETS
rDS(on)
P
Power
MOSFET switches
it h
VI = 6 V(2)
VI = 4.5
V(2)
(1)
Specified by design
(2)
Matched MOSFETs, low-side rDS(on) production tested, high-side rDS(on) production tested.
4
26
47
30
60
mΩ
Ω
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE.
PGND
15−19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point
connection to AGND is recommended.
PH
6−14
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
27
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE
20−24
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 10-µF ceramic capacitor.
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
FUNCTIONAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
1.2 V
Hysteresis: 0.03 V
Falling
Edge
Deglitch
2.5 µs
VIN UVLO
Comparator
VIN
3.8 V
Hysteresis: 0.16 V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-Start
(Internal Slow-Start Time = 3.35 ms)
PH
+
−
R Q
Error
Amplifier
Reference
VREF = 0.891 V
S
PWM
Comparator
VIN
OSC
PGND
Powergood
Comparator
VSENSE
0.90 Vref
TPS54810
Hysteresis: 0.03 Vref
COMP
RELATED DC/DC PRODUCTS
D TPS56300—dc/dc controller
D PT6600 series—9-A plugin modules
6
RT
SYNC
SHUTDOWN
LOUT
CO
Adaptive Dead-Time
and
Control Logic
30 mΩ
VSENSE
3−6V
Leading
Edge
Blanking
Falling
Edge
Deglitch
35 µs
PWRGD
VO
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
INTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
60
f − Internally Set Oscillator Frequency − kHz
Drain Source On-State Reststance − m Ω
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
VI = 5 V,
IO = 8 A
50
40
30
20
10
0
−40
−15
10
35
60
85
110
135
750
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
TJ − Junction Temperature − °C
0
25
Figure 1
500
RT = 100 k
400
300
0.893
Device Power Losses − W
RT = 68 k
0.891
0.889
0.887
25
85
125
−40
0
25
85
TJ − Junction Temperature − °C
Figure 3
0
1
2
3
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
120
0.893
100
Gain − dB
0.891
0.889
Phase
Gain
20
0.887
5.4
VI − Input Voltage − V
5.7
6
−20
−40
−80
−140
−160
0
−180
1
10
100
−200
1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 7
7
8
3.80
−120
40
6
−20
−100
60
5
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
0
−60
80
4
IL − Load Current − A
Figure 5
Phase − Degrees
140
Figure 6
VI = 5 V
1
ERROR AMPLIFIER
OPEN LOOP RESPONSE
0.895
5.1
2
1.5
Figure 4
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
4.8
125
Internal Slow-Start Time − ms
0
3
2.5
0
0.885
200
−40
4
3.5
0.5
RT = 180 k
TJ − Junction Temperature − °C
VO − Output Voltage Regulation − V
TJ = 125°C
fs = 700 kHz
4.5
600
4.5
DEVICE POWER LOSSES
vs
LOAD CURRENT
5
0.895
V ref − Voltage Reference − V
f − Externally Set Oscillator Frequency − kHz
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
800
700
125
Figure 2
EXTERNALLY SET
OSCILLATOR FREQUENCY
vs
JUNCTION TEMPERATURE
0.885
85
TJ − Junction Temperature − °C
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
125
TJ − Junction Temperature − °C
Figure 8
7
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical
TPS54810 application. The TPS54810 (U1) can provide
up to 8 A of output current at a nominal output voltage of
VI
C10
10 µF
C12
10 µF
R6
U1
TPS54810PWP
28
VIN
27
C6
C1
1000 pF
R2
R3
301 Ω
10 kΩ
C4
C2
VIN
SYNC
VIN
26
VIN
SS/ENA
0.047 µF
25
C3
1 µF
VIN
RT
71.5 kΩ
R5
10 kΩ
PH
PH
VBIAS
PH
4
PH
PWRGD
PH
3
PH
COMP
3300 pF
PH
PH
R1
10 kΩ
150 pF
1.8 V. For proper thermal performance, the PowerPAD
underneath the integrated circuit TPS54810 needs to be
soldered well to the printed-circuit board.
2
PH
VSENSE
BOOT
PGND
R4
9.76 kΩ
PGND
1
PGND
AGND
PGND
PGND
PWRPAD
24
23
22
21
20
14
13
12
11
L1
0.65 µH
10
9
8
C8
22 µF
7
C7
22 µF
C5
22 µF
VO
6
5
C9
19
0.047 µF
18
R7
2.4 Ω
17
16
15
C11
3300 pF
Analog and Power Grounds are Tied at the Pad Under the Package of IC
Figure 9. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example were selected for low output ripple voltage and
small PCB area. Additional design information is available
at www.ti.com.
INPUT FILTER
The input voltage is a nominal 5 VDC. The input filter C10
is a 10-µF ceramic capacitor (Taiyo Yuden). C12, also a
10-µF ceramic capacitor (Taiyo Yuden) provides high
frequency decoupling of the TPS54810 from the input
supply and must be located as close as possible to the
device. Ripple current is carried in both C10 and C12, and
the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, and C8.
FEEDBACK CIRCUIT
The values for these components have been selected to
provide low output ripple voltage. The resistor divider
network of R1 and R4 sets the output voltage for the circuit
8
at 1.8 V. R1, along with R2, R3, C1, C2, and C4 forms the
loop compensation network for the circuit. For this design,
a Type 3 topology is used.
OPERATING FREQUENCY
In the application circuit, RT is grounded through a 71.5 kΩ
resistor to select the operating frequency of 700 kHz. To
set a different frequency, place a 68 kΩ to 180 kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default of 350 kHz. The resistance can
be approximated using the following equation:
R+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor and
3 x 22-µF capacitor. The inductor is a low dc resistance
(0.017 Ω) type, Pulse Engineering PA0277. The
capacitors used are 22-µF, 6.3 V ceramic types with X5R
dielectric. The feedback loop is compensated so that the
unity gain frequency is approximately 75 kHz.
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TPS54810
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PCB LAYOUT
Figure 10 shows a generalized PCB layout guide for the
TPS54810
The VIN pins are connected together on the printed-circuit
board (PCB) and bypassed with a low-ESR
ceramic-bypass capacitor. Care should be taken to
minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS54810 ground
pins. The minimum recommended bypass capacitance is
10-µF ceramic capacitor with a X5R or X7R dielectric and
the optimum placement is closest to the VIN pins and the
PGND pins.
The TPS54810 has two internal grounds (analog and
power). Inside the TPS54810, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54810, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground traces are
recommended. There is an area of ground on the top layer
directly under the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to
any internal ground planes. Additional vias are also used
at the ground side of the input and output filter capacitors.
The AGND and PGND pins are tied to the PCB ground by
connecting them to the ground area under the device as
shown. The only components that tie directly to the power
ground plane are the input capacitors, the output
capacitors, the input voltage decoupling capacitor, and the
PGND pins of the TPS54810. Use a separate wide trace
for the analog ground signal path. The analog ground is
used for the voltage set point divider, timing resistor RT,
slow-start capacitor and bias capacitor grounds. Connect
this trace directly to AGND (Pin 1).
The PH pins are tied together and routed to the output
inductor. Since the PH connection is the switching node,
the inductor is located close to the PH pins. The area of the
PCB conductor is minimized to prevent excessive
capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, LOUT, COUT and PGND as small as
practical.
Place the compensation components from the VOUT trace
to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin-out, they must be routed
close, but maintain as much separation as possible while
still keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC
pin is used to select 350-kHz operating frequency, connect
them to this trace.
9
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
VSENSE
COMPENSA TION
NETWORK
COMP
SYNC
SLOW ST ART
CAPACITOR
SS/ENA
BIAS CAP ACITOR
PWRGD
BOOT
CAP ACITOR
BOOT
PH
VOUT
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
VBIAS
VIN
EXPOSED
POWERP AD
AREA
VIN
PH
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
PH
PGND
PH
PGND
VIN
INPUT
BYP ASS
CAPACITOR
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 10. PCB Layout
10
INPUT
BULK
FILTER
TPS54810
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SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
8 PL Ø 0.0130
4 PL
Ø 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
any area available should be used when 8 A or greater
operation is desired. Connection from the exposes area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance should be included in
areas not under the device package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
0.1700
Minimum Recommended Top
Side Analog Ground Area
0.1340
Minimum Recommended Exposed
Copper Area for Powerpad. 5-mil
Stencils May Require 10 Percent
Larger Area
0.0630
0.0400
Figure 11. Recommended Land Pattern for the 28−Pin PWP PowerPAD
11
TPS54810
www.ti.com
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
PERFORMANCE GRAPHS (FROM APPLICATION CIRCUIT SHOWN IN FIGURE 9)
EFFICIENCY
vs
OUTPUT CURRENT
1.003
VI = 5 V
VO = 1.8 V
fs = 700 kHz
95
90
Load Regulation
75
70
65
60
1.001
1
0.999
0
2
4
6
8
10
1
0.9998
4A
0.9996
0A
0.9994
0
2
4
6
8
10
OUTPUT RIPPLE VOLTAGE
105
VI = 5 V
85
75
65
55
45
35
25
0
1
2
3
4
5
6
IO − Output Current − A
7
VI = 5 V
VO = 1.8 V
IO = 6 A
fs = 700 kHz
t − Time − 20 µs/div
Figure 16
Figure 15
Figure 17
VI = 5 V,
0.04 µF
Slow-start Cap
Output Voltage − 2 V/div
Input Voltage − 2 V/div
SLOW-START TIMING
4.0 ms/div
Figure 18
Safe operating area is applicable to the test board conditions in the Dissipation Ratings
5.9
VI = 5 V
2 A to 6.5 A
t − Time − 1 µs/div
8
4.9 5.1 5.3 5.5 5.7
VI − Input Voltage − V
TRANSIENT RESPONSE
VO − Output Voltage − 100 mV/div
Output Ripple Voltage − 10 mV/div
TJ = 25°C
fs = 700 kHz
95
4.7
Figure 14
125
115
0.999
4.5
Figure 13
AMBIENT TEMPERATURE
vs
OUTPUT CURRENT (1)
T A − Ambient Temperature − ° C
1.0002
IO − Output Current − A
Figure 12
12
1.0004
0.9992
0.997
IO − Output Current − A
(1)
VI = 5 V
VO = 1.8 V
TA = 25°C
fs = 700 kHz
8A
1.0006
0.998
55
50
1.0008
I O − Output Current − 2 A/div
Efficiency − %
80
1.001
VI = 5 V
VO = 1.8 V
TA = 25°C
fs = 700 kHz
1.002
85
LINE REGULATION
vs
INPUT VOLTAGE
Line Regulation
100
LOAD REGULATION
vs
OUTPUT CURRENT
TPS54810
www.ti.com
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54810 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 3.80 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
3.5 V. Hysteresis in the UVLO comparator, and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
t +C
d
(SS)
1.2 V
5 mA
(2)
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
ramp-up time set by the capacitor is approximately:
t
(d)
+C
(SS)
0.7 V
5 mA
(3)
The actual ramp-up time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54810, since it cancels
offset errors in the scale and error amplifier circuits.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
Switching Frequency + 100 kW
R
500 [kHz]
(4)
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose an RT resistor which
sets the free running frequency to 80% of the
synchronization signal. The following table summarizes
the frequency selection configurations:
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
=2.5 V
Float
Externally set 280 kHz
to 700 kHz
Float
R = 68 k to 180 k
Externally synchronized frequency
Synchronization
signal
R = RT value for 85%
of external synchronization frequency
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54810 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
13
TPS54810
www.ti.com
SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005
particular application needs. Type 2 or type 3 compensation can be employed using external compensation
components.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54810 is capable of sinking current continuously
until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
14
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
Overcurrent Protection
The cycle by cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge
blanking circuit prevents false tripping of the current limit
when the high side switch is turning on. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low. When
VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and
VSENSE > 90% of Vref, the open drain output of the
PWRGD pin is high. A hysteresis voltage equal to 3% of
Vref and a 35 µs falling edge deglitch circuit prevent
tripping of the power good comparator due to high
frequency noise.
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS54810PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54810
TPS54810PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54810
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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