TPS54872PWPR

6,4 mm x 9,7 mm
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005  

 
   

 

   
 
 

 
 
! FEATURES D Tracks Externally Applied Reference Voltage D 30-mΩ MOSFET Switches for High Efficiency D D D D at 8-A Continuous Output Source or Sink Current 6% to 90% VI Output Tracking Range Wide PWM Frequency: Fixed 350 kHz or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS D DDR Memory Termination Voltage D Active Termination of GTL and SSTL D D High-Speed Logic Families DAC Controlled High Current Output Stage Precision Point of Load Power Supply DESCRIPTION As a member of the SWIFT family of dc/dc regulators, the TPS54872 low-input voltage high-output current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3.8 V; an internally set slow-start circuit to limit in-rush currents; and a status output to indicate valid operating conditions. The TPS54872 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. SIMPLIFIED SCHEMATIC VIN PH TPS54872 BOOT PGND REFIN V(TTQ) COMP VBIAS AGND VSENSE Compensation Network VI = 5 V, VO = 1.25 V 2 A to 6 A I O − Output Current − 2 A/div V(DDQ) VO − Output Voltage − 20 mV/div TRANSIENT RESPONSE Input t − Time − 100 ms/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD and SWIFT are trademarks of Texas Instruments. 
 
"#$%&'()"%# " *+&&,#) ( %$ -+./"*()"%# 0(),1 &%0+*) *%#$%&' )% -,*"$"*()"%# -,& )2, ),&' %$
,3( #)&+',#) )(#0(&0 4(&&(#)51 &%0+*)"%# -&%*,"#6 0%, #%) #,*,(&"/5 "#*/+0, ),)"#6 %$ (// -(&(',),&1 Copyright  2002 − 2005, Texas Instruments Incorporated 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C REFIN VOLTAGE 0.2 V to 1.75 V PACKAGE Plastic HTSSOP (PWP)(1) PART NUMBER TPS54872PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54872PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) TPS54872 Input voltage range, VI Output voltage range, VO VIN, ENA −0.3 V to 7 RT −0.3 V to 6 VSENSE, REFIN −0.3 V to 4 BOOT −0.3 V to 17 VBIAS, COMP, STATUS −0.3 V to 7 PH −0.6 V to 10 PH Source current, IO Sink current, IS UNITS V V Internally Limited COMP, VBIAS 6 mA PH 12 A COMP 6 ENA, STATUS 10 mA ±0.3 V Operating virtual junction temperature range, TJ −40 to 125 °C Storage temperature, Tstg −65 to 150 °C Voltage differential AGND to PGND Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 4 6 V −40 125 °C Input voltage, VI Operating junction temperature, TJ NOM DISSIPATION RATINGS(1)(2) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 28 Pin PWP with solder 14.4°C/W 6.94 W(3) 3.81 W 2.77 W 1.97 W 1.43 W 28 Pin PWP without solder 27.9°C/W 3.58 W (1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002. (2) Test board conditions: 1. 3” x 3”, 4 layers, thickness: 0.062” 2. 1.5 oz. copper traces located on the top of the PCB 3. 1.5 oz. copper ground plane on the bottom of the PCB 4. 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet) (3) Maximum power dissipation may be limited by overcurrent protection. 2 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 4 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 11 15.8 16 23.5 1 1.4 3.80 3.85 UNIT SUPPLY VOLTAGE, VIN VIN I(Q) Input voltage range Quiescent current 4.0 fs = 350 kHz, RT open, PH pin open fs = 500 kHz, RT = 100 kΩ, PH pin open Shutdown, SS/ENA = 0 V 6.0 V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO V Stop threshold voltage, UVLO 3.40 3.50 Hysteresis voltage, UVLO 0.14 0.16 V 2.5 µs Rising and falling edge deglitch, UVLO(1) V BIAS VOLTAGE Output voltage, VBIAS I(VBIAS) = 0 2.70 2.80 Output current, VBIAS (2) 2.90 V 100 µA 0.04 %/V 0.03 %/A kHz REGULATION Line regulation(1)(3) Load regulation(1)(3) IL = 4 A, fs = 350 kHz, TJ = 85°C IL = 0 A to 8 A, fs = 350 kHz, TJ = 85°C OSCILLATOR Internally set free running frequency Externally set free running frequency range RT open 280 350 420 RT = 180 kΩ (1% resistor to AGND) 252 280 308 RT = 100 kΩ (1% resistor to AGND) 460 500 540 RT = 68 kΩ (1% resistor to AGND) 663 700 762 Ramp valley(1) 0.75 Ramp amplitude (peak-to-peak)(1) Minimum controllable on time(1) V 1 V 200 Maximum duty cycle(1) kHz ns 90% ERROR AMPLIFIER Error amplifier open loop voltage gain 1 kΩ COMP to AGND(1) Error amplifier unity gain bandwidth Error amplifier common mode input voltage range Parallel 10 kΩ, 160 pF COMP to AGND(1) Powered by internal LDO(1) Input bias current, VSENSE VSENSE = Vref Output voltage slew rate (symmetric), COMP 90 110 3 5 0 60 1.0 dB MHz VBIAS V 250 nA 1.4 V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding deadtime) 10-mV overdrive(1) 70 85 ns (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 8 3 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 4 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.82 1.20 1.40 V SLOW-START/ENABLE Enable threshold voltage, ENA Enable hysteresis voltage, ENA(1) Falling edge deglitch, ENA(1) Internal slow-start time 2.6 0.03 V 2.5 µs 3.35 4.1 ms 0.18 0.30 V 1 µA STATUS Output saturation voltage, PWRGD Leakage current, PWRGD Isink = 2.5 mA VI = 3.6 V CURRENT LIMIT Current limit 11 A Current limit leading edge blanking time VI = 4.5 V 9 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point(1) Thermal shutdown hysteresis(1) 135 150 165 °C °C 10 OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches VI = 4.5 V(4) VI = 6 V(4) (1) Specified by design (2) Static resistive loads only (3) Specified by the circuit used in Figure 7 (4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) production tested. 4 30 60 25 50 mΩ 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 TPS54872 Externally Composed Pin-Out 28 Pin HTSSOP PowerPAD (TOP VIEW) AGND VSENSE COMP STATUS BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 21 PAD 20 19 18 17 16 15 RT ENA REFIN VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD connection to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE ENA 27 Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and places device in a low quiescent current state. PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. REFIN 26 External reference input. High impedance input to slow-start and error amplifier circuits. STATUS 4 Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal shutdown signal is active. Otherwise STATUS is high. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. VIN VSENSE 2 Error amplifier inverting input. Connect to output voltage compensation network/output divider. 5 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 INTERNAL BLOCK DIAGRAM ENABLE COMPARATOR ENA TPS54872 VIN 1−4 µs VIN UVLO COMPARATOR BIAS REG VIN Falling Edge Delay 0.8 V VDDQ Vbias SHUTDOWN UVLO highdr UVLO highin Rising Edge Delay /T_SHUT FAULT BIAS UVLO BG GOOD Delay REFIN Rising Edge Delay SHUTDOWN Vin_uvlo SAMPLING LOGIC VPHASE Vilim VIN BOOT SHUTDOWN ILIM COMPARATOR SHUTDOWN highin highdr Reference/DAC VSENSE MUX PWM COMPARATOR ERROR AMPLIFIER R Q C S SHUTDOWN PGND OSC Ct Iset AGND RT RELATED DC/DC PRODUCTS D TPS54372 D TPS54672 6 Lout PH DEADTIME FAULT STATUS O V TTQ 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 50 40 30 20 10 0 −40 −15 10 35 60 85 110 135 TJ − Junction Temperature − °C 750 650 550 450 RT = Open 350 250 −40 0 85 3.5 3 2.5 2 1.5 VI = 5 V 1 0 4 5 IL − Load Current − A Figure 4 200 −40 0 6 7 8 25 85 125 Figure 3 ERROR AMPLIFIER OPEN LOOP RESPONSE 0 140 RL = 10 kΩ, CL = 160 pF, TA = 25°C 120 3.65 100 −20 −40 −60 3.50 3.35 3.20 80 Phase −120 40 20 2.90 0 2.75 −20 −80 −100 60 3.05 Gain −140 −160 0.5 3 300 TJ − Junction Temperature − °C Gain − dB Internal Slow-Start Time − ms 4 2 400 125 3.80 TJ = 125°C fs = 700 kHz 1 500 INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE 5 0 600 Figure 2 DEVICE POWER LOSSES vs LOAD CURRENT 4.5 700 TJ − Junction Temperature − °C Figure 1 Device Power Losses − W 25 800 Phase − Degrees VI = 5 V, IO = 8 A EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE f − Externally Set Oscillator Frequency − kHz 60 f − Internally Set Oscillator Frequency − kHz Drain Source On-State Reststance − m Ω DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE −40 0 25 85 TJ − Junction Temperature − °C Figure 5 125 −180 1 10 100 −200 1 k 10 k 100 k 1 M 10 M f − Frequency − Hz Figure 6 7 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 APPLICATION INFORMATION Figure 7 shows the schematic diagram for a typical TPS54872 application. The TPS54872 (U1) can provide up to 8 A of output current at a nominal output voltage of one half of V(DDQ) (typically 1.25 V). For proper operation, the PowerPAD underneath the integrated circuit TPS54872 is soldered directly to the printed-circuit board. VIN C4 10 µF R2 10 kΩ C2 470 pF C6 0.047 µF C1 12 pF R3 301 Ω R1 10 kΩ VDDQ U1 TPS54872PWP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C3 470 pF RT AGND VSENSE ENA COMP REFIN STATUS VBIAS BOOT VIN PH VIN PH VIN PH VIN VIN PH PH PGND PH PGND PH PGND PGND PH PH PGND PwrPad 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R6 10 kΩ C10 1 µF R7 10 kΩ R5 71.5 kΩ C13 0.1 µF C14 0.1 µF C8 10 µF VTTQ C12 1 µF C11 22 µF C9 22 µF C7 22 µF R4 2.4 W L1 0.65 µH C5 3300 pF Figure 7. Application Circuit COMPONENT SELECTION FEEDBACK CIRCUIT The values for the components used in this design example were selected for good transient response and small PCB area. Ceramic dielectric capacitors are utilized in the output filter circuit. A small size, small value output inductor is also used. Compensation network components are chosen to maximize closed loop bandwidth and provide good transient response characteristics. Additional design information is available at www.ti.com. The values for these components are selected to provide fast transient response times. Components R1 R2, R3, C1, C2, and C3 forms the loop compensation network for the circuit. For this design, a type 3 topology is used. The transfer function of the feedback network is chosen to provide maximum closed loop gain available with open loop characteristics of the internal error amplifier. Closed loop cross-over frequency is typically between 80 kHz and 125 kHz for input from 4 V to 6 V. INPUT VOLTAGE OPERATING FREQUENCY The input voltage is a nominal 5.0 VDC. The input filter (C4) is a 10-µF ceramic capacitor (Taiyo Yuden). Capacitor C8, a 10-µF ceramic capacitor (Taiyo Yuden) that provides high frequency decoupling of the TPS54872 from the input supply, must be located as close as possible to the device. Ripple current is carried in both C4 and C8, and the return path to PGND should avoid the current circulating in the output capacitors C7, C9, C11, and C12. 8 In the application circuit, RT is grounded through a 71.5 kΩ resistor to select the operating frequency of 700 kHz. To set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 28) and analog ground or leave RT floating to select the default of 350 kHz. The resistance can be approximated using the following equation: R+ 500 kHz Switching Frequency 100 [kW] (1) www.ti.com
 SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 OUTPUT FILTER The output filter is composed of a 0.65-µH inductor and three 22-µF capacitors. The inductor is a low dc resistance (0.017 Ω) type, Pulse PA0277 0.65-µH. The capacitors used are 22 µF, 6.3-V ceramic types with X5R dielectric. An additional 1-µF output capacitor (C12) is included to suppress high frequencies. PCBLAYOUT Figure 8 shows a generalized PCB layout guide for the TPS54872. The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54872 ground pins. The minimum recommended bypass capacitance is 10 µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. The TPS54872 has two internal grounds (analog and power). The analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54872, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There should be an area of ground on the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the ground area under the device as shown. The only components that should tie directly to the power ground plane are the input capacitors, the output capacitors, the input voltage decoupling capacitor, and the PGND pins of the TPS54872. Use a separate wide trace for the analog ground signal path. This analog ground should be used for the voltage set point divider, timing resistor RT, and bias capacitor grounds. Connect this trace directly to AGND (Pin 1). The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching node, the inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pinout, the components will have to be routed somewhat close, but maintain as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If an RT resistor is used, connect it to this trace as well. 9 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 ANALOG GROUND TRACE AGND RT COMPENSATION NETWORK TRACKING VOLTAGE ENA VSENSE COMP REFIN RESISTOR DIVIDER BIAS CAPACITOR PWRGD BOOT CAPACITOR BOOT PH VOUT PH OUTPUT INDUCTOR OUTPUT FILTER CAPACITOR VBIAS VIN EXPOSED POWERPAD AREA VIN PH VIN PH VIN PH VIN PH PGND PH PGND PH PGND PH PGND PH PGND VIN INPUT BYPASS CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 8. TPS54872 PCB Layout 10 NETWORK 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 8 A or greater 8 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground plane in this area for optimum performance operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. Minimum recommended thermal vias: 8 x .013 dia. inside powerpad area 4 x .018 dia. under device as shown. Additional .018 dia. vias may be used if top side Analog Ground ar ea is extended. 0.0150 0.06 0.0339 0.0650 0.3820 0.0500 0.3478 0.0500 0.0500 0.2090 0.0256 0.0650 0.0339 0.1700 0.1340 Minimum recommended top side Analog Ground area Minimum recommended exposed copper area for powerpad. 5 mm stencils may required 10 percent larger area. 0.0603 0.0400 Figure 9. Recommended Land Pattern for 28-Pin PWP PowerPAD 11 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 PERFORMANCE GRAPHS EFFICIENCY vs OUTPUT CURRENT 100 1.255 fs = 700 kHz, VI = 5 V, VO = 1.25 V 95 90 1.255 fs = 700 kHz, TA = 25°C, VI = 5 V, VO = 1.25 V 1.253 80 75 70 65 60 fs = 700 kHz, TA = 25°C, VO = 1.25 V 1.253 Line Regulation Load Regulation 85 Efficiency − % LINE REGULATION vs INPUT VOLTAGE LOAD REGULATION vs OUTPUT CURRENT 1.251 1.249 1.247 1.251 IO = 0 A IO = 1.5 A 1.249 1.247 IO = 3 A 55 1.245 1.245 2 4 6 IO − Output Current − A 8 10 0 2 6 8 10 2 A to 6 A 6 VI = 5 V, VO = 1.25 V t −Time − 2.5 ms/div Figure 15 Figure 14 AMBIENT TEMPERATURE vs OUTPUT CURRENT (1) SOURCE-SINK TRANSIENT RESPONSE 125 VI = 5 V, VO = 1.25 V −4 A to 4 A t − Time − 100 µs/div Figure 16 T A − Ambient Temperature − ° C 115 I O − Output Current − 1 A/div VO − Output Voltage − 50 mV/div VI − Input Voltage − 2 V/div t − Time − 100 ms/div Figure 13 5.5 SLOW-START TIMING VI = 5 V, VO = 1.25 V t − Time − 1 µs/div 5 Figure 12 TRANSIENT RESPONSE VO − Output Voltage − 20 mV/div fs = 700 kHz, IO = 8 A, VI = 5 V, VO = 1.25 V 4.5 VI − Input Voltage − V Figure 11 OUTPUT RIPPLE VOLTAGE 12 4 IO − Output Current − A Figure 10 Output Ripple Voltage − 10 mV/div 4 I O − Output Current − 2 A/div 0 VO − Output Voltage − 500 mV/div 50 105 TJ = 125°C fs = 700 kHz VI = 5 V VO = 1.25 V 95 85 75 65 55 45 35 25 0 1 2 3 4 5 6 IO − Output Current − A 7 8 (1) Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. Figure 17 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 DETAILED DESCRIPTION UNDERVOLTAGE LOCK OUT (UVLO) The TPS54872 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 3.80 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 3.50 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. ENABLE (ENA) The enable pin, ENA, provides a digital control to enable or disable (shut down) the TPS54872. An input voltage of 1.4 V or greater ensures the TPS54872 is enabled. An input of 0.9 V or less ensures the device operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs. When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from 0 V. SLOW-START The slow-start circuit provides start-up slope control control of the output voltage to limit in-rush currents. The nominal internal slow-start rate is 0.25 V/ms with the minimum rate being 0.35 V/ms. When the voltage on REFIN rises faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the reference voltage on REFIN rises more slowly, then the output rises at approximately the same rate as REFIN. VBIAS REGULATOR (VBIAS) VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. VOLTAGE REFERENCE The REFIN pin provides an input for a user supplied tracking voltage. Typically this input is one half of V(DDQ). The input range for this external reference is 0.2 V to 1.75 V. Above this level, the internal bandgap reference overrides the externally supplied reference voltage. OSCILLATOR AND PWM RAMP The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected (floating). If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor to the RT pin to ground. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: (2) Switching Frequency + 100 kW 500 [kHz] R The following table summarizes the frequency selection configurations: SWITCHING FREQUENCY RT PIN 350 kHz, internally set Float Externally set 280 kHz to 700 kHz R = 68 kΩ to 180 kΩ ERROR AMPLIFIER The high performance, wide bandwidth, voltage error amplifier sets the TPS54872 apart from most dc/dc converters. The user has a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on 13 
 www.ti.com SLVS436C − JULY 2002 − REVISED FEBRUARY 2005 PWM CONTROL Signals from the error amplifier output, oscillator and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54872 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. DEAD-TIME CONTROL AND MOSFET DRIVERS Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver does not turn 14 on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω. bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. OVERCURRENT PROTECTION The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of the current limit when the high-side switch is turning on. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. THERMAL SHUTDOWN The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal limit trip point. This sequence repeats until the fault condition is removed. STATUS The status pin is an open drain output that indicates when internal conditions are sufficient for proper operation. STATUS can be coupled back to a system controller or monitor circuit to indicate that the termination or tracking regulator is ready for start-up. STATUS is high impedance when the TPS54872 is operating or ready to be enabled. STATUS is active low if any of the following occur: D D D VIN < UVLO threshold VBIAS or internal reference have not settled. Thermal shutdown is active. PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS54872PWP ACTIVE HTSSOP PWP 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS54872 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of