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TPS549A20
SLUSC79A – NOVEMBER 2015 – REVISED DECEMBER 2015
TPS549A20 1.5-V to 20-V (4.5-V to 25-V Bias) Input,
15-A Synchronous Step-Down SWIFT™ Converter With PMBus™
1 Features
2 Applications
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Integrated SWIFT™ 9.9-mΩ and 4.3-mΩ
MOSFETs Support 15-A Continuous IOUT
Wide Conversion Input Voltage Range: 1.5 V to
20 V (with Snubber)
Output Voltage Range from 0.6 V to 5.5 V
Available PMBus™ Adjustments
– Voltage Margin and Adjustment
– Soft-Start Time
– Power-On Delay
– VDD UVLO Level
– Fault Reporting
– Switching Frequency
Supports All Ceramic Output Capacitors
Reference Voltage: 600 mV with ±0.5% Tolerance
from –40°C to 85°C ambient temperature
D-CAP3™ Control Mode With Fast Load-Step
Response
Hiccup Over Current Protection
Auto-Skipping Eco-Mode™ for High Light-Load
Efficiency
FCCM for Tight Output Ripple and Voltage
Tolerance Requirements
Pre-charged Startup Capability
Eight Selectable Frequency Settings from
200 kHz to 1 MHz via PMBus
4.5 mm x 3.5 mm, 28-Pin, VQFN-CLIP Package
Supported at the WEBENCH™ Design Center
SWIFT™
Server, Cloud-Computing, Storage
Telecom & Networking, Point-of-Load (POL)
IPCs, Factory Automation, PLC, Test
Measurement
Performance DSPs, FPGAs
•
3 Description
The TPS549A20 is a small-sized, synchronous buck
converter with an adaptive on-time D-CAP3 control
mode. The device offers ease-of-use and low bill-ofmaterial count for space-conscious power systems.
This device features high-performance integrated
MOSFETs, accurate 0.6-V reference, and an
integrated boost switch. Competitive features include
very-low external-component count, fast loadtransient response, auto-skip mode operation,
internal soft-start control, and no requirement for
compensation. The device also features fault report
via PMBus™ to simplify the power supply design
A forced continuous conduction mode helps meet
tight voltage regulation accuracy requirements for
performance DSPs and FPGAs. The TPS549A20 is
available in a 28-pin VQFN-CLIP package and is
specified from –40°C to 125°C ambient temperature.
Device Information(1)
PART NUMBER
TPS549A20
PACKAGE
BODY SIZE (NOM)
VQFN-CLIP (28)
4.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application
PGOOD
VIN
23
22
21
20
18
19
17
16
15
FB
GND
MODE
VREG
NC
VDD
VIN
VIN
VIN
Thermal
Pad
24
VO
PGND
14
25
TRIP
PGND
13
26
ALERT
PGND
12
27
SDA
PGND
11
28
SCL
PGND
10
ADDR
PGOOD
EN
VBST
N/C
SW
SW
SW
SW
TPS549A20
1
2
3
4
5
6
7
8
9
EN
Thermal
Pad
VOUT
VREG
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS549A20
SLUSC79A – NOVEMBER 2015 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Electrical Characteristics........................................... 5
Thermal Information .................................................. 8
Typical Characteristics .............................................. 9
Thermal Performance ............................................. 15
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagrams ..................................... 16
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 23
7.5 Programming........................................................... 23
8
Application and Implementation ........................ 34
8.1 Application Information............................................ 34
8.2 Typical Application .................................................. 34
9 Power Supply Recommendations...................... 39
10 Layout................................................................... 39
10.1 Layout Guidelines ................................................. 39
10.2 Layout Example .................................................... 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
41
12 Mechanical, Packaging, and Orderable
Information ........................................................... 41
4 Revision History
Changes from Original (October 2015) to Revision A
•
2
Page
Updated document status from Product Preview to Production Data ................................................................................... 1
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SLUSC79A – NOVEMBER 2015 – REVISED DECEMBER 2015
5 Pin Configuration and Functions
SCL
SDA
ALERT
TRIP
VO
28-PIN
QFN
(TOP VIEW)
28
27
26
25
24
ADDR
1
23
FB
PGOOD
2
22
GND
EN
3
21
MODE
VBST
4
20
VREG
NC
5
19
VDD
SW
6
18
NC
SW
7
17
VIN
SW
8
16
VIN
15
VIN
Thermal Pad
10
11
12
13
14
PGND
PGND
PGND
PGND
9
PGND
SW
Pin Functions
PIN
I/O (1)
DESCRIPTION
1
I
PMBus address configuration pin. Connect this pin into a resistor divider between VREG and GND to
program different address settings
ALERT
26
O
Alert output for the PMBus interface
EN
3
I
The enable pin turns on the DC-DC switching converter.
FB
23
I
VOUT feedback input. Connect this pin to a resistor divider between the VOUT pin and GND.
GND
22
G
This pin is the ground of internal analog circuitry and driver circuitry. Connect GND to the PGND
plane with a short trace (For example, connect this pin to the thermal pad with a single trace and
connect the thermal pad to PGND pins and PGND plane).
MODE
21
I
The MODE pin sets the forced continuous-conduction mode (FCCM) or auto-skip mode operation. It
also selects the ramp coefficient of D-CAP3 mode.
NAME
NO.
ADDR
5
NC
18
—
Not connected. These pins are floating internally.
G
These ground pins are connected to the return of the internal low-side MOSFET.
10
11
PGND
12
13
14
PGOOD
2
O
Open-drain power-good status signal which provides startup delay after the FB voltage falls within the
specified limits. After the FB voltage moves outside the specified limits, PGOOD goes low within 2 µs.
SCL
28
I
Clock input for the PMBus interface
SDA
27
I/O
(1)
Data I/O for the PMBus interface
I = Input, O = Output, P = Supply, G = Ground
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Pin Functions (continued)
PIN
NAME
I/O (1)
NO.
DESCRIPTION
6
7
SW
8
I/O
SW is the output switching terminal of the power converter. Connect this pin to the output inductor.
9
TRIP
25
I/O
TRIP is the OCL detection threshold setting pin. ITRIP = 10 µA at TA = 25°C, 3000 ppm/°C current is
sourced and sets the OCL trip voltage. See the Current Sense and Overcurrent Protection section for
detailed OCP setting.
VBST
4
P
VBST is the supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor
from this pin to the SW node. Internally connected to VREG via bootstrap PMOS switch.
VDD
19
P
Power-supply input pin for controller. Input of the VREG LDO. The input range is from 4.5 to 25 V.
P
VIN is the conversion power-supply input pins.
15
VIN
16
17
VREG
20
O
VREG is the 5-V LDO output. This voltage supplies the internal circuitry and gate driver.
VO
24
I
VOUT voltage input to the controller.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
EN
MAX
–0.3
7.7
DC
–3
25
Transient < 10 ns
–5
27
VBST
–0.3
31
VBST (3)
–0.3
SW
Input voltage range (2)
MIN
6
VBST when transient < 10 ns
UNIT
V
33
VDD
–0.3
28
VIN
–0.3
25
ADDR, SDA, SCL, FB, MODE, VO
–0.3
6
PGOOD
–0.3
7.7
ALERT TRIP, VREG
–0.3
6
Junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Output voltage range
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
Voltage values are with respect to the SW terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±2500
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage range
Output voltage range
EN
–0.1
7
SW
–3
20
VBST
–0.1
25.5
VBST (1)
–0.1
5.5
VDD
4.5
25
VIN
1.5
20
ADDR, SDA, SCL, FB, MODE, VO
–0.1
5.5
PGOOD
–0.1
7
ALERT TRIP, VREG
–0.1
5.5
–40
125
Ambient temperature, TA
(1)
MAX
UNIT
V
V
°C
Voltage values are with respect to the SW pin.
6.4 Electrical Characteristics
over operating free-air temperature range, VDD = 12V, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1350
1850
µA
850
1150
µA
0.5
µA
603
mV
SUPPLY CURRENT
IVDD
VDD bias current
TA = 25°C, No load
Power conversion enabled (no
switching)
IVDDSTBY
VDD standby current
TA = 25°C, No load
Power conversion disabled
IVIN(leak)
VIN leakage current
TA = 25°C, VEN = 0 V
Reference voltage
FB w/r/t GND, TA = 25°C
597
FB w/r/t GND, -40°C ≤ TJ ≤ 85°C
–0.5
0.5
FB w/r/t GND, –40°C ≤ TJ ≤ 125°C
–1.0
1.0
VREF OUTPUT
VVREF
VVREFTOL
Reference voltage tolerance
600
%
OUTPUT VOLTAGE
IFB
FB input current
VFB = 600 mV
IVODIS
VO discharge current
VVO = 0.5 V, Power Conversion
Disabled
50
100
6
nA
uA
INTERNAL DAC REFERENCE
VDACTOL1
DAC voltage tolerance 1
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
certain VOUT_ADJUSTMENT
settings only (1)
–6.0
6.0
mV
VDACTOL2
DAC voltage tolerance 2
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
certain VOUT_MARGIN settings
only (2)
–6.0
6.0
mV
VDACTOL3
DAC voltage tolerance 3
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
VOUT_ADJUSTMENT=0Dh and
VOUT_MARGIN=70h for 5%
–6.0
6.0
mV
VDACTOL4
DAC voltage tolerance 4
FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with
VOUT_ADJUSTMENT=13h and
VOUT_MARGIN=07h for -5%
–6.0
6.0
mV
(1)
(2)
Tested at these VOUT_ADJUSTMENT settings: –9.0%, –8.25%, –5.25%, –2.25%, 0.0%, 3.00%, 6.00%, 9.0%
Tested at these VOUT_MARGIN settings: –11.62%, –10.74%, –7.06%, –3.15%, 0%, 3.7%, 7.74%, 12.05%
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Electrical Characteristics (continued)
over operating free-air temperature range, VDD = 12V, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SMPS FREQUENCY
fSW
VO switching frequency
VIN = 12 V, VVO = 3.3 V, FS =
000
250
VIN = 12 V, VVO = 3.3 V, FS =
001
300
VIN = 12 V, VVO = 3.3 V, FS =
010
400
VIN = 12 V, VVO = 3.3 V, FS =
011
500
VIN = 12 V, VVO = 3.3 V, FS =
100
600
VIN = 12 V, VVO = 3.3 V, FS =
101
750
VIN = 12 V, VVO = 3.3 V, FS =
110
850
VIN = 12 V, VVO = 3.3 V, FS =
111
1000
tON(min)
Minimum on-time
TA = 25°C (3)
tOFF(min)
Minimum off-time
TA = 25°C
kHz
60
175
ns
240
310
ns
INTERNAL BOOTSTRAP SW
VF
Forward Voltage
VVREG–VBST, TA = 25°C, IF = 10 mA
0.15
0.25
V
IVBST
VBST leakage current
TA = 25°C, VVBST = 33 V, VSW = 28
V
0.01
1.5
µA
1.4
1.5
V
1.2
1.3
V
1
µA
LOGIC THRESHOLD
VENH
EN enable threshold voltage
1.3
VENL
EN disable threshold voltage
1.1
VENHYST
EN hysteresis voltage
VENLEAK
EN input leakage current
0.22
–1
0
V
SOFT-START
tSS
Soft-start time
SST = 00
1
SST = 01
2
SST = 10
4
SST = 11
8
ms
POWERGOOD COMPARATOR
PGOOD in from higher
VPGTH
(3)
6
PGOOD threshold
104
108
111
%
PGOOD in from lower
89
92
96
%
PGOOD out to higher
113
116
120
%
PGOOD out to lower
80
84
87
%
Specified by design. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VDD = 12V, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
tPGDLY
TEST CONDITIONS
PGOOD delay time
MIN
TYP
MAX
UNIT
Delay for PGOOD going in
PGD=000
165
256
320
μs
Delay for PGOOD going in
PGD=001
409
512
614
μs
Delay for PGOOD going in
PGD=010
0.819
1.024
1.228
ms
Delay for PGOOD going in
PGD=011
1.638
2.048
2.458
ms
Delay for PGOOD going in
PGD=100
3.276
4.096
4.915
ms
Delay for PGOOD going in
PGD=101
6.553
8.192
9.83
ms
Delay for PGOOD going in
PGD=110
13.104
16.38
19.656
ms
Delay for PGOOD going in
PGD=111
105
131
157
ms
Delay tolerance for PGOOD coming
out
2
IPG
PGOOD sink current
VPGOOD = 0.5 V
4
6
IPGLK
PGOOD leakage current
VPGOOD = 5.0 V
–1
0
µs
mA
1
µA
POWER-ON DELAY
tPODLY
Power-on delay time
Delay from enable to switching
POD=000
356
µs
Delay from enable to switching
POD=001
612
µs
Delay from enable to switching
POD=010
1.124
ms
Delay from enable to switching
POD=011
2.148
ms
Delay from enable to switching
POD=100
4.196
ms
Delay from enable to switching
POD=101
8.292
ms
Delay from enable to switching
POD=110
16.48
ms
Delay from enable to switching
POD=111
32.86
ms
CURRENT DETECTION
IOCL
Current limit threshold, valley
IOCLN
Negative current limit threshold,
valley
VZC
Zero cross detection offset
RTRIP = 49 kΩ
11.5
15.0
17.5
RTRIP = 28 kΩ
6.5
8
11
RTRIP = 49 kΩ
-18.0
–14.9
-10.5
RTRIP = 28 kΩ
-11.5
-8.0
-6.0
0
A
A
mV
PROTECTIONS
Wake-up
3.25
3.34
3.41
Shutdown
3.00
3.12
3.19
Wake-up (default)
4.15
4.25
4.35
Shutdown
3.95
4.05
4.15
Overvoltage-protection (OVP)
threshold voltage
OVP detect voltage
116
120
124
OVP propagation delay
With 100-mV overdrive
VVREGUVLO
VREG undervoltage-lockout (UVLO)
threshold voltage
VVDDUVLO
VDD UVLO threshold voltage
VOVP
tOVPDLY
300
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V
V
%
ns
7
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Electrical Characteristics (continued)
over operating free-air temperature range, VDD = 12V, VREG = 5 V, VEN = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VUVP
Undervoltage-protection (UVP)
threshold voltage
UVP detect voltage
tUVPDLY
UVP delay
UVP filter delay
MIN
TYP
MAX
64
68
71
1
UNIT
%
ms
THERMAL SHUTDOWN
Shutdown temperature
Thermal shutdown threshold (3)
TSDN
140
Hysteresis
°C
40
LDO VOLTAGE
VREG
LDO output voltage
VIN = 12 V, ILOAD = 10 mA
VDOVREG
LDO low droop drop-out voltage
VIN = 4.5 V, ILOAD = 30 mA, TA =
25°C
ILDOMAX
LDO over-current limit
VIN = 12 V, TA = 25°C
4.65
170
5
5.45
V
365
mV
200
mA
INTERNAL MOSFETS
RDS(on)H
High-side MOSFET on-resistance
TA = 25°C
9.9
11.4
mΩ
RDS(on)L
Low-side MOSFET on-resistance
TA = 25°C
4.3
4.94
mΩ
0.8
V
PMBus SCL and SDA INPUT BUFFER LOGIC THRESHOLDS
VIL-PMBUS
SCL and SDA low-level input
voltage (3)
VIH-PMBUS
SCL and SDA high-level input
voltage (3)
VHY-PMBUS
SCL and SDA hysteresis voltage
0°C ≤ TJ ≤ 85°C
0°C ≤ TJ ≤ 85°C
(3)
0°C ≤ TJ ≤ 85°C
2.1
V
240
mV
PMBus SDA and ALERT OUTPUT PULLDOWN
VOL1-PMBUS
SDA and ALERT low-level output
voltage (3)
VDDPMBus = 5.5 V, RPULLUP = 1.1 kΩ,
0°C ≤ TJ ≤ 85°C
0.4
V
VOL2-PMBUS
SDA and ALERT low-level output
voltage (3)
VDDPMBus = 3.6 V, RPULLUP = 0.7 kΩ,
0°C ≤ TJ ≤ 85°C
0.4
V
6.5 Thermal Information
TPS549A20
THERMAL METRIC (1)
RVE
(VQFN-CLIP)
UNIT
28 PINS
θJA
Junction-to-ambient thermal resistance
37.5
°C/W
θJCtop
Junction-to-case (top) thermal resistance
34.1
°C/W
θJB
Junction-to-board thermal resistance
18.1
°C/W
ψJT
Junction-to-top characterization parameter
1.8
°C/W
ψJB
Junction-to-board characterization parameter
18.1
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
2.2
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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6.6 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
TA = 25°C (unless otherwise noted)
70
VOUT (V)
0.6
1.2
1.5
1.8
2.5
3.3
5
60
50
40
70
VOUT (V)
0.6
1.2
1.5
1.8
2.5
3.3
5
60
50
40
30
30
0
2
4
6
8
10
Output Current (A)
fSW = 500 kHz
VIN = 12 V
12
14
16
0
90
90
80
80
70
VOUT (V)
0.6
1.2
1.5
1.8
2.5
3.3
5
40
12
14
16
D001
FCCM
70
VOUT (V)
0.6
1.2
1.5
1.8
2.5
3.3
5
60
50
40
30
30
0
2
4
6
8
10
Output Current (A)
fSW = 970 kHz
VIN = 12 V
12
14
16
0
2
4
D001
6
8
10
Output Current (A)
12
Figure 3. Efficiency vs. Output Current
14
16
D001
fSW = 970 kHz
VIN = 12 V
Auto-skip Mode
FCCM
Figure 4. Efficiency vs. Output Current
1.3
1.3
VIN = 5
VIN = 12
VIN = 18
1.275
VIN = 5
VIN = 12
VIN = 18
1.275
1.25
Output Voltage (V)
1.25
Output Voltage (V)
6
8
10
Output Current (A)
Figure 2. Efficiency vs. Output Current
100
Efficiency (%)
Efficiency (%)
Figure 1. Efficiency vs. Output Current
50
4
fSW = 500 kHz
VIN = 12 V
Auto-skip Mode
100
60
2
D001
1.225
1.2
1.175
1.225
1.2
1.175
1.15
1.15
1.125
1.125
1.1
1.1
0
3
6
9
Output Current (A)
fSW = 500 kHz
12
15
0
3
D001
VOUT = 1.2 V
fSW = 970 kHz
Figure 5. DC Load Regulation
6
9
Output Current (A)
12
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D001
VOUT = 1.2 V
Figure 6. DC Load Regulation
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
1.3
1.3
VIN = 5
VIN = 12
VIN = 18
1.275
1.25
Output Voltage (V)
1.25
Output Voltage (V)
VIN = 5
VIN = 12
VIN = 18
1.275
1.225
1.2
1.175
1.225
1.2
1.175
1.15
1.15
1.125
1.125
1.1
1.1
0
3
6
9
Output Current (A)
fSW = 500 kHz
12
15
0
3
VOUT = 1.2 V
fSW = 970 kHz
12
15
D001
VOUT = 1.2 V
Figure 8. DC Load Regulation
110
100
100
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure 7. DC Load Regulation
110
90
80
70
400 LFM
200 LFM
100 LFM
Natural convection
60
6
9
Output Current (A)
D001
90
80
70
400 LFM
200 LFM
100 LFM
Natural convection
60
50
50
0
3
6
9
Output Current (A)
12
15
0
3
6
9
Output Current (A)
D001
fSW = 500 kHz
VOUT = 5 V
VIN = 12 V
12
fSW = 500 kHz
VOUT = 1 V
Figure 9. Safe Operating Area
15
D001
VIN = 12 V
Figure 10. Safe Operating Area
1000
Switching Frequency (kHz)
900
250 kHz, Skip Mode
500 kHz, Skip Mode
970 kHz, Skip Mode
250 kHz, FCCM
500 kHz, FCCM
970 kHz, FCCM
800
700
600
500
400
300
200
0
3
6
9
Output Current (A)
VIN = 12 V
12
15
D001
VOUT = 1.2 V
Figure 11. Switching Frequency vs. Output Current
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
ILOAD = 0 A
Figure 12. Skip Mode Steady-State Operation
fSW = 1 MHz
VOUT = 1.2 V
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
ILOAD = 0 A
Figure 13. FCCM Steady-State Operation
VIN = 12 V
ILOAD = 0.1 A
Figure 14. Skip Mode Steady-State Operation
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
ILOAD = 0.1 A
Figure 15. Steady-State Operation
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
ILOAD = 8 A
Figure 16. Skip Mode Steady-State Operation
ILOAD from 0 A to 8 A
VIN = 12 V
fSW = 1 MHz
Div = 2 A/µs
VOUT = 1.2 V
fSW = 1 MHz
VOUT = 1.2 V
Figure 17. Skip Mode Steady-State Operation
ILOAD from 0 A to 8 A
VIN = 12 V
fSW = 1 MHz
Figure 18. Auto-skip Mode Load Transient
12
VIN = 12 V
ILOAD = 8 A
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Div = 2 A/µs
VOUT = 1.2 V
Figure 19. Load Transient
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
Figure 20. Auto-skip Mode Start-Up
ILOAD = 0 A
VOUT = 1.2 V
VIN = 12 V
fSW = 1 MHz
Figure 22. Skip Mode Pre-Bias Start-Up
fSW = 1 MHz
VOUT = 1.2 V
VIN = 12 V
Figure 21. FCCM Mode Start-Up
ILOAD = 0 A
VOUT = 1.2 V
VIN = 12 V
fSW = 1 MHz
Figure 23. FCCM Pre-Bias Start-Up
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
ILOAD = 8A
VOUT = 1.2 V
VIN = 12 V
fSW = 1 MHz
Figure 24. Auto-skip Mode Shutdown Operation
ILOAD = 0 A
VOUT = 1.2 V
ILOAD = 8 A
VOUT = 1.2 V
Figure 25. Auto-skip Mode Shutdown Operation
VIN = 12 V
fSW = 1 MHz
Figure 26. FCCM Shutdown Operation
14
VIN = 12 V
fSW = 1 MHz
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ILOAD = 8 A
VOUT = 1.2 V
VIN = 12 V
fSW = 1 MHz
Figure 27. FCCM Shutdown Operation
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Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
Figure 28. Overcurrent Protection Hiccup
Figure 29. Overcurrent Protection
6.7 Thermal Performance
fSW = 500 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 12 A, COUT = 10 × 22 µF (1206, 6.3 V, X5R), RBOOT = 0 Ω, SNB = 3 Ω + 470 pF
Inductor: LOUT = 1 µH, PCMC135T-1R0MF, 12.6 mm × 13.8 mm × 5 mm, 2.1 mΩ (typ)
Figure 30. SP1: 68.2℃
℃ ( TPS549A20 ), SP2: 75℃
℃ (Inductor)
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7 Detailed Description
7.1 Overview
The TPS549A20 is a high-efficiency, single-channel, synchronous-buck converter. The device suits low-output
voltage point-of-load applications with 15-A or lower output current in computing and similar digital consumer
applications. The TPS549A20 features proprietary D-CAP3 mode control combined with adaptive on-time
architecture. This combination builds modern low-duty-ratio and ultra-fast load-step-response DC-DC converters
in an ideal fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from
1.5 V to 20 V (with snubber) and the VDD input voltage ranges from 4.5 V to 25 V. D-CAP3 mode operation uses
emulated current information to control the modulation. An advantage of this control scheme is that it does not
require a phase-compensation network outside which makes the device easy-to-use and also allows low-external
component count. Adaptive on-time control tracks the preset switching frequency over a wide range of input and
output voltage while increasing switching frequency as needed during load-step transient.
7.2 Functional Block Diagrams
+
UV
PGOOD
+
0.6 V + 8/16%
0.6 V ± 32%
Delay
Delay
+
+
OV
0.6 V ± 8/16%
0.6 V+20%
VREG
Internal
Ramp
Control Logic
0.6 V
SS
UVP / OVP
Logic
+
+ PWM
VFB
VBST
VIN
10 µA
GND
TRIP
LL
+
+
OneShot
OCP
SW
XCON
+
ZC
PGND
Control
Logic
PGND
SW
FCCM / SKIP
RC Time Constant
ALERT
SDA
PMBus
Communication
Block
x
x
x
x
x
x
On/Off time
Minimum On/Off
Light load
OVP/UVP
FCCM/SKIP
Soft-Start
VO
Fault
Shut Down
+
MODE
VREGOK
3.34 V /
3.12 V
SCL
LDO
+
VDDOK
+
1.4 V / 1.2 V
Enable
+
EN
THOK
140°C /
100°C
VREG
VDD
4.3 V /
4.03 V
RF
TPS549A20
16
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7.3 Feature Description
7.3.1 Powergood
The TPS549A20 has powergood output that indicates high when switcher output is within the target. The powergood function is activated after the soft-start operation is complete. If the output voltage becomes within ±8% of
the target value, internal comparators detect the power-good state and the power-good signal becomes high
after a 1-ms internal delay. If the output voltage goes outside of ±16% of the target value, the power-good signal
becomes low after a 2-μs internal delay. The power-good output is an open-drain output and must be pulled-up
externally.
7.3.2 D-CAP3 Control and Mode Selection
RR
SW
To comparator
CR
VOUT
Figure 31. Internal RAMP Generation Circuit
The TPS549A20 uses D-CAP3 mode control to achieve fast load transient while maintaining the ease-of-use
feature. An internal RAMP is generated and fed to the VFB pin to reduce jitter and maintain stability. The
amplitude of the ramp is determined by the R-C time-constant as shown in Figure 31. At different switching
frequencies, (fSW) the R-C time-constant varies to maintain relatively constant RAMP amplitude.
The default switching frequency (fSW) is pre-set at 400 kHz. The switching frequency can be changed via PMBus
function (see Table 13).
7.3.3 D-CAP3 Mode
From small-signal loop analysis, a buck converter using the D-CAP3 mode control architecture can be simplified
as shown in Figure 32.
VO
CC1
CC2
RC2
SW
RC1
VIN
Sample
and Hold
DRVH
PWM
Comparator
RFBH
G
FB
VRAMP
+
+
+
VREF
Lx
Control
Logic
and
Driver
RFBL
VOUT
DRVL
RCO
COUT
RLOAD
Figure 32. D-CAP3 Mode
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Feature Description (continued)
The D-CAP3 control architecture includes an internal ripple generation network enabling the use of very low-ESR
output capacitors such as multi-layered ceramic capacitors (MLCC). No external current sensing network or
voltage compensators are required with D-CAP3 control architecture. The role of the internal ripple generation
network is to emulate the ripple component of the inductor current information and then combine it with the
voltage feedback signal to regulate the loop operation. For any control topologies supporting no external
compensation design, there is a minimum and/or maximum range of the output filter it can support. The output
filter used with the TPS549A20 device is a lowpass L-C circuit. This L-C filter has double pole that is described in
Equation 1.
1
fP =
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency L-C double pole has a 180 degree in phase. At the output filter frequency,
the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple generation network
introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per decade and increases
the phase to 90 degree one decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 1 is
located close enough to the high-frequency zero so that the phase boost provided by the high-frequency zero
provides adequate phase margin for the stability requirement.
Table 1. Locating the Zero
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
250 and 300
6
400 and 500
7
600 and 750
9
850 and 1000
12
After identifying the application requirements, the output inductance should be designed so that the inductor
peak-to-peak ripple current is approximately between 25% and 35% of the ICC(max) (peak current in the
application). Use Table 1 to help locate the internal zero based on the selected switching frequency. In general,
where reasonable (or smaller) output capacitance is desired, Equation 2 can be used to determine the necessary
output capacitance for stable operation.
1
= fZ
fP =
2 ´ p ´ LOUT ´ COUT
(2)
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10-µF, X5R and 6.3 V, the deratings by DC bias and
AC bias are 80% and 50% respectively. The effective derating is the product of these two factors, which in this
case is 40% and 4-µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be
used in the system/applications.
Table 2 shows the recommended output filter range for an application design with the following specifications:
• Input voltage, VIN = 12 V
• Switching frequency, fSW = 600 kHz
• Output current, IOUT = 8 A
The minimum output capacitance is verified by the small signal measurement conducted on the EVM using the
following two criteria:
• Loop crossover frequency is less than one-half the switching frequency (300 kHz)
• Phase margin at the loop crossover is greater than 50 degrees
For the maximum output capacitance recommendation, simplify the procedure to adopt an unrealistically high
output capacitance for this type of converter design, then verify the small signal response on the EVM using the
following one criteria:
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Phase margin at the loop crossover is greater than 50 degrees
As indicated by the phase margin, the actual maximum output capacitance (COUT(max)) can continue to go higher.
However, small signal measurement (bode plot) should be done to confirm the design.
Select a MODE pin configuration as shown in Table 3 to double the R-C time constant option for the maximum
output capacitance design and application. Select a MODE pin configuration to use single R-C time constant
option for the normal (or smaller) output capacitance design and application.
The MODE pin also selects Auto-skip-mode or FCCM-mode operation.
Table 2. Recommended Component Values
COUT(min)
(µF)
CROSSOVER
(kHz)
0.36
PIMB065T-R36MS
3 × 100
247
70
48
62
10
0.68
PIMB065T-R68MS
9 × 22
207
53
25
84
31.6
1.2
PIMB065T-1R2MS
4 × 22
185
57
11
63
3.3
45.3
1.5
PIMB065T-1R5MS
3 × 22
185
57
9
59
5.5
82.5
2.2
PIMB065T-2R2MS
2 × 22
185
51
7
58
VOUT
(V)
RUPPER
(kΩ)
LOUT
(µH)
0.6
0
1.2
2.5
(1)
RLOWER
(kΩ)
10
(1)
PHASE COUT(max) INTERNAL
MARGIN
(µF)
RC SETTING
(1)
(°)
(µs)
40
30 x 100
40
33%
80
40
30 x 100
34%
80
40
30 x 100
8
33%
80
40
30 x 100
ICC(max)
(A)
33%
80
30 x 100
INDUCTOR
ΔI/ICC(max)
28%
80
All COUT(min) and COUT(max) capacitor specifications are 1206, X5R, 10 V.
For higher output voltage at or above 2.0 V, additional phase boost might be required in order to secure sufficient
phase margin due to phase delay/loss for higher output voltage (large on-time (tON)) setting in a fixed on time
topology based operation.
A feedforward capacitor placing in parallel with RUPPER is found to be very effective to boost the phase margin at
loop crossover.
Table 3. Mode Selection and Internal RAMP RC Time Constant
MODE
SELECTION
RMODE
(kΩ)
ACTION
R-C TIME
CONSTANT (µs)
60
275
and
325
50
425
and
525
40
625
and
750
30
850
and
1000
120
275
and
325
100
425
and
525
80
625
and
750
60
850
and
1000
60
275
and
325
50
425
and
525
40
625
and
750
30
850
and
1000
120
275
and
325
100
425
and
525
80
625
and
750
60
850
and
1000
0
Auto-skip Mode
Pull down to GND
150
20
FCCM (1)
Connect to
PGOOD
150
(1)
SWITCHING
FREQUENCIES
fSW (kHz)
Device goes into Forced CCM (FCCM) after PGOOD becomes high.
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Table 3. Mode Selection and Internal RAMP RC Time Constant (continued)
MODE
SELECTION
FCCM
RMODE
(kΩ)
ACTION
Connect to VREG
R-C TIME
CONSTANT (µs)
0
SWITCHING
FREQUENCIES
fSW (kHz)
120
275
and
325
100
425
and
525
80
625
and
750
60
850
and
1000
7.3.4 Sample and Hold Circuitry
Sampled_CSP
CSP
C1
Buffer 1
C2
Buffer 2
Figure 33. Sample and Hold Circuitry
The sample and hold circuitry is the difference between D-CAP3 and D-CAP2. The sample and hold circuitry,
which is an advance control scheme to boost output voltage accuracy higher on the TPS549A20 , is one of
features of the TPS549A20 . The sample and hold circuitry generates a new DC voltage of CSN instead of the
voltage which is produced by RC2 and CC2 which allows for tight output-voltage accuracy and makes the
TPS549A20 more competitive.
CSP
CSN
CSN_NEW
(sample at valley of CSP)
Figure 34. Continuous Conduction Mode (CCM) With
Sample and Hold Circuitry
CSP
CSN
CSN_NEW
(sample at valley of CSP)
Figure 35. Discontinuous Conduction Mode (DCM) With
Sample and Hold Circuitry
CSP
CSN
Figure 36. Continuous Conduction Mode (CCM) Without
Sample and Hold Circuitry
20
CSP
CSN
Figure 37. Discontinuous Conduction Mode (DCM) Without
Sample and Hold Circuitry
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1.25
1.25
1.23
1.23
1.21
1.21
VOUT (V)
VOUT (V)
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VIN = 12 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 H
Mode = FCCM
1.19
1.17
1.15
1
2
3
1.19
1.17
D-CAP3
D-CAP2
1.15
4
5
6
7
8
9
10
11
Output Current (A)
12
VIN = 12 V
VDD = 5 V
VOUT = 1.2 V
fSW = 500 kHz
TA = 25°C
LOUT = 1 H
Mode = Auto-skip
1
2
4
D-CAP2
5
6
7
8
9
10
11
Output Current (A)
C013
Figure 38. Output Voltage vs Output Current
3
D-CAP3
12
C014
Figure 39. Output Voltage vs Output Current
7.3.5 Adaptive Zero-Crossing
The TPS549A20 uses an adaptive zero-crossing circuit to perform optimization of the zero inductor-current
detection during Auto-skip-mode operation. This function allows ideal low-side MOSFET turn-off timing. The
function also compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection
circuit. Adaptive zero-crossing prevents SW-node swing-up caused by too-late detection and minimizes diode
conduction period caused by too-early detection. As a result, the device delivers better light-load efficiency.
7.3.6 Forced Continuous-Conduction Mode
When the MODE pin is tied to the PGOOD pin through a resistor, the controller operates in continuous
conduction mode (CCM) during light-load conditions. During CCM, the switching frequency maintained to an
most constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency at the cost of lower efficiency.
7.3.7 Current Sense and Overcurrent Protection
The TPS549A20 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent trip level. In order to provide good accuracy and a cost-effective solution, the TPS549A20 supports
temperature compensated MOSFET RDS(on) sensing. Connect the TRIP pin to GND through the trip-voltage
setting resistor, RTRIP(20kΩ
