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TPS549B22
SNVSAU8 – JUNE 2017
TPS549B22 1.5-V to 18-V VIN, 4.5-V to 22-V VDD, 25-A SWIFT™
Synchronous Step-Down Converter With Full Differential Sense and PMBus™
1 Features
2 Applications
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Input Voltage (PVIN): 1.5 V to 18 V
Input Bias Voltage (VDD) Range: 4.5 V to 22 V
Output Voltage Range: 0.6 V to 5.5 V
Integrated, 4.1-mΩ and 1.9-mΩ Power MOSFETs
With 25-A Continuous Output Current
Voltage Reference 0.6 V to 1.2 V in 50-mV Steps
Using VSEL Pin
±0.5%, 0.9-VREF Tolerance Range: –40°C to
+125°C Junction Temperature
True Differential Remote Sense Amplifier
D-CAP3™ Control Loop
Adaptive On-Time Control with 8 PMBusTM
Frequencies: 315 kHz, 425 kHz, 550 kHz, 650
kHz, 825 kHz, 900 kHz, 1.025 MHz, 1.125 MHz
Temperature Compensated and Programmable
Current Limit with RILIM and OC Clamp
Choice of Hiccup or Latch-Off OVP or UVP
VDD UVLO External Adjustment by Precision EN
Prebias Start-up Support
Eco-mode™ and FCCM Selectable
Full Suite of Fault Protection and PGOOD
Standard VOUT_COMMAND and
VOUT_MARGIN (HIGH and LOW)
Pin-Strapping and On-the-Fly Programming
Fault Reporting and Warning
NVM Backup for Selected Commands
1-MHz PMBus with PEC and SMB_ALRT#
Create a Custom Design Using the TPS549B22
With the WEBENCH® Power Designer
Enterprise Storage, SSD, NAS
Wireless and Wired Communication Infrastructure
Industrial PCs, Automation, ATE, PLC, Video
Surveillance
Enterprise Server, Switches, Routers
ASIC, SoC, FPGA, DSP Core and I/O Rails
•
•
3 Description
The TPS549B22 device is a compact single buck
converter with adaptive on-time, D-CAP3 mode
control. It is designed for high accuracy, high
efficiency, fast transient response, ease-of-use, low
external component count and space-conscious
power systems.
This device features full differential sense and TI
integrated FETs with a high-side on-resistance of
4.1 mΩ and a low-side on-resistance of 1.9 mΩ. The
device also features an accurate 0.5%, 0.9-V
reference with an ambient temperature range
between –40°C and +125°C. Competitive features
include: very low external component count, accurate
load regulation and line regulation, auto-skip or
FCCM mode operation, and internal soft-start control.
The TPS549B22 device is available in 7 mm × 5 mm,
40-pin, LQFN-CLIP (RVF) package (RoHs exempt).
Device Information(1)
PART NUMBER
TPS549B22
PACKAGE
BODY SIZE (NOM)
LQFN-CLIP (40)
7.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
MODE
PGOOD
PVIN
PVIN
PVIN
PVIN
PVIN
NC
VDD
DRGND
BP
AGND
VSEL
ADDR
PVIN
PGND
ILIM
PGND
TPS549B22
PGND
Load
+
±
SW
SW
SW
SW
PGND
SW
BOOT
EN_UVLO
PMB_CLK
VOSNS
PGND
PMB_DATA
RSP
SMB_ALRT#
RESV_TRK
RSN
PGND
PGND
PGOOD
PGND
ALERT#
DATA
CLOCK
ENABLE
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS549B22
SNVSAU8 – JUNE 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
7
7.6 Register Maps ......................................................... 29
1
1
1
2
3
4
8
8.1 Application Information............................................ 43
8.2 Typical Applications ................................................ 44
9 Power Supply Recommendations...................... 54
10 Layout................................................................... 54
10.1 Layout Guidelines ................................................. 54
10.2 Layout Examples................................................... 55
10.3 Mounting and Thermal Profile Recommendation.. 57
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Typical Characteristics ............................................ 10
11 Device and Documentation Support ................. 58
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 14
7.1
7.2
7.3
7.4
7.5
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Application and Implementation ........................ 43
14
15
15
19
19
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
58
59
12 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
June 2017
*
Initial release
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5 Pin Configuration and Functions
ADDR
BP
AGND
DRGND
VDD
NC
NC
PVIN
PVIN
PVIN
PVIN
PVIN
RVF Package
40-Pin LQFN-CLIP With Thermal Pad
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20 PGND
VSEL 33
19 PGND
MODE 34
18 PGND
PGOOD 35
17 PGND
ILIM 36
16 PGND
RESV_TRK 37
15 PGND
RSN 38
Thermal Pad
RSP 39
14 PGND
13 PGND
6
7
8
EN_UVLO
BOOT
NC
NC
SW
9
10
11
12
SW
5
SW
4
SW
3
SW
2
PMB_CLK
SMB_ALRT#
1
PMB_DATA
VOSNS 40
Pin Functions
PIN
NAME
NO.
I/O/P (1)
DESCRIPTION
ADDR
32
I
Program device address and SKIP or FCCM mode.
AGND
30
G
Ground pin for internal analog circuits.
BOOT
5
P
Supply rail for high-side gate driver (boot terminal). Connect boot capacitor from this pin to SW
node. Internally connected to BP via bootstrap PMOS switch.
BP
31
O
LDO output
DRGND
29
P
Internal gate driver return.
EN_UVLO
4
I
Enable pin that can turn on the DC/DC switching converter. Use also to program the required
PVIN UVLO when PVIN and VDD are connected together.
ILIM
36
I/O
34
I
MODE
6, 7, 26,
27
NC
Program overcurrent limit by connecting a resistor to ground.
Mode selection pin. Select the control mode (DCAP3 or DCAP), and soft-start timing selection.
No connect.
13, 14, 15,
16, 17, 18,
19, 20
P
Power ground of internal FETs.
PGOOD
35
O
Open drain power-good status signal.
PMB_CLK
3
I
Clock input for the PMBus interface.
PMB_DATA
2
I/O
PVIN
21, 22, 23,
24, 25
P
Power supply input for integrated power MOSFET pair.
RSN
38
I
Inverting input of the differential remote sense amplifier.
RSP
39
I
Non-inverting input of the differential remote sense amplifier.
RESV_TRK
37
I
Do not connect.
SMB_ALRT#
1
O
Alert output for the PMBus interface.
PGND
(1)
Data I/O for the PMBus interface.
I = input, O = output, G = GND
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SNVSAU8 – JUNE 2017
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Pin Functions (continued)
PIN
NAME
NO.
I/O/P (1)
DESCRIPTION
SW
8, 9, 10,
11, 12
I/O
VDD
28
P
Controller power supply input.
VOSNS
40
I
Output voltage monitor input pin.
VSEL
33
I
Program the initial start-up and or reference voltage without feedback resistor dividers (from
0.6 V to 1.2 V in 50-mV increments).
Output switching terminal of power converter. Connect the pins to the output inductor.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
PVIN
–0.3
25
VDD
–0.3
25
BOOT
BOOT to SW
Input voltage
–0.3
34
DC
–0.3
7.7
< 10 ns
–0.3
9
PMB_CLK, PMB_DATA
–0.3
6
EN_UVLO, VOSNS, MODE, ADDR, ILIM
–0.3
7.7
RSP, RESV_TRK, VSEL
–0.3
3.6
RSN
–0.3
0.3
–0.3
0.3
–0.3
25
–5
27
PGND, AGND, DRGND
DC
SW
< 10 ns
UNIT
V
Output voltage
PGOOD, BP
–0.3
7.7
Output voltage
SMB_ALRT#, PMB_DATA
–0.3
6
V
Junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SNVSAU8 – JUNE 2017
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
PVIN with no snubber circuit:
SW ringing peak voltage equals 23 V at 25-A output
1.5
14
PVIN with snubber circuit:
SW ringing peak voltage equals 23 V at 25-A output
1.5
18
VDD
4.5
22
–0.1
24.5
DC
–0.1
6.5
< 10 ns
BOOT
BOOT to SW
–0.1
7
PMB_CLK, PMB_DATA
–0.1
5.5
EN_UVLO, VOSNS, MODE, ADDR, ILIM
–0.1
5.5
RSP, RESV_TRK, VSEL
–0.1
3.3
RSN
–0.1
0.1
PGND, AGND, DRGND
–0.1
0.1
–0.1
18
–5
27
Input voltage
DC
SW
< 10 ns
UNIT
V
Output voltage
PGOOD, BP
–0.1
7
V
Output voltage
SMB_ALRT#, PMB_DATA
–0.1
5.5
V
–40
125
°C
Junction temperature, TJ
6.4 Thermal Information
TPS549B22
THERMAL METRIC
(1)
RVF (LQFN-CLIP)
UNIT
40 PINS
RθJA
Junction-to-ambient thermal resistance
28.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
18.3
°C/W
RθJB
Junction-to-board thermal resistance
3.6
°C/W
ψJT
Junction-to-top characterization parameter
0.96
°C/W
ψJB
Junction-to-board characterization parameter
3.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
MOSFET ON-RESISTANCE (RDS(on))
RDS(on)
High-side FET
(VBOOT – VSW) = 5 V, ID = 25 A, TJ = 25°C
4.1
mΩ
Low-side FET
VVDD = 5 V, ID = 25 A, TJ = 25°C
1.9
mΩ
INPUT SUPPLY AND CURRENT
VVDD
VDD supply voltage
Nominal VDD voltage range
IVDD
VDD bias current
No load, power conversion enabled (no switching),
TA = 25°C,
IVDDSTBY
VDD standby current
No load, power conversion disabled, TA = 25°C
4.5
22
2
mA
700
µA
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
4.23
4.25
4.34
V
UNDERVOLTAGE LOCKOUT
VVDD_UVLO
VDD UVLO rising threshold
VVDD_UVLO(HYS)
VDD UVLO hysteresis
VEN_ON_TH
EN_UVLO on threshold
1.45
1.6
1.75
V
VEN_HYS
EN_UVLO hysteresis
270
300
340
mV
IEN_LKG
EN_UVLO input leakage
current
–1
0
1
µA
0.2
VEN_UVLO = 5 V
V
INTERNAL REFERENCE VOLTAGE RANGE
VINTREF
Internal REF voltage
VINTREFTOL
Internal REF voltage
tolerance
VINTREF
Internal REF voltage range
900.4
–40°C ≤ TJ ≤ 125°C
mV
–0.5%
0.5%
0.6
1.2
V
–2.5
2.5
mV
OUTPUT VOLTAGE
VIOS_LPCMP
Loop comparator input offset
voltage (1)
IRSP
RSP input current
VRSP = 600 mV
IVO(dis)
VO discharge current
VVO = 0.5 V, power conversion disabled
–1
1
µA
8
12
mA
5
7
MHz
DIFFERENTIAL REMOTE SENSE AMPLIFIER
fUGBW
Unity gain bandwidth (1)
A0
Open loop gain (1)
SR
Slew rate (1)
VIRNG
Input range (1)
–0.2
1.8
V
VOFFSET
Input offset voltage (1)
–3.5
3.5
mV
75
dB
±4.7
V/µsec
INTERNAL BOOT STRAP SWITCH
VF
Forward voltage
VBP-BOOT, IF = 10 mA, TA = 25°C
IBOOT
VBST leakage current
VBOOT = 30 V, VSW = 25 V, TA = 25°C
0.1
0.2
V
0.01
1.5
µA
275
315
350
380
425
475
490
550
615
585
650
740
740
825
930
SWITCHING FREQUENCY
VO switching frequency (2)
fSW
tON(min)
Minimum on-time (1)
tOFF(min)
Minimum off-time (1)
(1)
(2)
6
VIN = 12 V, VVO = 1 V, TA = 25°C
790
900
995
920
1025
1160
950
1125
1250
60
DRVH falling to rising
kHz
ns
300
ns
Specified by design. Not production tested.
Correlated with close-loop EVM measurement at load current of 30 A.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
MODE, VSEL, ADDR DETECTION
Open
VDETECT_TH
MODE, VSEL, and ADDR
detection voltage
VBP = 2.93 V,
RHIGH = 100 kΩ
VBP
RLOW = 187 kΩ
1.9091
RLOW = 165 kΩ
1.8243
RLOW = 147 kΩ
1.7438
RLOW = 133 kΩ
1.6725
RLOW = 121 kΩ
1.6042
RLOW = 110 kΩ
1.5348
RLOW = 100 kΩ
1.465
RLOW = 90.9 kΩ
1.3952
RLOW = 82.5 kΩ
1.3245
RLOW = 75 kΩ
1.2557
RLOW = 68.1 kΩ
1.187
RLOW = 60.4 kΩ
1.1033
RLOW = 53.6 kΩ
1.0224
RLOW = 47.5 kΩ
0.9436
RLOW = 42.2 kΩ
0.8695
RLOW = 37.4 kΩ
0.7975
RLOW = 33.2 kΩ
0.7303
RLOW = 29.4 kΩ
0.6657
RLOW = 25.5 kΩ
0.5953
RLOW = 22.1 kΩ
0.5303
RLOW = 19.1 kΩ
0.4699
RLOW = 16.5 kΩ
0.415
RLOW = 14.3 kΩ
0.3666
RLOW = 12.1 kΩ
0.3163
RLOW = 10 kΩ
0.2664
RLOW = 7.87 kΩ
0.2138
RLOW = 6.19 kΩ
0.1708
RLOW = 4.64 kΩ
0.1299
RLOW = 3.16 kΩ
0.0898
RLOW = 1.78 kΩ
0.0512
RLOW = 0 Ω
GND
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
RMODE_LOW = 60.4 kΩ
7
8 (3)
10
RMODE_LOW = 53.6 kΩ
3.6
4 (4)
5.2
RMODE_LOW = 47.5 kΩ
1.6
2
2.8
RMODE_LOW = 42.2 kΩ
0.8
1
1.6
UNIT
SOFT-START
tSS
Soft-start time
VOUT rising from 0 V to
95% of final set point,
RMODE_HIGH = 100 kΩ
ms
POWER-ON DELAY
tPODLY
Power-on delay time
Delay from enable to switching POD[2:0] = 000
256
Delay from enable to switching POD[2:0] = 001
512
Delay from enable to switching POD[2:0] = 010
1.024
Delay from enable to switching POD[2:0] = 011
2.048
Delay from enable to switching POD[2:0] = 100
4.096
Delay from enable to switching POD[2:0] = 101
8.192
Delay from enable to switching POD[2:0] = 110
16.384
Delay from enable to switching POD[2:0] = 111
32.768
µs
ms
PGOOD COMPARATOR
VPGTH
PGOOD threshold
IPG
PGOOD sink current
tPGDLY
PGOOD delay time
PGOOD in from higher
105
108
111
PGOOD in from lower
89
92
95
PGOOD out to higher
120
PGOOD out to lower
68
VPGOOD = 0.5 V
6.9
Delay for PGOOD going in, PGD[2:0] = 000
256
Delay for PGOOD going in, PGD[2:0] = 001
512
Delay for PGOOD going in, PGD[2:0] = 010
1.024
Delay for PGOOD going in, PGD[2:0] = 011
2.048
Delay for PGOOD going in, PGD[2:0] = 100
4.096
Delay for PGOOD going in, PGD[2:0] = 101
8.192
Delay for PGOOD going in, PGD[2:0] = 110
16.384
Delay for PGOOD going in, PGD[2:0] = 111
131
Delay for PGOOD coming out
IPGLK
PGOOD leakage current
VPGOOD = 5 V
–1
0
%VREF
mA
µs
ms
2
µs
1
μA
CURRENT DETECTION
RLIM = 61.9 kΩ
30
IOCL_VA
Valley current limit threshold
RLIM = 51.1 kΩ
25
A
±15% (5)
OC tolerance
RLIM = 40.2 kΩ
A
±15% (5)
OC tolerance
17
20
RLIM = 61.9 kΩ
–30
RLIM = 51.1 kΩ
–25
RLIM = 40.2 kΩ
–20
23
A
A
IOCL_VA_N
Negative valley current limit
threshold
ICLMP_LO
Clamp current at VLIM clamp
at lowest
VILIM_CLMP = 0.1 V, TA = 25°C
5
A
ICLMP_HI
Clamp current at VLIM clamp
at highest
VILIM_CLMP = 1.2 V, TA = 25°C
50
A
(3)
(4)
(5)
8
In order to use the 8-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
In order to use the 4-ms SS setting, follow the steps outlined in Application Workaround to Support 4-ms and 8-ms SS Settings.
Calculated from 20-A test data. Not production tested.
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Electrical Characteristics (continued)
over operating free-air temperature range, VVDD = 12 V, VEN_UVLO = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PROTECTIONS AND OOB
Wake-up
3.32
Shutdown
3.11
VBPUVLO
BP UVLO threshold voltage
VOVP
OVP threshold voltage
OVP detect voltage
tOVPDLY
OVP response time
100-mV over drive
VUVP
UVP threshold voltage
UVP detect voltage
tUVPDLY
UVP delay filter delay time
VOOB
OOB threshold voltage
tHICDLY
Hiccup blanking time
117%
120%
V
123%
1
65%
68%
71%
1
VREF
µs
VREF
ms
8%
VREF
tSS = 1 ms
16
ms
tSS = 2 ms
24
ms
tSS = 4 ms
38
ms
tSS = 8 ms
67
ms
BP VOLTAGE
VBP
BP LDO output voltage
VIN = 12 V, 0 A ≤ ILOAD ≤ 10 mA,
VBPDO
BP LDO dropout voltage
VIN = 4.5 V, ILOAD = 30 mA, TA = 25°C
IBPMAX
BP LDO overcurrent limit
VIN = 12 V, TA = 25°C
5.07
V
365
100
mV
mA
PMB_CLK and PMB_DATA INPUT BUFFER LOGIC THRESHOLDS
VIL-PMBUS
PMB_CLK and PMB_DATA
low-level input voltage (1)
VIH-PMBUS
PMB_CLK and PMB_DATA
high-level input voltage (1)
VHY-PMBUS
PMB_CLK and PMB_DATA
hysteresis voltage (1)
0.8
1.35
V
V
150
mV
PMB_CLK and SMB_ALRT OUTPUT PULLDOWN
VOL-PMBUS
PMB_DATA and SMB_ALRT
low-level output voltage (1)
ISINK = 20 mA
0.4
V
THERMAL SHUTDOWN
TSDN
Built-In thermal shutdown
threshold (1)
Shutdown temperature
Hysteresis
155
165
30
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100%
100%
95%
95%
90%
90%
85%
85%
Efficiency
Efficiency
6.6 Typical Characteristics
80%
75%
70%
75%
70%
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
65%
80%
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
65%
60%
60%
0
5
VOUT = 1 V
fSW = 650 kHz
10
15
Output Current (A)
20
25
0
5
D001
VDD = VIN
SKIP Mode
VOUT = 1 V
fSW = 650 kHz
Figure 1. Efficiency vs Output Current
10
15
Output Current (A)
20
25
D002
VDD = VIN
FCCM Mode
Figure 2. Efficiency vs Output Current
1.01
4.5
Output Voltage Regulation (V)
Converter Power Loss (W)
4
3.5
3
2.5
2
1.5
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
1
0.5
0
1.005
1
0.995
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0.99
0
5
10
15
Output Current (A)
VOUT = 1 V
fSW = 650 kHz
20
25
0
5
D003
VDD= VIN
SKIP Mode
VOUT = 1 V
fSW = 650 kHz
Figure 3. Converter Power Loss vs Output Current
10
15
Output Current (A)
20
25
D004
VDD = VIN
FCCM Mode
Figure 4. Output Voltage Regulation vs Output Current
100%
2.525
Converter Power Loss (W)
2.52
Efficiency
95%
90%
85%
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
2.51
2.505
2.5
2.495
2.49
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
2.485
2.48
80%
2.475
0
VDD = VIN
VOUT = 2.5 V
5
10
15
Output Current (A)
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
20
25
0
D005
SKIP Mode
Figure 5. Efficiency vs Output Current
10
2.515
VDD = VIN
VOUT = 2.5 V
5
10
15
Output Current (A)
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
20
25
D006
SKIP Mode
Figure 6. Output Voltage Regulation vs Output Current
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Typical Characteristics (continued)
100%
Converter Power Loss (W)
6
Efficiency
95%
90%
85%
VIN = 9 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
5
4
3
2
VIN = 9 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
1
80%
0
0
5
VDD = VIN
VOUT = 5 V
10
15
Output Current (A)
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
20
25
FCCM Mode
Figure 7. Efficiency vs Output Current
VDD = VIN = 12 V
VOUT = 1 V
0
5
D007
IOUT = 25 A
fSW = 650 kHz
Natural convection at room temperature
VDD = VIN
VOUT = 5 V
fSW = 650 kHz
L= 820 nH, 0.9 mΩ
20
25
D008
FCCM Mode
Figure 8. Power Loss vs Output Current
VDD = VIN = 12 V
VOUT = 1 V
Figure 9. Thermal Image
VDD = VIN = 12 V
VOUT = 2.5 V
10
15
Output Current (A)
IOUT = 25 A
fSW = 650 kHz
Natural convection at room temperature
Figure 10. Thermal Image
IOUT = 25 A
fSW = 650 kHz
Natural convection at room temperature
VDD = VIN = 12 V
VOUT = 5 V
Figure 11. Thermal Image
IOUT = 25 A
fSW = 650 kHz
Natural convection at room temperature
Figure 12. Thermal Image
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Typical Characteristics (continued)
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
Figure 13. PMBus 1-MHz Bus Speed with 1.8-V Pullup
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – VOUT Command up to 1.2 V
5 – VOUT Command down to 0.6 V
6 – Turnoff
Figure 15. 6 Sequenced Events – I2C Write/Read
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – 16 VOUT Command up to 1.2 V,
50 mV per step down to 0.6 V
17 – Turnoff
Figure 17. 17 Sequenced Events – I2C Write
12
4 – VOUT Command up to 1.2 V
5 – VOUT Command down to 0.6 V
6 – Turnoff
Figure 14. 6 Sequenced Events – I2C Write
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – VOUT Command up to 1.2 V
5 – VOUT Command down to 0.6 V
6 – Turnoff
Figure 16. 6 Sequenced Events – I2C Write/Read with PEC
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – 16 VOUT Command up to 1.2 V,
50 mV per step down to 0.6 V
17 – Turnoff
Figure 18. 17 Sequenced Events – I2C Write/Read
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Typical Characteristics (continued)
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – 16 VOUT Command up to 1.2 V,
50 mV per step down to 0.6 V
17 – Turnoff
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
Figure 19. 17 Sequenced Events – I2C Write/Read with PEC
4 – 16 VOUT Command up to 1.2
V,
50 mV per step down to 0.6 V
17 – 28 VOUT Command from 0.6
V
to 1.2 V, 50 mV per step
29 – Turnoff
Figure 20. 29 Sequenced Events – I2C Write
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – 16 VOUT Command up to 1.2 V,
50 mV per step down to 0.6 V
17 – 28 Vout Command from 0.6 V
to 1.2 V, 50 mV per step
29 – Turnoff
Figure 21. 29 Sequenced Events – I2C Write/Read
1 – Operation only
2 – Turnoff
3 – Turnon without Margin
4 – 16 Vout Command up to 1.2 V,
50 mV per step down to 0.6 V
17 – 28 Vout Command from 0.6 V
to 1.2 V, 50 mV per step
29 – Turnoff
Figure 22. 29 Sequenced Events – I2C Write/Read with PEC
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7 Detailed Description
7.1 Overview
TPS549B22 device is a high-efficiency, single-channel, FET-integrated, synchronous buck converter. It is
suitable for point-of-load applications with 25 A or lower output current in storage, telecom and similar digital
applications. The device features proprietary D-CAP3 mode control combined with adaptive on-time architecture.
This combination is ideal for building modern high/low duty ratio, ultra-fast load step response DC-DC converters.
TPS549B22 device has integrated MOSFETs rated at 25-A TDC.
The converter input voltage range is from 1.5 V up to 18 V, and the VDD input voltage range is from 4.5 V to
22 V. The output voltage ranges from 0.6 V to 5.5 V.
Stable operation with all ceramic output capacitors is supported as the D-CAP3 mode uses emulated current
information to control the modulation. An advantage of this control scheme is that it does not require phase
compensation network outside which makes it easy to use and also enables low external component count. .
Adaptive on-time control tracks the preset switching frequency over a wide range of input and output voltage
while increasing switching frequency as needed during load step transient.
The default preset switching frequency for this device is 650 kHz. Switching frequency is also programmable
from 8 preset values via PMBus interface. supports digital communication via PMBus using standard interfacing
pins, PMB_CLK, PMB_DATA and SMB_ALRT#. The detailed PMBus features, capabilities and command sets of
the TPS549B22 can be found in PMBus Programming.
14
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7.2 Functional Block Diagram
External Soft
Start
RESV_TRK
MUX
Internal
Soft Start
EN_UVLO
VREF -32%
+
UV
-
VREF +8/16%
PGOOD
+
Delay
Control
RSN
+
OV
-
+
RSP
+
VREF -8/16%
-
PVIN
VREF +20%
BOOT
+
+
+
vout
VOSNS
D-CAP3TM
Ramp Generator
PWM
VREF
Reference
Generator
VSEL
XCON
PMB_CLK
PMBus
Interface
PMB_DATA
Adjustment/
Margining
SMB_ALRT#
SW
Control Logic
tON
OneShot
Address
Detector
ADDR
BP
+
x(1/16)
ILIM
ZC
PGND
AGND
MODE
x(-1/16)
+
LS
OCP
-
LDO
Regulator
VDD
MODE Logic
DRGND
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7.3 Feature Description
7.3.1 25-A FET
The TPS549B22 device is a high-performance, integrated FET converter supporting current rating up to 25 A
thermally. It integrates two N-channel NexFET™ power MOSFETs, enabling high power density and small PCB
layout area. The drain-to-source breakdown voltage for these FETs is 25-V DC and 27-V transient for 10 ns.
Avalanche breakdown occurs if the absolute maximum voltage rating exceeds 27 V. In order to limit the switch
node ringing of the device, TI recommends adding an R-C snubber from the SW node to the PGND pins. Refer
to Layout Guidelines for the detailed recommendations.
7.3.2 On-Resistance
The typical on-resistance (RDS(on)) for the high-side MOSFET is 4.1 mΩ, and typical on-resistance for the lowside MOSFET is 1.9 mΩ with a nominal gate voltage (VGS) of 5 V.
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Feature Description (continued)
7.3.3 Package Size, Efficiency and Thermal Performance
110
110
100
100
Ambient Temperature (qC)
Ambient Temperature (qC)
The TPS549B22 device is available in a 7 mm × 5 mm QFN package with 40 power and I/O pins. The device
employs TI proprietary MCM packaging technology with thermal pad. With a properly designed system layout,
applications achieve optimized safe operating area (SOA) performance. The curves shown in Figure 23 and
Figure 24 are based on the orderable evaluation module design. (See www.ti.com to order the EVM.)
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
90
80
70
60
50
Nat Conv
100 LFM
200 LFM
400 LFM
40
30
30
0
5
10
15
Output Current (A)
VIN = 12 V
VOUT = 1 V
20
25
0
5
10
15
Output Current (A)
D011
fSW = 650 kHz
VIN = 12 V
Figure 23. Safe Operating Area
VOUT = 5.5 V
20
25
D012
fSW = 650 kHz
Figure 24. Safe Operating Area
7.3.4 Soft-Start Operation
In the TPS549B22 device the soft-start time controls the inrush current required to charge the output capacitor
bank during start-up. The device offers selectable soft-start options of 1 ms, 2 ms, 4 ms and 8 ms. When the
device is enabled (either by EN or VDD UVLO), the reference voltage ramps from 0 V to the final level defined by
VSEL pin-strap configuration, in a given soft-start time. The TPS549B22 device supports several soft-start times
between 1 ms and 8 ms selected by MODE pin configuration. Refer to MODE definition table for details.
7.3.5 VDD Supply Undervoltage Lockout (UVLO) Protection
The TPS549B22 device provides fixed VDD undervoltage lockout threshold and hysteresis. The typical VDD turnon
threshold is 4.25 V, and hysteresis is 0.2 V. The VDD UVLO can be used in conjunction with the EN_UVLO signal
to provide proper power sequence to the converter design. UVLO is a non-latched protection.
7.3.6 EN_UVLO Pin Functionality
The EN_UVLO pin drives an input buffer with accurate threshold and can be used to program the exact required
turnon and turnoff thresholds for switcher enable, VDD UVLO or VIN UVLO (if VIN and VDD are tied together). If
desired, an external resistor divider can be used to set and program the turnon threshold for VDD or VIN UVLO.
Figure 25 shows how to program the input voltage UVLO using the EN_UVLO pin.
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Feature Description (continued)
29
28
26
25
24
23
22
21
DRGND
VDD
NC
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PGND 20
PGND 19
PGND 18
PGND 17
TPS549B22
PGND 16
EN_UVLO
PGND 15
PGND 14
PGND 13
4
PVIN
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Figure 25. Programming the UVLO Voltage
7.3.7 Fault Protections
This section describes positive and negative overcurrent limits, overvoltage protections, out-of-bounds limits,
undervoltage protections, and overtemperature protections.
7.3.7.1 Current Limit (ILIM) Functionality
90
ILIM Pin Resistance (k:)
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
Output Current (A)
30
35
40
D010
Figure 26. Current Limit Resistance vs OCP Valley Overcurrent Limit
The ILIM pin sets the OCP level. Connect the ILIM pin to GND through the voltage setting resistor, RILIM. In order
to provide both good accuracy and a cost-effective solution, the TPS549B22 device supports temperature
compensated internal MOSFET RDS(on) sensing.
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Feature Description (continued)
Also, the TPS549B22 device performs both positive and negative inductor current limiting with the same
magnitudes. The positive current limit normally protects the inductor from saturation that causes damage to the
high-side FET and low-side FET. The negative current limit protects the low-side FET during OVP discharge.
The voltage between GND pin and SW pin during the OFF time monitors the inductor current. The current limit
has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance (RDS(on)).
The GND pin is used as the positive current sensing node.
The TPS549B22 device uses cycle-by-cycle over-current limiting control. The inductor current is monitored
during the OFF-state and the controller maintains the OFF-state during the period that the inductor current is
larger than the overcurrent ILIM level. VILIM sets the valley level of the inductor current.
7.3.7.2 VDD Undervoltage Lockout (UVLO)
The TPS549B22 device has an UVLO protection function for the VDD supply input. The on-threshold voltage is
4.25 V with 200 mV of hysteresis. During a UVLO condition, the device is disabled regardless of the EN_UVLO
pin voltage. The supply voltage (VVDD) must be above the on-threshold to begin the pin strap detection.
7.3.7.3 Overvoltage Protection (OVP) and Undervoltage Protection (UVP)
The device monitors a feedback voltage to detect overvoltage and undervoltage. When the feedback voltage
becomes lower than 68% of the target voltage, the UVP comparator output goes high and an internal UVP delay
counter begins counting. After 1 ms, the device latches OFF both high-side and low-side MOSFETs drivers. The
UVP function enables after soft-start is complete.
When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes
high and the circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching
a negative current limit. Upon reaching the negative current limit, the low-side FET is turned off and the high-side
FET is turned on again for a minimum on-time. The TPS549B22 device operates in this cycle until the output
voltage is pulled down under the UVP threshold voltage for 1 ms. The fault is cleared with a reset of VDD or by
retoggling the EN pin.
Table 1. Overvoltage Protection Details
REFERENCE
VOLTAGE
(VREF)
SOFT-START
RAMP
START-UP
OVP
THRESHOLD
OPERATING
OVP
THRESHOLD
OVP DELAY
100 mV OD
(µs)
OVP RESET
Internal
Internal
1.2 × Internal
VREF
1.2 × Internal
VREF
1
UVP
7.3.7.4 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, so
the device is not latched off after an OOB event. OOB protection operates as an early no-fault overvoltageprotection mechanism. During the OOB operation, the controller operates in forced PWM mode only by turning
on the low-side FET. Turning on the low-side FET beyond the zero inductor current quickly discharges the output
capacitor thus causing the output voltage to fall quickly toward the setpoint. During the operation, the cycle-bycycle negative current limit is also activated to ensure the safe operation of the internal FETs.
7.3.7.5 Overtemperature Protection
TPS549B22 device has overtemperature protection (OTP) by monitoring the die temperature. If the temperature
exceeds the threshold value (default value 165°C), TPS549B22 device is shut off. When the temperature falls
about 25°C below the threshold value, the device turns on again. The OTP is a non-latch protection.
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7.4 Device Functional Modes
7.4.1 DCAP3 Control Topology
The TPS549B22 employs an artificial ramp generator that stabilizes the loop. The ramp amplitude is
automatically adjusted as a function of selected switching frequency (fSW) The ramp amplitude is a function of
duty cycle (VOUT-to-VIN ratio). Consequently, two additional pin-strap bits are provided for fine tuning the internal
ramp amplitude. The device uses an improved DCAP3 control loop architecture that incorporates a steady-state
error integrator. The slow integrator improves the output voltage DC accuracy greatly and presents minimal
impact to small signal transient response. To further enhance the small signal stability of the control loop, the
device uses a modified ramp generator that supports a wider range of output LC stage.
7.4.2 DCAP Control Topology
For advanced users of this device, the internal DCAP3 ramp can be disabled using the MODE[4] pin-strap bit.
This situation requires an external RCC network to ensure control loop stability. Place this RCC network across
the output inductor. Use a range between 10 mV and 15 mV of injected RSP pin ripple. If no feedback resistor
divider network is used, insert a 10-kΩ resistor between the VOUT pin and the RSP pin.
7.5 Programming
7.5.1 Programmable Pin-Strap Settings
ADDR, VSEL and MODE. Description: a 1% or better 100-kΩ resistor is needed from BP to each of the three
pins. The bottom resistor from each pin to ground (see MODE, VSEL, ADDR DETECTION section of the
Electrical Characteristics table) in conjunction with the top resistor defines each pin strap selection. The pin
detection checks for external resistor divider ratio during initial power up (VDD is brought down below
approximately 3 V) when BP LDO output is at approximately 2.9 V.
7.5.1.1 Address Selection (ADDR) Pin
The TPS549B22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as
001. The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address
detection circuit starts to work only after the initial power up when VDD has risen above its UVLO threshold.
Table 4 lists all combinations of the address selections. The 1% or better tolerance resistors with typical
temperature coefficient of ±100ppm/°C are recommended.
ADDR pin-strap configuration also programs the light load conduction mode.
7.5.1.2 VSEL Pin
VSEL pin strap configuration is used to program initial boot voltage value, hiccup mode and latch off mode. The
initial boot voltage is used to program the main loop voltage reference point. VSEL voltage settings provide TI
designated discrete internal reference voltages. Table 2 lists internal reference voltage selections.
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Table 2. Internal Reference Voltage Selections
VSEL[4]
VSEL[3]
VSEL[2]
VSEL[1]
1111: 0.975 V
1110: 1.1992 V
1101: 1.1504 V
1100: 1.0996 V
1011: 1.0508 V
1010: 1.0000 V
1001: 0.9492 V
1000: 0.9023 V
0111: 0.9004 V
0110: 0.8496 V
0101: 0.8008 V
0100: 0.7500 V
0011: 0.6992 V
0010: 0.6504 V
0001: 0.5996 V
0000: 0.975 V
(1)
20
VSEL[0]
RVSEL (kΩ)
1: Latch-Off
Open
0: Hiccup
187
1: Latch-Off
165
0: Hiccup
147
1: Latch-Off
133
0: Hiccup
121
1: Latch-Off
110
0: Hiccup
100
1: Latch-Off
90.9
0: Hiccup
82.5
1: Latch-Off
75
0: Hiccup
68.1
1: Latch-Off
60.4
0: Hiccup
53.6
1: Latch-Off
47.5
0: Hiccup
42.2
1: Latch-Off
37.4
0: Hiccup
33.2
1: Latch-Off
29.4
0: Hiccup
25.5
1: Latch-Off
22.1
0: Hiccup
19.1
1: Latch-Off
16.5
0: Hiccup
14.3
1: Latch-Off
12.1
0: Hiccup
10
1: Latch-Off
7.87
0: Hiccup
6.19
1: Latch-Off
4.64
0: Hiccup
3.16
1: Latch-Off
1.78
0: Hiccup
0
(1)
1% or better and connect to ground
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7.5.1.3 DCAP3 Control and Mode Selection
The MODE pinstrap configuration programs the control topology and internal soft-start timing selections. The
TPS549B22 device supports both DCAP3 and DCAP operation
MODE[4] selection bit is used to set the control topology. If MODE[4] bit is 0, it selects DCAP operation. If
MODE[4] bit is 1, it selects DCAP3 operation.
MODE[1] and MODE[0] selection bits are used to set the internal soft-start timing.
Table 3. Allowable MODE Pin Selections
MODE[4]
MODE[3]
MODE[2]
MODE[1]
0: DCAP
(1)
(2)
0: Internal
Reference
0: Internal
Reference
0: Internal SS
0: Internal SS
RMODE (kΩ)
60.4
10: 4 ms (2)
53.6
01: 2 ms
47.5
11: 8 ms
1: DCAP3
MODE[0]
(2)
00: 1 ms
42.2
11: 8 ms (2)
4.64
10: 4 ms (2)
3.16
01: 2 ms
1.78
00: 1 ms
0
(1)
1% or better and connect to ground
See Application Workaround to Support 4-ms and 8-ms SS Settings.
7.5.1.4 Application Workaround to Support 4-ms and 8-ms SS Settings
In order to properly design for 4-ms and 8-ms SS settings, additional application consideration is needed. The
recommended application workaround to support the 4-ms and 8-ms soft-start settings is to ensure sufficient time
delay between the VDD and EN_UVLO signals. The minimum delay between the rising maximum VDD UVLO level
and the minimum turn on threshold of EN_UVLO is at least TDELAY_MIN.
TDELAY _ MIN K u VREF
where
•
•
•
K = 9 ms/V for SS setting of 4 ms
K = 18 ms/V for SS setting of 8 ms
VREF is the internal reference voltage programmed by VSEL pin strap
(1)
For example, if SS setting is 4 ms and VREF = 1 V, program the minimum delay at least 9 ms; if SS setting is 8
ms, the minimum delay should be programmed at least 18 ms. See Figure 27 and Figure 28 for detailed timing
requirement. Because TPS549B22 is a PMBus device, the end user has the option of programming power-on
delay (POD) as another workaround. Be sure to follow the same calculation to determine the needed POD (see
MFR_SPECIFIC_01 (address = D1h) and Table 25 for detailed information).
Figure 27. Proper Sequencing of VDD and EN_UVLO to Support the use of 4-ms SS Setting
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VDD
VDD_UVLO
Maximum Threshold
4.34 V
EN_UVLO
Minimum
TDELAY_MIN
EN_UVLO
Minimum ON Threshold 1.45 V
Figure 28. Minimum Delay Between VDD and EN_UVLO to Support the use of 4-ms and 8-ms SS settings
The workaround/consideration described previously is not required for SS settings of 1 ms and 2 ms.
7.5.2 Programmable Analog Configurations
7.5.2.1 RSP/RSN Remote Sensing Functionality
RSP and RSN pins are used for remote sensing purpose. In the case where feedback resistors are required for
output voltage programming, connect the RSP pin to the mid-point of the resistor divider, and connect the RSN
pin to the load return. In the case where feedback resistors are not required as when the VSEL programs the
output-voltage setpoint, connect the RSP pin to the positive sensing point of the load, and the RSN pin must
always be connected to the load return.
RSP and RSN pins are extremely high-impedance input terminals of the true differential remote sense amplifier.
The feedback resistor divider must use resistor values much less than 100 kΩ.
7.5.2.1.1 Output Differential Remote Sensing Amplifier
The examples in this section show simplified remote sensing circuitry where each example uses an internal
reference of 1 V. Figure 29 shows remote sensing without feedback resistors, with an output voltage setpoint of 1
V. Figure 30 shows remote sensing using feedback resistors, with an output voltage setpoint of 5 V.
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TPS549B22
TPS549B22
38 RSN
38 RSN
39 RSP
39 RSP
40 VOSNS
40 VOSNS
BOOT
BOOT
5
5
Load
Load
+
+
±
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Figure 29. Remote Sensing Without Feedback
Resistors
±
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Figure 30. Remote Sensing With Feedback
Resistors
7.5.2.2 Power Good (PGOOD Pin) Functionality
The TPS549B22 device has power-good output that registers high when switcher output is within the target. The
power-good function is activated after soft start has finished. When the soft-start ramp reaches 300 mV above
the internal reference voltage, SS end signal goes high to enable the PGOOD detection function. If the output
voltage becomes within ±8% of the target value, internal comparators detect power-good state and the powergood signal becomes high after a 1-ms programmable delay. If the output voltage goes outside of ±16% of the
target value, the power-good signal becomes low after two microsecond (2-µs) internal delay. The open-drain
power-good output must be pulled up externally. The internal N-channel MOSFET does not pull down until the
VDD supply is above 1.2 V.
7.5.3 PMBus Programming
TPS549B22 has seven internal custom user-accessible 8-bit registers. The PMBus interface has been designed
for program flexibility, supporting direct format for write operation. Read operations are supported for both
combined format and stop separated format. While there is no auto increment/decrement capability in the
TPS549B22 PMBus logic, a tight software loop can be designed to randomly access the next register
independent of which register was accessed first. The start and stop commands frame the data packet and the
repeat start condition is allowed when necessary.
7.5.3.1 TPS549B22 Limitations to the PMBUS Specifications
TPS549B22 only recognizes seven bit addressing. This means TPS549B22 is not compatible with ten bit
addressing and CBUS communication. The device can operate in standard mode (100 kbit/s), fast mode (400
kbit/s) or faster mode (1000 kbit/s).
7.5.3.2 Slave Address Assignment
The seven bit slave address is 001A3A2A1A0x, where A3A2A1A0 is set by the ADDR pin on the device. Bit 0 is the
data direction bit, i.e. 001A3A2A1A00 is used for write operation and 001A3A2A1A01 is used for read operation.
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7.5.3.3 PMBUS Address Selection
TPS549B22 allows up to 16 different chip addresses for PMBus communication, with the first three bits fixed as
001. The address selection process is defined by the resistor divider ratio from BP pin to ADDR pin, and the
address detection circuit will start to work only after VDD input supply has risen above its UVLO threshold.
Table 4 lists the divider ratio and some example resistor values. The 1% tolerance resistors with typical
temperature coefficient of ±100 ppm/ºC are recommended. Higher performance resistors can be used if tighter
noise margin is required for more reliable address detection.
7.5.3.4 Supported Formats
The supported formats are described in the following subsections.
7.5.3.4.1 Direct Format — Write
The simplest format for a PMBus write is direct format. After the start condition [S], the slave chip address is
sent, followed by an eighth bit indicating a write. TPS549B22 then acknowledges that it is being addressed, and
the master responds with an 8 bit register address byte. The slave acknowledges and the master sends the
appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the
stop condition [P].
7.5.3.4.2 Combined Format — Read
After the start condition [S], the slave chip address is sent, followed by an eighth bit indicating a write.
TPS549B22 then acknowledges that it is being addressed, and the master responds with an 8-bit register
address byte. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the
slave chip address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge
followed by previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK) and finally
terminates the transfer with the stop condition [P].
7.5.3.5 Stop Separated Reads
Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a
read and return to that slave at a later time to read the data. In this format the slave chip address followed by a
write bit are sent after a start [S] condition. TPS549B22 then acknowledges it is being addressed, and the master
responds with the 8-bit register address byte. The master then sends a stop or restart condition and may then
address another slave. After performing other tasks, the master can send a start or restart condition to the
TPS549B22 with a read command. The device acknowledges this request and returns the data from the register
location that had been set up previously.
24
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Table 4. ADDR Pin Selection Table
PMBus_Address
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
CM
RADDR (kΩ)
(1% or better and
connect to ground)
1: FCCM
Open
0: SKIP
187
1: FCCM
165
0: SKIP
147
1: FCCM
133
0: SKIP
121
1: FCCM
110
0: SKIP
100
1: FCCM
90.9
0: SKIP
82.5
1: FCCM
75
0: SKIP
68.1
1: FCCM
60.4
0: SKIP
53.6
1: FCCM
47.5
0: SKIP
42.2
1: FCCM
37.4
0: SKIP
33.2
1: FCCM
29.4
0: SKIP
25.5
1: FCCM
22.1
0: SKIP
19.1
1: FCCM
16.5
0: SKIP
14.3
1: FCCM
12.1
0: SKIP
10
1: FCCM
7.87
0: SKIP
6.19
1: FCCM
4.64
0: SKIP
3.16
1: FCCM
1.78
0: SKIP
0
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7.5.3.6 Supported PMBUS Commands and Registers
Only the following PMBus commands are supported by TPS549B22, and not all parts of each command are
supported.
Table 5. PMBUS Command and Register Table
No. of DATA
BYTES
BIT PATTERN
1
00XX XX00 = Turn Off
1000 XX00 = Turn on (VOUT Margin off)
1001 0100 = Turn on (VOUT Margin Low, Ignore
Fault)
1001 1000 = Turn on (VOUT Margin Low, Act on
Fault)
1010 0100 = Turn on (VOUT Margin High,
Ignore Fault)
1010 1000 = Turn on (VOUT Margin High, Act
on Fault)
R/W Byte
1
0001 0011 = Act on neither OPERATION nor EN
pin
0001 0111 = Act on EN pin and ignore
OPERATION
0001 1011 = Act on OPERATION and ignore EN
pin
0001 1111 = Act on OPERATION and Act on EN
pin (requires both)
Send Byte
0
No data. Write only.
R/W Byte
1
1000 0000 Only allow WRITE_PROTECT
0100 0000 Only allow WRITE_PROTECT and
OPERATION
0010 0000 Only allow WRITE_PROTECT,
OPERATION, ON_OFF_CONFIG and
VOUT_COMMAND
0000 0000 Allow all writes
no
Send Byte
0
No data. Write only.
Restores all parameters from
non-volatile Default Store
Memory to Operating Memory
no
Send Byte
0
No data. Write only.
CAPABILITY
This command provides a way
for a host system to determine
some key capabilities of a
PMBus device, including PEC,
Alert and Speed.
no
Read Byte
1
1101 0000 = PEC, 1-MHz bus speed, ALERT
20h
VOUT_MODE
Hard coded to linear mode with
exponent of –9.
no
Read Byte
1
000x xxxx = Linear format.
0001 0111 = Exponent value of –9 (1.953 mV
resolution)
21h
VOUT_COMMAND
Output voltage setpoint. DAC
resolution is 1.9531 mV and
range is ~0.6 V to ~1.200 V
yes
R/W Word
2
0000 0001 0011 0011 = 0.5996 V
0000 0010 0110 0110 = 1.1992 V
25h
VOUT_MARGIN_HIGH
Sets the voltage to which the
output is to be changed when
the OPERATION command is
set to "MARGIN HIGH".
no
R/W Word
2
0000 0001 0011 0011 = 0.5996 V
0000 0010 0110 0110 = 1.1992 V
26h
VOUT_MARGIN_LOW
Sets the voltage to which the
output is to be changed when
the OPERATION command is
set to "MARGIN LOW".
no
R/W Word
2
0000 0001 0011 0011 = 0.5996 V
0000 0010 0110 0110 = 1.1992 V
78h
STATUS_BYTE
Status of all fault conditions in a
data byte.
no
Read Byte
1
See Table 6
79h
STATUS_WORD
Status of all fault conditions in
two data bytes.
no
Read Word
2
See Table 6
7Ah
STATUS_VOUT
Returns one byte of information
relating to the status of the
output voltage related faults.
no
Read Byte
1
See Table 8
7Bh
STATUS_OUT
Returns one byte of information
relating to the status of the
output current related faults.
no
Read Byte
1
See Table 8
CMD CODE
COMMAND NAME
DESCRIPTION
OPERATION
The OPERATION command is
used to turn the unit on and off
in conjunction with the input
from the EN pin. It is also used
to cause the device to set the
output voltage to the upper or
lower margin voltages.
ON_OFF_CONFIG
Configures the combination of
EN pin input and serial bus
commands needed to turn the
unit on and off. This includes
how the unit responds when
power is applied.
yes
CLEAR_FAULTS
Clears all fault status registers
to 0x00 and deasserts
SMBAlert. The "Unit is Off" bit
in the status byte and
"PGOOD# de-assertion" bit in
the status word are not cleared
when this command is issued.
no
10h
WRITE_PROTECT
Prevents unwanted writes to
the device. This register can be
over-written. This is not a
permanent lock.
yes
11h
STORE_DEFAULT_ALL
Copies Operating Memory to
matching non-volatile Default
Store Memory.
12h
RESTORE_DEFAULT_ALL
19h
1h
2h
3h
26
NVM?
no
TYPE
R/W Byte
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Table 5. PMBUS Command and Register Table (continued)
CMD CODE
COMMAND NAME
DESCRIPTION
NVM?
TYPE
No. of DATA
BYTES
BIT PATTERN
XXX0 0000
0XX0 0000 = A valid or supported command has
been received
1XX0 0000 = An invalid or unsupported
command has been received
X0X0 0000 = A valid or supported data has been
received
X1X0 0000 = An invalid or unsupported data has
been received
XX00 0000 = Packet error check has failed
XX10 0000 = Packet error check has succeeded
Status of communications, logic
and memory in a data byte
no
Read Byte
1
MFR_SPECIFIC_00
Customer programmable byte
that does not affect chip
functionality
yes
R/W Byte
1
MFR_SPECIFIC_01
Program PGOOD delay and
Power-On delay
yes
R/W Byte
1
D2h
MFR_SPECIFIC_02
Read SST, CM, HICLOFF, TRK
and SEQ. Program Forced
SKIP Soft Start.
yes
R/W Byte
1
D3h
MFR_SPECIFIC_03
Program Fsw and control
mode, Read RC ramp
yes
R/W Byte
1
D4h
MFR_SPECIFIC_04
Program the DCAP3 offset
yes
R/W Byte
1
D6h
MFR_SPECIFIC_06
Program the VDD UVLO level
yes
R/W Byte
1
D7h
MFR_SPECIFIC_07
Program the final tracking set
point and select
pseudo/external tracking
yes
R/W Byte
1
FCh
MFR_SPECIFIC_44
Read TI PMBUS GUI Devcie ID
and IC revision code
no
Read Word
2
7Eh
STATUS_CML
D0h
D1h
Free format
spacer
spacer
Figure 31. Start-up and VOUT_COMMAND Timing Diagram
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Table 6. Status Word Summary Table
BITS
NAME
MEANING
Low 7
not used
not used
Low 6
OFF
Unit is not providing power to the output
Low 5
VOUT_OV_FAULT
Output overvoltage
Low 4
IOUT_OC_FAULT
Output overcurremt
Low 3
VDD_UV_FAULT
Input VDD undervoltage
Low 2
TEMP
Internal die temperature.
Overtemperature fault
Low 1
CML
Communications, logic or memory fault
Low 0
OTHER
None of the above in the PMBUS spec
High 7
VOUT
Any output voltage fault or warning
High 6
IOUT
Any output current fault or warning
High 5
VDD_UV_FAULT
Input VDD undervoltage
High 4
not used
Not used
High 3
PGOOD#
Power good de-asserted
High 2
not used
not used
High 1
not used
not used
High 0
not used
not used
Table 7. Status VOUT Summary Table
BITS
NAME
MEANING
7
OVF
Overvoltage fault
6
OVW
Overvoltage warning
5
UVW
Undervoltage warning
4
UVF
Undervoltage fault
3
not used
not used
2
not used
not used
1
not used
not used
Table 8. Status IOUT Summary Table
28
BITS
NAME
MEANING
7
OCF
Overcurrent fault
6
OCUVF
Overcurrent and output undervoltage
fault
5
not used
not used
4
UCF
Negative overcurrent limit
3
not used
not used
2
not used
not used
1
not used
not used
0
not used
not used
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7.6 Register Maps
7.6.1 OPERATION Register (address = 1h)
Figure 32. OPERATION
7
On_OFF
R/W
6
0
R/W
5
4
3
OPMARGIN
R/W
2
1
0
R
0
0
R
RLEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. OPERATION
Bit
7
Field
Type
Reset
Description
ON_OFF
R/W
0
0: Turn off switching converter (if CMD=1)
1: Turn on switching converter (if CMD=1), and also enable
VOUT Margin function
R
0
6
5:2
OPMARGIN
R/W
0
1
R
0
0
R
0
00xx: Turn off VOUT Margin function
0101: Turn on VOUT Margin Low and Ignore Fault
0110: Turn on VOUT Margin Low and Act On Fault
1001: Turn on VOUT Margin High and Ignore Fault
1010: Turn on VOUT Margin High and Act On Fault
7.6.2 ON_OFF_CONFIG Register (address = 2h)
Figure 33. ON_OFF_CONFIG
7
0
R
6
0
R
5
0
R
4
1
R
3
CMD
R/W
2
CP
R/W
1
1
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. ON_OFF_CONFIG
Bit
Type
Reset
7
Field
R
0
6
R
0
5
R
0
4
R
1
Description
3
CMD
R/W
0
0: Ignore ON_OFF bit
1: Act on ON_OFF bit
2
CP
R/W
1
0: Ignore ON_OFF bit
1: Act on ON_OFF bit
1
R
1
0
R
1
7.6.3 CLEAR FAULTS (address = 3h)
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command simultaneously
clears all bits in all status registers. At the same time, the device clears its SMB_ALERT# signal output if the
device is asserting the SMB_ALERT# signal.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the
fault is still present when the bit is cleared, the fault bit shall immediately be set again and the host notified by the
usual means.
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7.6.4 WRITE PROTECT (address = 10h)
Figure 34. WRITE PROTECT
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. WRITE PROTECT
Bit
Field
7:0
Type
WRITE_PROTECT
R/W
Reset
Description
0
00000000: Enable writes to ALL commands
00100000: Enable writes to only WRITE_PROTECT,
OPERATION and ON_OFF_CONFIG and VOUT_COMMAND
commands
01000000: Enable writes to only WRITE_PROTECT and
OPERATION
10000000: Enable writes to only WRITE_PROTECT
7.6.5 STORE_DEFAULT_ALL (address = 11h)
Store all of the current storable register settings in the EEPROM memory as the new defaults on power up.
It is permitted to use the STORE_DEFAULT_ALL command while the device is operating. However, the device
may be unresponsive during the write operation with unpredictable memory storage results. TI recommends to
turn the device output off before issuing this command.
EEPROM programming faults will set the ‘CML’ bit in the STATUS_BYTE and the ‘MEM’ bit in the STATUS_CML
registers.
7.6.6 RESTORE_DEFAULT_ALL (address = 12h)
Write EEPROM data to those CSRs that: (1) have EEPROM support, and; (2) are unprotected according to
current setting of WRITE_PROTECT.
It is permitted to use the RESTORE_DEFAULT_ALL command while the device is operating. However, the
device may be unresponsive during the copy operation with unpredictable, undesirable or even catastrophic
results. TI recommends turning the device output off before issuing this command.
No data bytes are sent, just the command code is sent.
7.6.7 CAPABILITY (address = 19h)
This command provides a way for a host system to determine some key capabilities of this PMBus device.
Figure 35. CAPABILITY
7
PEC=1
R
6
5
4
ALRT=1
R
SPEED
R
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CAPABILITY
Bit
Field
Type
Reset
Description
PEC=1
R
1
1: Packet Error Checking is supported
SPEED
R
10b
10: Maximum supported bus speed is 1 MHz
ALRT=1
R
1
TPS549B22 has an ALERT# pin and it supports SMBus Alert Response
protocol
3
R
0
2
R
0
1
R
0
0
R
0
7
6:5
4
30
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7.6.8 VOUT_MODE (address = 20h)
Figure 36. VOUT_MODE
7
6
MODE = 000
R
R
5
4
3
R
R
R
2
Exponent = 10111
R
1
0
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. VOUT_MODE
Bit
Field
Type
Reset
Description
7:5
MODE = 000
R
0
000: Linear Format
4:0
Exponent
R
17h
10111: Exponent = −9 (equivalent of 1.9531 mV/LSB)
7.6.9 VOUT_COMMAND (address = 21h)
The VOUT_COMMAND command sets the output voltage in volts. The exponent is set be VOUT_MODE at –9
(equivalent of 1.9531 mV/LSB). The programmed VOUT is computed as:
VOUT = VOUT_COMMAND × VOUT_MODE volts = VOUT_COMMAND × 2–9 V
(2)
The support range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9 bits limited to 307 to 614 decimal.
Slew-rate control is provided through MODE pin.
VOUT changes 1 step per tslew, where tslew is programmable by MODE pin: 4, 8, 16, or 32 µs.
Figure 37. VOUT_COMMAND
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
7
6
Mantissa
R/W
R/W
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. VOUT_COMMAND
Bit
Field
Type
Reset
7:4
Mantissa
R
0000
3:0
Mantissa
R/W
00xx
7:0
Mantissa
R/W
xxxx xxxx
Description
x = pin strap
7.6.10 VOUT_MARGIN_HIGH (address = 25h) ®
The VOUT_MARGIN_HIGH command loads the TPS549B22 with the voltage to which the output is to be
changed when the OPERATION command is set to “Margin High”.
The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.
The support margin range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9 bits limited to 307 to 614
decimal. Slew-rate control is provided through MODE pin.
Figure 38. VOUT_MARGIN_HIGH
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
7
6
Mantissa
R/W
R/W
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. VOUT_MARGIN_HIGH
Bit
Field
Type
Reset
7:4
Mantissa
R
0000
3:0
Mantissa
R/W
00xx
7:0
Mantissa
R/W
xxxx xxxx
Description
x = pin strap
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7.6.11 VOUT_MARGIN_LOW (address = 26h)
The VOUT_MARGIN_LOW command loads the TPS549B22 with the voltage to which the output is to be
changed when the OPERATION command is set to “Margin Low”.
The data bytes are two bytes formatted according to the setting of the VOUT_MODE command.
The support margin range for TPS549B22 is: 0.5996 V to 1.1992 V. It is effectively 9-bits limited to 307 to 614
decimal. Slew-rate control is provided through MODE pin.
Figure 39. VOUT_MARGIN_LOW:
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R/W
R/W
7
6
Mantissa
R/W
R/W
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. VOUT_MARGIN_LOW:
Bit
Field
Type
Reset
7:4
Mantissa
R
0000
3:0
Mantissa
R/W
00xx
7:0
Mantissa
R/W
xxxx xxxx
Description
x = pin strap
7.6.12 STATUS_BYTE (address = 78h)
Figure 40. STATUS_BYTE
7
Not used
R
6
OFF
R
5
VOUT_OV
R
4
IOUT_OC
R
3
VDD_UV
R
2
TEMP
R
1
CML
R
0
OTHER
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. STATUS_BYTE
Bit
7
32
Field
Type
Reset
Description
Not Used
R
N/A
Not used
6
OFF
R
N/A
0: IC is on. This includes the following fault response conditions
where the output is still being actively driven, such as OVP and
OCF.
1: IC is off. This includes two conditions. One is unit is
commanded off via OPERATION/ON_OFF _CONFIG and the
other is unit is commanded on via
OPERATION/ON_OFF_CONFIG; but, due to fault response the
output has been tri-stated by UVF, OT and UVLO.
5
VOUT_OV
R
N/A
0: An output overvoltage fault has not occurred
1: An output overvoltage fault has occurred
4
IOUT_OC
R
N/A
0: An output overcurrent fault has not occurred
1: An output overcurrent fault has occurred
3
VDD_UV
R
N/A
0: An input undervoltage fault has not occurred
1: An input undervoltage fault has occurred
2
TEMP
R
N/A
0: A temperature fault or warning has not occurred
1: A temperature fault or warning has occurred
1
CML
R
N/A
0: A communications, memory or logic fault has not occurred
1: A communications, memory or logic fault has occurred
0
OTHER
R
N/A
0: A fault or warning not listed above has not occurred
1: A fault of warning not listed above has occurred
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7.6.13 STATUS_WORD (High Byte) (address = 79h)
Figure 41. STATUS_WORD (High Byte)
7
VOUT
R
6
IOUT
R
5
VDD
R
4
Not Used
R
3
PGOOD#
R
2
1
Not Used
R
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. STATUS_WORD (High Byte)
Bit
Field
Type
Reset
Description
7
VOUT
R
N/A
0: An output voltage fault or warning has not occurred
1: An output voltage fault or warning has occurred
6
IOUT
R
N/A
0: An output current fault has not occurred
1:An output current fault has occurred
5
VDD
R
N/A
A VDD voltage fault has not occurred
1: A VDD voltage fault has occurred
4
Not Used
R
N/A
Not Used
3
PGOOD#
R
N/A
0: PGOOD pin is at logic high
1: PGOOD pin is at logic high
2:0
Not Used
R
N/A
Not used
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7.6.14 STATUS_VOUT (address = 7Ah)
Figure 42. STATUS_VOUT
7
OVF
R
6
OVW
R
5
UVW
R
4
UVF
R
3
2
1
0
Not Used
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. STATUS_VOUT
Bit
Field
Type
Reset
Description
7
OVF
R
N/A
0: An output overvoltage fault has not occurred
1: An output overvoltage fault has occurred
6
OVW
R
N/A
0: An output overvoltage warning has not occurred
1: An output overvoltage warning has occurred
5
UVW
R
N/A
0: An output undervoltage warning has not occurred
1: An output undervoltage warning has occurred
4
UVF
R
N/A
0: An output undervoltage fault has not occurred
1: An output undervoltage fault has occurred
Not Used
R
N/A
Not Used
3:0
7.6.15 STATUS_IOUT (address = 7Bh)
Figure 43. STATUS_IOUT
7
OCF
R
6
OCUVF
R
5
Not Used
R
4
UCF
R
3
2
1
0
Not Used
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. STATUS_IOUT
Bit
Field
Type
Reset
Description
7
OCF
R
N/A
0: An output positive overcurrent fault has not occurred
1: An output positive overcurrent fault has occurred
6
OCUVF
R
N/A
0: A simultaneous output positive overcurrent and undervoltage
fault has not occurred
1: A simultaneous output positive overcurrent and undervoltage
fault has occurred
5
Not Used
R
N/A
Not Used
4
UCF
R
N/A
0: An output negative overcurrent fault has not occurred
1: An output negative overcurrent fault has occurred
Not Used
R
N/A
Not Used
3:0
34
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7.6.16 STATUS_CML (address = 7Eh)
Figure 44. STATUS_CML
7
COMM
R
6
DATA
R
5
PEC
R
4
3
Not Used
R
2
1
OTH
R
0
Not Used
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. STATUS_CML
Bit
Field
Type
Reset
Description
7
COMM
R
N/A
0: A valid or supported command has been received
1: An invalid or unsupported command has been received
6
DATA
R
N/A
0: A valid or supported data has been received
1: An invalid or unsupported data has been received
5
PEC
R
N/A
0: Packet Error Check has failed
1: Packet Error Check has succeeded
Not Used
R
N/A
Not Used
4:2
1
OTH
R
N/A
0: A communication fault other than the ones listed in this table
has not occurred
1: A communication fault other than the ones listed in this table
has occurred. Currently, this bit is only set for too many data
bytes
0
Not Used
R
N/A
Not Used
7.6.17 MFR_SPECIFIC_00 (address = D0h)
Figure 45. MFR_SPECIFIC_00
7
6
5
4
3
USER SCRATCH PAD
R/W
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. MFR_SPECIFIC_00
Bit
Field
Type
Reset
Description
7:0
USER SCRATCH PAD
R/W
0
The MFR_SPECIFIC_00 is a user-accessible register dedicated
as a user scratch pad.
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7.6.18 MFR_SPECIFIC_01 (address = D1h)
Figure 46. MFR_SPECIFIC_01
7
0
R
6
0
R
5
4
PGD
R/W
3
2
1
POD
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. MFR_SPECIFIC_01
Bit
Field
7:6
Type
Reset
R
00b
5:3
PGD
R/W
010b
2:0
POD
R/W
010b
Description
The MFR_SPECIFIC_01 is a user-accessible register dedicated
for configuring the PGOOD delay and Power-On Delay
functions. (Refer to Table 24 and Table 25)
Table 24. PGD[2:0]
PGD[2]
PGD[1]
PGD[0]
PGood Delay
0
0
0
256 µs
0
0
1
512 µs
0
1
0
1.024 ms
0
1
1
2.048 ms
1
0
0
4.096 ms
1
0
1
8.192 ms
1
1
0
16.384 ms
1
1
1
131.072 ms
Table 25. POD[2:0]
36
POD[2]
POD[1]
POD[0]
Power-On Delay
0
0
0
256 µs
0
0
1
512 µs
0
1
0
1.024 ms
0
1
1
2.048 ms
1
0
0
4.096 ms
1
0
1
8.192 ms
1
1
0
16.384 ms
1
1
1
32.768 ms
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7.6.19 MFR_SPECIFIC_02 (address = D2h)
The MFR_SPECIFIC_02 register allows the user to read the configuration of various pin-strap features and/or
overwrite them. Note that any overwritten values here are only good until the next power-on-reset, when all
parameters revert back to their pin-strap configurations.
Figure 47. MFR_SPECIFIC_02
7
TRK
R/W
6
SEQ
R/W
5
0
R
4
FORCESKIPSS
R/W
3
2
1
HICLOFF
R/W
SST
R/W
0
CM
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. MFR_SPECIFIC_02
Bit
7
6
Field
Type
TRK
3:2
1
0
Description
P
This bit indicates whether the device is using internal or external
reference voltage tracking. It will initially be loaded and reflect
the value of the pin strap; but, can also be overwritten by
PMBus.
0: No tracking. The device will use internal reference voltage.
1: External tracking.
R/W
P
This bit indicates whether the device is using internal or external
soft-start ramp. It will initially be loaded and reflect the value of
the pin strap; but, can also be overwritten by PMBus.
0: No sequencing. The device will use the internal soft start
ramp.
1: Sequencing
R
0
R/W
SEQ
5
4
Reset
FORCESKIPSS
R/W
1
This bit (when set) allows the user to force Soft-start to always
use SKIP mode; regardless of the CM pin strap.
0: CM bit controls whether to operate in SKIP or FCCM mode
during and after soft start.
1: Soft start is forced to operate in SKIP mode, then CM bit
controls the mode after soft start.
SST
R/W
P
These bits indicate the time the device takes to ramp the output
voltage up to regulation (that is, soft-start). The field will initially
be loaded and reflect the value of the pin strap; but, can also be
overwritten by PMBus. (Refer to Table 27)
P
This bit indicates the response the device will take upon an
output undervoltage fault. There are two fault response options
which are enforced by the analog circuits: Hiccup or Latch-off.
The bit value will initially be loaded and reflect the value of the
pin strap; but, can also be overwritten by PMBus.
0: Hiccup after UVP fault.
1: Latch off after UVP fault.
P
This bit indicates the conduction mode for the device. The bit
value will initially be loaded and reflect the value of the pin strap;
but,
can
also
be
overwritten
by
PMBus.
0: SKIP
1: FCCM
HICLOFF
R/W
CM
R/W
Table 27. SST
SST[1]
SST[0]
Soft-start time
0
0
1 ms
0
1
2 ms
1
0
4 ms
1
1
8 ms
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7.6.20 MFR_SPECIFIC_03 (address = D3h)
The MFR_SPECIFIC_03 register allows the user to read the configuration of the DCAP pin-strap feature (and/or
overwrite it), as well configure the Ramp Generator and the PWM switching frequency.
Figure 48. MFR_SPECIFIC_03
7
DCAP3
R/W
6
0
R
5
4
3
0
R
RCSP
R/W
2
1
FS
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. MFR_SPECIFIC_03 Field Descriptions
Bit
7
Field
Type
DCAP3
6
5:4
RCSP
3
2:0
FS
Reset
Description
R/W
P
This bit allows the user to read/configure the device’s internal
DCAP-3 mode. It is initially loaded and reflects the value of the
pin strap, but can also be overwritten by PMBus.
0: Internal DCAP3 is disabled (ramp injection is off).
1: Internal DCAP3 is enabled (ramp injection is on)
R
0
R/W
P
R
0
R/W
011b
These bits allow the user to read/configure the D-CAP3 ramp
generator’s resistor value selection. (Refer to Table 29.)
These bits allow the user to read/configure the device’s PWM
switching frequency. (Refer to Table 30)
Table 29. RCSP
RCSP[1]
RCSP[0]
Resistor Selection
0
0
Resistor ÷ 2
0
1
Resistor ÷ 1
1
0
Resistor × 2
1
1
Resistor × 3
Table 30. FS
38
FS[2]
FS[1]
FS[0]
Switching Frequency
0
0
0
315 kHz
0
0
1
425 kHz
0
1
0
550 kHz
0
1
1
650 KHz
1
0
0
825 KHz
1
0
1
900 KHz
1
1
0
1.025 MHz
1
1
1
1.125 MHz
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7.6.21 MFR_SPECIFIC_04 (address = D4h)
The MFR_SPECIFIC_04 register allows the user to configure the D-CAP offset reduction and fixed offset
correction.
Figure 49. MFR_SPECIFIC_04
7
DCAP3OffsetSel
R/W
6
5
DCAP3Offset[1:0]
R/W
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. MFR_SPECIFIC_04
Bit
7
6:5
Field
Type
Reset
Description
DCAP3OffsetSel
R/W
1
This bit allows the user to read/configure the D-CAP loop’s offset
reduction scheme.
0: Select DCAP loop manual offset reduction circuit.
1: Select DCAP loop automatic offset reduction circuit.
DCAP3Offset
R/W
0
These bits allow the user to read/configure the D-CAP3 offset
correction if and only if DCAP3OffsetSel = 0 (refer to Table 32).
R
0
4:0
Table 32. DCAP3OFFSET
Additional Offset Correction
Voltage Added
DCAP3Offset[1]
DCAP3Offset[0]
0
0
0 mV
0
1
+ 2 mV
1
0
+ 4 mV
1
1
+ 6 mV
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7.6.22 MFR_SPECIFIC_06 (address = D6h)
The MFR_SPECIFIC_06 is a user-accessible register dedicated for configuring the VDD UVLO threshold.
Figure 50. MFR_SPECIFIC_06
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
1
VDDUVLO[2:0]
R/W
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. MFR_SPECIFIC_06
Bit
Field
7:3
2:0
VDDUVLO
Type
Reset
R
0
R/W
101b
Description
These bits allow the user to read/configure the device VDD
ULVO threshold (refer to Table 34).
Table 34. VDDUVLO
40
VDDUVLO[2]
VDDUVLO[1]
VDDUVLO[0]
VDD UVLO threshold
0
X
X
10.2 volts
1
0
0
2.8 volts
1
0
1
4.25 volts
1
1
0
6 volts
1
1
1
8.1 volts
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7.6.23 MFR_SPECIFIC_07 (address = D7h)
The MFR_SPECIFIC_07 is a user-accessible register dedicated for configuring the device’s PGOOD threshold
and external tracking options.
Figure 51. MFR_SPECIFIC_07
7
VPBAD
R/W
6
SPARE
R/W
5
0
R
4
TRKOPTION
R/W
3
2
1
0
VTRKIN[3:0]
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. MFR_SPECIFIC_07
Bit
Field
Type
Reset
Description
7
VPBAD
R/W
1
This bit allows the user to read/configure the PGOOD high and
low thresholds.
0: PGOOD high and low thresholds are +16% and -16%,
respectively
1: PGOOD high and low thresholds are +20% and -32%,
respectively
6
SPARE
R/W
0
This bit allows the user to read/configure an EEPROM backed
SPARE bit and corresponding digital block output.
0: pSPARE = 0
1: pSPARE = 1
R
0
5
4
3:0
TRKOPTION
R/W
0
This bit allows the user to read/control whether the external
TRKIN is enabled by a 425 mV threshold, or not.
0: TRKIN voltage must be above 425mV (that is, TRKINOK = 1)
before switcher can be enabled.
1: TRKIN voltage does not need to be above 425mV before
switcher can be enabled.
VTRKIN
R/W
1111b
These bits allow the user to read/configure the device’s final
TRKIN target voltage for external tracking operation. (Refer to
Table 36)
Table 36. VTRKIN
VTRKIN[3]
VTRKIN[2]
VTRKIN[1]
VTRKIN[0]
Final TRKIN target
voltage for
external tracking
operation
0
0
0
0
500 mV
0
0
0
1
550 mV
0
0
1
0
600 mV
0
0
1
1
650 mV
0
1
0
0
700 mV
0
1
0
1
750 mV
0
1
1
0
800 mV
0
1
1
1
850 mV
1
0
0
0
900 mV
1
0
0
1
950 mV
1
0
1
0
1.00 V
1
0
1
1
1.05 V
1
1
0
0
1.10 V
1
1
0
1
1.15 V
1
1
1
0
1.20 V
1
1
1
1
1.25 V
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7.6.24 MFR_SPECIFIC_44 (address = FCh)
The DEVICE_CODE command returns a 12-bit unique identifier code for the device and a 4 bit device revision
code.
Figure 52. MFR_SPECIFIC_44
7
6
5
4
3
R
R
R
R
R
2
1
0
Identifier Code
R
R
R
7
6
5
4
3
R
R
R
R
R
2
1
Revision Code
R
R
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. MFR_SPECIFIC_44
Bit
7:0
7:4
3:0
Field
Identifier Code
Revision Code
Type
Reset
R
02h
R
0
R
0
Description
0000 0010 0000b – Device ID Code Identifier for TPS549B22.
1000b - Revision Code (first silicon starts at 0)
Can
42
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS549B22 device is a highly-integrated synchronous step-down DC-DC converter with PMBus features
and capabilities. This devices is used to convert a higher DC input voltage to a lower DC output voltage, with a
maximum output current of 25 A. Use the following design procedure to select key component values for this
family of devices.
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8.2 Typical Applications
8.2.1 TPS549B22 1.5-V to 18-V Input, 1-V Output, 25-A Converter
J1
VIN = 6V - 16V
C1
DNP 330uF
C11
100µF
DNP
C2
22µF
C3
22µF
C12
330uF
C13
22µF
C4
22µF
DNPC14
22uF
C5
22µF
DNPC15
22uF
C6
22µF
DNPC16
22uF
C7
22µF
DNPC17
22uF
C8
22µF
DNPC18
22uF
C9
22µF
DNPC19
22uF
C10
2200pF
DNPC20
22µF
J2
PGND
VDD
TP1
R1
1.00
U1
VDD
DNP
R6
200k
C34
1uF
C35
1µF TP4
VDD
21
22
23
24
25
PVIN
PVIN
PVIN
PVIN
PVIN
DRGND
TP9
BP
4
CNTL
CNTL/EN_UVLO
BP
J4
LOW
28
R12
100k
C45
4.7µF
DNP C44
1uF
R13
PGOOD
TP8
100k
MODE
FSEL
DRGND
DRGND
TP12
ILIM
VSEL
35
PGOOD
34
MODE
33
36
37
DNP C46
1000pF
ALERT
DATA
1
2
3
CLK
29
AGND
30
SW
SW
SW
SW
SW
EN_UVLO
BP
TP14
R19
61.9k
BOOT
31
32
VOSNS
40
NetC31_1
R10
5
TP2
0
8
9
10
11
12
NC
NC
NC
NC
6
7
26
27
RSP
39
TP5
SW
C22
0.1µF
330nH
TP6
DNPC21
R5
DNP
470pF
1.50k
PGND
R11
0
R8 DNPC32
1.10k 6800pF
CHA
C31
DNP
0.1uF
C36
1000pF
ADDR
TP7
J3
R3
DNP
0
R15
10.0k
C25
100µF
C26
100µF
DNPC27
100µF
DNPC28
100µF
C29
100µF
DNPC30
100uF
DNP C23
470µF
C24
470µF
C39
100µF
C40
100µF
DNPC41
100µF
C42
100µF
DNPC43
100uF
DNP C37
470uF
C38
470µF
R16
38
J5
0
ILIM
RESV_TRK
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SMB_ALRT#
PMB_DATA
PMB_CLK
DRGND
AGND
PAD
VOUT = 1V
I_OUT = 25A MAX
C33
100µF
R14
DNP
0
NetC31_1
RSN
TP3
Remote Sense pos/neg should run as balanced pair
R4
0
CHB
R7
0
TP19
R9
DNP
3.01
DNP
VSEL
R2
DNP
0
L1
TP10
13
14
15
16
17
18
19
20
TP13
TP18
PGND
PGND
NT1
NT2
Net-Tie
Net-Tie
R17
DNP
0
TP11
R18
DNP
0
PGND
41
TPS549B22RVFR
DRGND
AGND
PGND
AGND
PGND
DRGND
----- GND NET TIES ----TP15
VSEL
TP16
MODE
TP17
FSEL
R20
100k
VSEL
R21
100k
MODE
R22
100k
J6
1
3
5
7
9
2
4
6
8
10
DATA
ALERT
CLK
BP
TP20
CLK
TP21
DATA
TP22
ALERT
FSEL
PMBus
R23
37.4k
R24
42.2k
R25
25.5k
AGND
AGND
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Figure 53. Typical Application Schematic
44
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8.2.2 Design Requirements
For this design example, use the input parameters shown in Table 38.
Table 38. Design Example Specifications
PARAMETER
VIN
Input voltage
VIN(ripple)
Input ripple voltage
VOUT
Output voltage
TEST CONDITION
MIN
TYP
MAX
5
12
18
V
0.4
V
IOUT = 25 A
1
Line regulation
5 V ≤ VIN ≤ 18 V
UNIT
V
0.5%
Load regulation
0 V ≤ IOUT ≤ 25 A
VPP
Output ripple voltage
IOUT = 25 A
10
mV
VOVER
Transient response overshoot
ISTEP = 15 A
30
mV
VUNDER
Transient response undershoot
ISTEP = 15 A
30
IOUT
Output current
5 V ≤ VIN ≤ 18 V
tSS
Soft-start time
IOC
Overcurrent trip point
η
Peak efficiency
fSW
Switching frequency
0.5%
mV
25
IOUT = 7 A,
A
1
ms
32
A
90%
650
kHz
8.2.3 Detailed Design Procedure
8.2.3.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS549B22 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.3.2 Switching Frequency Selection
The default switching frequency of the TPS549B22 device is 650 kHz. There are a total of 8 switching frequency
settings that can be programmed via PMBus interface. For each switching frequency setting, there are 4 internal
ramp compensations (DCAP3) to choose from, also via PMBus. When DCAP3 mode is selected (preferred), the
internal ramp compensation is used for stabilizing the converter design. The ramp is a function of the switching
frequency and duty cycle range (the output voltage to input voltage ratio). Table 39 summarizes the ramp
choices using these functions.
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Table 39. Switching Frequency Selection
SWITCHING FREQUENCY
SETTING
(fSW) (kHz)
RAMP
SELECT
OPTION
R/2
315,
425
R×1
R×2
550,
650
825,
900
1.025,
1.225 MHz
TIME
CONSTANT
t (µs)
VOUT RANGE
(FIXED VIN = 12 V)
DUTY CYCLE RANGE
(VOUT/VIN) (%)
MIN
MAX
MIN
MAX
9
0.6
0.9
5
7.5
16.8
0.9
1.5
7.5
12.5
32.3
1.5
2.5
12.5
21
R×3
55.6
2.5
5.5
>21
R/2
7
0.6
0.9
5
7.5
R×1
13.5
0.9
1.5
7.5
12.5
R×2
25.9
1.5
2.5
12.5
21
R×3
44.5
2.5
5.5
R/2
5.6
0.6
0.9
5
7.5
R×1
10.4
0.9
1.5
7.5
12.5
R×2
20
1.5
2.5
12.5
21
R×3
34.4
2.5
5.5
>21
R/2
3.8
0.6
0.9
5
7.5
R×1
7.1
0.9
1.5
7.5
12.5
R×2
13.6
1.5
2.5
12.5
21
R×3
23.3
2.5
5.5
>21
>21
8.2.3.3 Inductor Selection
To calculate the value of the output inductor, use Equation 3. The coefficient KIND represents the amount of
inductor ripple current relative to the maximum output current. The output capacitor filters the inductor ripple
current. Therefore, choosing a high inductor ripple current impacts the selection of the output capacitor since the
output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general,
maintain a KIND coefficient between 0 and 40 for balanced performance. Using this target ripple current, the
required inductor size can be calculated as shown in Equation 3
VOUT
L1
u
VIN max u fSW
VIN
1V u 18 V 1V
VOUT
18 V u 650 kHz u 25 A u 0.2
IOUT max u KIND
0.29 PH
(3)
Selecting a KIND of 0.2, the target inductance L1 = 290 nH. Using the next standard value, the 330 nH is chosen
in this application for its high current rating, low DCR, and small size. The inductor ripple current, RMS current,
and peak current can be calculated using Equation 4, Equation 5 and Equation 6. Use these values to select an
inductor with approximately the target inductance value, and current ratings that allow normal operation with
some margin.
VIN max VOUT
1 V u 18 V 1 V
VOUT
IRIPPLE
4.4 A
u
L1
18
V
u 650 kHz u 330 nH
VIN max u fSW
(4)
IL rms
IL peak
46
IOUT
IOUT
2
1
u IRIPPLE
12
1
u IRIPPLE
2
2
25 A
(5)
27.2 A
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8.2.3.4 Output Capacitor Selection
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
affects three criteria:
• Stability
• Regulator response to a change in load current or load transient
• Output voltage ripple
These three considerations are important when designing regulators that must operate where the electrical
conditions are unpredictable. The output capacitance needs to be selected based on the most stringent of these
three criteria.
8.2.3.4.1 Minimum Output Capacitance to Ensure Stability
To prevent sub-harmonic multiple pulsing behavior, TPS549B22 application designs must strictly follow the small
signal stability considerations described in Equation 7.
t
V
8W
u REF
COUT min ! ON u
2 LOUT VOUT
where
•
•
•
•
•
•
COUT(min) is the minimum output capacitance needed to meet the stability requirement of the design
tON is the on-time information based on the switching frequency and duty cycle (in this design, 128 ns)
τ is the ramp compensation time constant of the design based on the switching frequency and duty cycle, (in
this design, 25.9 µs, refer to Table 39)
LOUT is the output inductance (in the design, 0.33 µH)
VREF is the user-selected reference voltage level (in this design, 1 V)
VOUT is the output voltage (in this design, 1 V)
(7)
The minimum output capacitance calculated from Equation 7 is 40 µF. The stability is ensured when the amount
of the output capacitance is 40 µF or greater. And when all MLCCs (multi-layer ceramic capacitors) are used,
both DC- and AC-derating effects must be considered to ensure that the minimum output capacitance
requirement is met with sufficient margin.
8.2.3.4.2 Response to a Load Transient
The output capacitance must supply the load with the required current when current is not immediately provided
by the regulator. When the output capacitor supplies load current, the impedance of the capacitor greatly affects
the magnitude of voltage deviation (such as undershoot and overshoot) during the transient.
Use Equation 8 and Equation 9 to estimate the amount of capacitance needed for a given dynamic load step and
release.
NOTE
There are other factors that can impact the amount of output capacitance for a specific
design, such as ripple and stability.
§V
ut
u ¨ OUT SW
¨ VIN min
©
§ § VIN min VOUT ·
¸ u t SW
u ¨¨
¸
¨¨
VIN min
¹
©©
LOUT u 'ILOAD max
COUT min_ under
2 u 'VLOAD insert
2
·
tOFF min ¸
¸
¹
·
tOFF min ¸ u VOUT
¸
¹
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2
COUT min_ over
LOUT u 'ILOAD max
2 u 'VLOAD release u VOUT
where
•
•
•
•
•
•
•
•
•
•
COUT(min_under) is the minimum output capacitance to meet the undershoot requirement
COUT(min_over)is the minimum output capacitance to meet the overshoot requirement
L is the output inductance value (0.33 µH)
∆ILOAD(max) is the maximum transient step (15 A)
VOUT is the output voltage value (1 V)
tSW is the switching period (1.54 µs)
VIN(min) is the minimum input voltage for the design (10.8 V)
tOFF(min) is the minimum off time of the device (300 ns)
∆VLOAD(insert) is the undershoot requirement (30 mV)
∆VLOAD(release) is the overshoot requirement (30 mV)
(9)
Most of the above parameters can be found in Table 38.
The minimum output capacitance to meet the undershoot requirement is 516 µF. The minimum output
capacitance to meet the overshoot requirement is 1238 µF. This example uses a combination of POSCAP and
MLCC capacitors to meet the overshoot requirement.
• POSCAP bank 1: 2 x 470 µF, 2.5 V, 6 mΩ per capacitor
• MLCC bank 2: 7 × 100 µF, 2.5 V, 1 mΩ per capacitor with DC+AC derating factor of 60%
Recalculating the worst case overshoot using the described capacitor bank design, the overshoot is 29.0 mV
which meets the 30-mV overshoot specification requirement.
8.2.3.4.3 Output Voltage Ripple
The output voltage ripple is another important design consideration. Equation 10 calculates the minimum output
capacitance required to meet the output voltage ripple specification. This criterion is the requirement when the
impedance of the output capacitance is dominated by ESR.
IRIPPLE
COUT min RIPPLE
82 PF
8 u fSW u VOUT ripple
(10)
In this case, the maximum output voltage ripple is 10 mV. For this requirement, the minimum capacitance for
ripple requirement yields 82 µF. Because this capacitance value is significantly lower compared to that of
transient requirement, determine the capacitance bank from steps in the previous section Response to a Load
Transient. Because the output capacitor bank consists of both POSCAP and MLCC type capacitors, it is
important to consider the ripple effect at the switching frequency due to effective ESR. Use Equation 11 to
determine the maximum ESR of the output capacitor bank for the switching frequency.
IRIPPLE
VOUT ripple
8 u fSW u COUT
ESRMAX
2.2 m:
IRIPPLE
(11)
Estimate the effective ESR at the switching frequency by obtaining the impedance vs frequency characteristics of
the output capacitors. The parallel impedance of capacitor bank 1 and capacitor bank 2 at the switching
frequency of the design example is estimated to be 1.2 mΩ, which is less than that of the maximum ESR value.
Therefore, the output voltage ripple requirement (10 mV) can be met. For detailed calculation on the effective
ESR please contact the factory to obtain a user-friendly Excel based design tool.
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8.2.3.5 Input Capacitor Selection
The TPS549B22 devices require a high-quality, ceramic, type X5R or X7R, input decoupling capacitor with a
value of at least 1 μF of effective capacitance on the VDD pin, relative to AGND. The power stage input
decoupling capacitance (effective capacitance at the PVIN and PGND pins) must be sufficient to supply the high
switching currents demanded when the high-side MOSFET switches on, while providing minimal input voltage
ripple as a result. This effective capacitance includes any DC bias effects. The voltage rating of the input
capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating
greater than the maximum input current ripple to the device during full load. The input ripple current can be
calculated using Equation 12.
ICIN rms
IOUT max u
VIN min VOUT
VOUT
u
VIN min
VIN min
10 Arms
(12)
The minimum input capacitance and ESR values for a given input voltage ripple specification, VIN(ripple), are
shown in Equation 13 and Equation 14. The input ripple is composed of a capacitive portion, VRIPPLE(cap), and a
resistive portion, VRIPPLE(esr).
IOUT max u VOUT
CIN min
21.4 PF
VRIPPLE cap u VIN max u fSW
(13)
ESRCIN max
VRIPPLE ESR
IOUT max
§ IRIPPLE ·
¨ 2 ¸
©
¹
3.4 m:
(14)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with the DC bias taken into account. For this example design, a ceramic capacitor with at
least a 25-V voltage rating is required to support the maximum input voltage. For this design, allow 0.1-V input
ripple for VRIPPLE(cap), and 0.1-V input ripple for VRIPPLE(esr). Using Equation 13 and Equation 14, the minimum
input capacitance for this design is 21.4 µF, and the maximum ESR is 3.4 mΩ. For this example, four 22-μF, 25V ceramic capacitors and one additional 100-μF, 25-V low-ESR polymer capacitors in parallel were selected for
the power stage.
8.2.3.6 Bootstrap Capacitor Selection
A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper
operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with a
voltage rating of 25 V or higher.
8.2.3.7 BP Pin
Bypass the BP pin to DRGND with 4.7 µF of capacitance. In order for the regulator to function properly, it is
important that these capacitors be localized to the TPS549B22 , with low-impedance return paths. See Layout
Guidelines for more information.
8.2.3.8 R-C Snubber and VIN Pin High-Frequency Bypass
Though it is possible to operate the TPS549B22 within absolute maximum ratings without ringing reduction
techniques, some designs may require external components to further reduce ringing levels. This example uses
two approaches: a high frequency power stage bypass capacitor on the VIN pins, and an R-C snubber between
the SW area and GND.
The high-frequency VIN bypass capacitor is a lossless ringing reduction technique which helps minimizes the
outboard parasitic inductances in the power stage, which store energy during the low-side MOSFET on-time, and
discharge once the high-side MOSFET is turned on. For this example two 2.2-nF, 25-V, 0603-sized highfrequency capacitors are used. The placement of these capacitors is critical to its effectiveness. Their ideal
placement is shown in Figure 53.
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Additionally, an R-C snubber circuit is added to this example. To balance efficiency and spike levels, a 1-nF
capacitor and a 1-Ω resistor are chosen. In this example a 0805-sized resistor is chosen, which is rated for 0.125
W, nearly twice the estimated power dissipation. See Snubber Circuits: Theory, Design and Application for more
information about snubber circuits.
8.2.3.9 Optimize Reference Voltage (VSEL)
Optimize the reference voltage by choosing a value for RVSEL. The TPS549B22 device is designed with a wide
range of precision reference voltage support from 0.6 V to 1.2 V with an available step change of 50 mV.
Program these reference voltages using the VSEL pin-strap configurations. See Table 2 for internal reference
voltage selections. In addition to providing initial boot voltage value, use the VSEL pin to program hiccup and
latch-off mode.
There are two ways to program the output voltage set point. If the output voltage set point is one of the 16
available reference and boot voltage options, no feedback resistors are required for output voltage programming.
In the case where feedback resistors are not needed, connect the RSP pin to the positive sensing point of the
load. Always connect the RSN pin to the load return sensing point.
In this design example, since the output voltage set point is 1 V, select RVSEL(LS) of either 75 kΩ (latch off) or 68.1
kΩ (hiccup) as shown in Table 3. If the output voltage set point is NOT one of the 16 available reference or boot
voltage options, feedback resistors are required for output voltage programming. Connect the RSP pin to the
mid-point of the resistor divider. Always connect the RSN pin to the load return sensing point as shown in Figure
23 and Figure 24.
The general guideline to select boot and internal reference voltage is to select the reference voltage closest to
the output voltage set point. In addition, because the RSP and RSN pins are extremely high-impedance input
terminals of the true differential remote sense amplifier, use a feedback resistor divider with values much less
than 100 kΩ.
8.2.3.10 MODE Pin Selection
MODE pin strap configuration is used to program control topology and internal soft-start timing selections.
TPS549B22 supports both DCAP3 and DCAP operation. For general POL applications, TI strongly recommends
configuring the control topology to be DCAP3 due to its simple to use and no external compensation features. In
the rare instance where DCAP is needed, an RCC network across the output inductor is needed to generate
sufficient ripple voltage on the RSP pin. In this design example, RMODE(LS) of 42.2 kΩ is selected for DCAP3 and
soft start time of 1 ms.
8.2.3.11 ADDR Pin Selection
ADDR pin strap configuration is used to program device address and light load conduction mode selection. The
TPS549B22 allows up to 16 different chip addresses for PMBus communication with the first 3 bits fixed as 001.
The address selection process is defined by resistor divider ratio from BP pin to ADDR pin, and the address
detection circuit will start to work only after the initial power up when VDD has risen above its UVLO threshold.
For this application example, a device address of 16d is desired. We select the low side RADDR to be 0 Ω
considering the SKIP operation and device address of 16d. Table 4 lists all combinations of the address
selections. The 1% or better tolerance resistors with typical temperature coefficient of ±100 ppm/°C are
recommended
8.2.3.12 Overcurrent Limit Design
The TPS549B22 device uses the ILIM pin to set the OCP level. Connect the ILIM pin to GND through the voltage
setting resistor, RILIM. In order to provide both good accuracy and cost effective solution, this device supports
temperature compensated MOSFET on-resistance (RDS(on)) sensing. Also, this device performs both positive and
negative inductor current limiting with the same magnitudes. Positive current limit is normally used to protect the
inductor from saturation therefore causing damage to the high-side and low-side FETs. Negative current limit is
used to protect the low-side FET during OVP discharge.
The inductor current is monitored by the voltage between PGND pin and SW pin during the OFF time. The ILIM
pin has 1200 ppm/°C temperature slope to compensate the temperature dependency of the on-resistance. The
PGND pin is used as the positive current sensing node.
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TPS549B22 has cycle-by-cycle over-current limiting control. The inductor current is monitored during the OFF
state and the controller maintains the OFF state during the period that the inductor current is larger than the
overcurrent ILIM level. The voltage on the ILIM pin (VILIM) sets the valley level of the inductor current. The range
of value of the RILIM resistor is between 9.53 kΩ and 105 kΩ. The range of valley OCL is between 5 A and 50 A
(typical). If the RILIM resistance is outside of the recommended range, OCL accuracy and function cannot be
ensured. (see Table 40)
Table 40. Closed Loop EVM Measurement of OCP Settings
1% RILIM
(kΩ)
OVERCURRENT PROTECTION VALLEY (A)
82.1
40
71.5
35
61.9
30
51.1
25
40.2
20
30.1
15
20.5
10
Use Equation 15 to relate the valley OCL to the RILIM resistance.
RILIM = 2.0664 × OCLVALLEY – 0.6036
where
•
•
RILIM is in kΩ
OCLVALLEY is in A
(15)
In this design example, the desired valley OCL is 43 A, the calculated RILIM is 61.9 kΩ. Use Equation 16 to
calculate the DC OCL to be 32.1 A.
OCLDC OCL VALLEY 0.5 u IRIPPLE
where
•
•
RILIM is in kΩ
OCLDC is in A
(16)
In an overcurrent condition, the current to the load exceeds the inductor current and the output voltage falls.
When the output voltage crosses the under-voltage fault threshold for at least 1 ms, the behavior of the device
depends on the VSEL pin strap setting. If hiccup mode is selected, the device restarts after a 16-ms delay (1-ms
soft-start option). If the overcurrent condition persists, the OC hiccup behavior repeats. During latch-off mode
operation the device shuts down until the EN pin is toggled or VDD pin is power cycled.
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Figure 54. VOUT Command Graphic User Interface
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Application Curves
Output Voltage Regulation (V)
1.01
1.005
1
0.995
VIN = 5 V
VIN = 12 V
VIN = 14 V
VIN = 18 V
0.99
0
5
VDD = VIN
VOUT = 1 V
10
15
Output Current (A)
fSW = 650 kHz
20
25
D009
SKIP Mode
5-A DC with 15-A
step at 40A/µs
VOUT = 1 V
Figure 55. Output Voltage Regulation vs. Output Current
VIN = 12 V
IOUT = 0 A
VOUT = 0.6 V to 1.2 V
FCCM mode
Figure 56. Transient Response Peak-to-Peak
VIN = 12 V
IOUT = 0 A
Figure 57. VOUT Command
VIN = 12 V
IOUT = 40 A
fSW = 650 kHz
VDD = VIN = 5 V
VOUT = 1.2 V to 0.6 V
Figure 58. VOUT Command
VOUT = 0.6 V to 1.2 V
VIN = 12 V
IOUT = 40 A
Figure 59. VOUT Command
VOUT = 1.2 V to 0.6 V
Figure 60. VOUT Command
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9 Power Supply Recommendations
This device is designed to operate from an input voltage supply between 1.5 V and 18 V. Ensure the supply is
well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise performance,
as is the quality of the PCB layout and grounding scheme. See the recommendations in the Layout section.
10 Layout
10.1 Layout Guidelines
Consider these layout guidelines before starting a layout work using TPS549B22.
• It is absolutely critical that all GND pins, including AGND (pin 30), DRGND (pin 29), and PGND (pins 13, 14,
15, 16, 17, 18, 19, and 20) are connected directly to the thermal pad underneath the device via traces or
plane.
• Include as many thermal vias as possible to support a 25-A thermal operation. For example, a total of 35
thermal vias are used (outer diameter of 20 mil) in the TPS49B22EVM-847, which is available for purchase at
www.ti.com.
• Placed the power components (including input/output capacitors, output inductor and TPS549B22 device) on
one side of the PCB (solder side). Insert at least two inner layers (or planes) connected to the power ground,
in order to shield and isolate the small signal traces from noisy power lines.
• Place the VIN pin decoupling capacitors as close as possible to the PVIN and PGND pins to minimize the
input AC current loop. Place a high-frequency decoupling capacitor (with a value between 1 nF and 0.1 µF)
as close to the PVIN pin and PGND pin as the spacing rule allows. This placement helps suppress the switch
node ringing.
• Place VDD and BP decoupling capacitors as close as possible to the device pins. Do not use PVIN plane
connection for the VDD pin. Separate the VDD signal from the PVIN signal by using separate trace
connections. Provide GND vias for each decoupling capacitor and make the loop as small as possible.
• Ensure that the PCB trace defined as switch node (which connects the SW pins and up-stream of the output
inductor) are as short and wide as possible. In the TPS49B22EVM-847 design, the SW trace width is 200 mil.
Use a separate via or trace to connect SW node to snubber and bootstrap capacitor. Do not combine these
connections.
• Place all sensitive analog traces and components (including VOSNS, RSP, RSN, ILIM, MODE, VSEL and
ADDR) far away from any high voltage switch node (itself and others), such as SW and BOOT to avoid noise
coupling. In addition, place MODE, VSEL and ADDR programming resistors near the device pins.
• The RSP and RSN pins operate as inputs to a differential remote sense amplifier that operates with very high
impedance. It is essential to route the RSP and RSN pins as a pair of diff-traces in Kelvin-sense fashion.
Route them directly to either the load sense points (+ and –) or the output bulk capacitors. The internal circuit
uses the VOSNS pin for on-time adjustment. It is critical to tie the VOSNS pin directly tied to VOUT (load
sense point) for accurate output voltage result.
• Pins 6, 7, and 26 are not connected in the 25-A TPS549B22 device, while pins 6, and 7 connect to SW and
pins 26 connects to PVIN in the 40-A TPS549D22 device.
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10.2 Layout Examples
Figure 61. EVM Top View
Figure 62. EVM Top Layer
Figure 63. EVM Inner Layer 1
Figure 64. EVM Inner Layer 2
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Layout Examples (continued)
Figure 65. EVM Inner Layer 3
Figure 66. EVM Inner Layer 4
Figure 67. EVM Bottom Layer
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10.3 Mounting and Thermal Profile Recommendation
Proper mounting technique adequately covers the exposed thermal tab with solder. Excessive heat during the
reflow process can affect electrical performance. Figure 68 shows the recommended reflow oven thermal profile.
Proper post-assembly cleaning is also critical to device performance. See
QFN/SON PCB Attachment for more information.
tP
Temperature (°C)
TP
TL
TS(max)
tL
TS(min)
rRAMP(up)
tS
rRAMP(down)
t25P
25
Time (s)
Figure 68. Recommended Reflow Oven Thermal Profile
Table 41. Recommended Thermal Profile Parameters
PARAMETER
MIN
TYP
MAX
UNIT
RAMP UP AND RAMP DOWN
rRAMP(up)
Average ramp-up rate, TS(max) to TP
3
°C/s
rRAMP(down)
Average ramp-down rate, TP to TS(max)
6
°C/s
PRE-HEAT
TS
Pre-heat temperature
tS
Pre-heat time, TS(min) to TS(max)
150
200
°C
60
180
s
REFLOW
TL
Liquids temperature
TP
Peak temperature
217
tL
Time maintained above liquidus temperature, TL
tP
Time maintained within 5°C of peak temperature, TP
t25P
Total time from 25°C to peak temperature, TP
°C
260
°C
60
150
s
20
40
s
480
s
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS549B22 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Snubber Circuits: Theory, Design and Application
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
D-CAP3, Eco-mode, NexFET, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
PMBus is a trademark of SMIF, Inc..
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
58
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TPS549B22
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SNVSAU8 – JUNE 2017
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TPS549B22
59
TPS549B22
SNVSAU8 – JUNE 2017
www.ti.com
PACKAGE OUTLINE
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
8X
B
4.0
3.8
NOTE 4
0.51
0.31
0.1
C A
1.7 MAX
B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.1
2.5
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.6
2.0
TYPICAL
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
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SNVSAU8 – JUNE 2017
EXAMPLE BOARD LAYOUT
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
SYMM
(1.3)
TYP
(3.1)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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61
TPS549B22
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www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
TPS549B22RVFR
ACTIVE
LQFN-CLIP
RVF
40
2500
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
(549B22, 549B22A1)
TPS549B22RVFT
ACTIVE
LQFN-CLIP
RVF
40
250
RoHS-Exempt
& Green
NIPDAU | SN
Level-2-260C-1 YEAR
-40 to 125
(549B22, 549B22A1)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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