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TPS55010
SLVSAV0B – APRIL 2011 – REVISED OCTOBER 2014
TPS55010 2.95-V To 6-V Input, 2 W, Isolated DC/DC Converter with Integrated FETs
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The TPS55010 is a transformer driver designed to
provide isolated power for isolated interfaces, such as
RS-485 and RS-232, from 3.3 V or 5 V input supply.
1
Isolated Fly-Buck™ Topology
Primary Side Feedback
100 kHz to 2000 kHz Switching Frequency
Synchronizes to External Clock
Adjustable Slow Start
Adjustable Input Voltage UVLO
Open Drain Fault Output
Cycle-by-Cycle Current Limit
Thermal Shutdown Protection
3 mm x 3 mm 16 Pin QFN Package
The device uses fixed frequency current mode control
and half bridge power stage with primary side
feedback to regulate the output voltage for power
levels up to 2W. The switching frequency is
adjustable from 100 kHz to 2000 kHz so solution size,
efficiency and noise can be optimized. The switching
frequency is set with a resistor or is synchronized to
external clock using the RT/CLK pin. To minimize
inrush currents, a small capacitor can be connected
to the SS pin. The EN pin can be used as an enable
pin or to increase the default input UVLO voltage
from 2.6V.
2 Applications
•
•
•
•
•
Noise Immunity in PLCs, Data Acquisition and
Measurement Equipment
Isolated RS-232 and RS-485 Communication
Channels
Powers Line Drivers, ISO Amplifiers, Sensors,
CAN Transceivers
Floating Supplies for IGBT Gate Drivers
Promotes Safety in Medical Equipment
With the same transformer the TPS55010 can
provide a solution for different input and output
voltage combinations by adjusting the primary side
voltage. Off the shelf transformers are available to
provide single positive, or dual positive and negative
output voltages.
The TPS55010 is available in a 3mm x 3mm 16 pin
QFN package with thermal pad.
(1)
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS55010
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at he
end of the datasheet.
4 Simplified Schematic
Efficiency vs Load Current
3V
to
5.5 V
100
90
CIN
BOOT
TPS55010
Cboot
T1
1:2.5
PH
Css
Rt
RC
EN
FAULT
SS
VSENSE
RT/CLK
COMP
GND
CC
CO
RHS
80
5V
200mA
+
VO
_
Efficiency (%)
VIN
70
60
50
40
30
CPRI
RLS
VOUT = 5V
FSW = 350kHz
20
10
0
0.00
VIN = 5V
0.05
0.10
0.15
0.20
Output Current (A)
0.25
0.30
G040
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS55010
SLVSAV0B – APRIL 2011 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
5
5
6
6
7
Absolute Maximum Ratings .....................................
Handling Rating.........................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
9
Application And Implementation........................ 17
9.1 Application Information............................................ 17
9.2 Typical Applications ................................................ 17
9.3 Typical Application, Dual Output............................. 29
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2011) to Revision B
Page
•
Changed Added the Device information table, Handling Ratings table, Applications and Implementation section,
Layout section, and the Device and Documentation Support section.................................................................................... 1
•
Added the Handling Rating table............................................................................................................................................ 4
•
Added the Recommended Operating Conditions table .......................................................................................................... 4
•
Added Figure 23 ................................................................................................................................................................... 23
•
Added Figure 24 .................................................................................................................................................................. 24
•
Changed Figure 26 through Figure 28 ................................................................................................................................ 26
•
Changed Figure 40 .............................................................................................................................................................. 27
•
Changed Figure 42 through Figure 44 ................................................................................................................................ 34
•
Changed Figure 54 .............................................................................................................................................................. 35
Changes from Original (April 2010) to Revision A
•
2
Page
Changed the device status From: Product Preview To: Production....................................................................................... 1
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6 Pin Configuration and Functions
VIN
EN
FAULT
BOOT
RTE PACKAGE
(TOP VIEW)
16
15
14
13
VIN 1
VIN 2
5
6
7
8
RT/CLK
4
COMP
GND
VSENSE
3
GND
GND
Thermal
Pad
(17)
12
PH
11
PH
10
PH
9
SS
Pin Functions
Name
Number
Description
VIN
1, 2, 16
Supplies the control circuitry and switches of the power converter.
GND
3, 4, 5
Power Ground. This pin should be electrically connected directly to the thermal pad under the IC.
VSENSE
6
Inverting node of the transconductance error amplifier.
COMP
7
Error amplifier output, and input to the output switch current comparator. Connect frequency
compensation components to this pin.
RT/CLK
8
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when
using an external resistor to ground to set the switching frequency. If the pin is pulled above the
PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The
internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If
clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set
function.
SS
9
Slow-start. An external capacitor connected to this pin sets the output rise time.
PH
10, 11, 12
The source of the internal high side power MOSFET, and drain of the internal low side MOSFET.
BOOT
13
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below
the minimum required by the output device, the output is forced to switch off until the capacitor is
refreshed.
FAULT
14
An open drain output. Active low if the output voltage is low due to thermal shutdown, dropout,
overvoltage or EN shut down.
EN
15
Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the
input undervoltage lockout with two resistors.
THERMAL PAD
17
GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad
should be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
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SLVSAV0B – APRIL 2011 – REVISED OCTOBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
–0.3
7
V
EN
–0.3
BOOT
Voltage
V
–0.3
3
V
COMP
–0.3
3
V
FAULT
–0.3
7
V
SS
–0.3
3
V
RT/CLK
–0.3
6
V
BOOT-PH
–0.3
7
V
PH
–0.6
7
V
–2
10
V
EN
100
µA
RT/CLK
100
µA
COMP
100
uA
FAULT
10
mA
SS
100
µA
150
°C
Operating Junction Temperature
(1)
V
VSENSE
PH, 10ns Transient
Current
3.6
PH + 7
–40
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under ELECTRICAL
SPECIFICATIONS is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Rating
over operating free-air temperature range (unless otherwise noted)
Tstg
Storage Temperature
V(ESD)
(1)
(2)
Electrostatic Discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins (1)
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
MIN
MAX
UNIT
–65
150
°C
–2
2
kV
–500
500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VI
Input voltage
PO
Output power
4
2.98
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NOM
MAX
UNIT
6
V
2
W
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7.4 Thermal Information
THERMAL METRIC (1)
TPS55010
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
55.5
θJB
Junction-to-board thermal resistance
24.9
ψJT
Junction-to-top characterization parameter
1.0
ψJB
Junction-to-board characterization parameter
24.9
θJCbot
Junction-to-case (bottom) thermal resistance
9.9
(1)
UNIT
RTE (16 PINS)
60
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
TJ = –40°C TO 150°C, VIN = 2.95V TO 6V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
Operating input voltage
VIN
2.95
Shutdown current
EN = 0V, 25°C
Operating current
VSENSE = 0.9V, 25°C
TYP
MAX
UNIT
SUPPLY VOLTAGE
Internal undervoltage lockout
6
V
2
5
µA
360
575
µA
2.6
2.9
V
1.25
1.37
V
ENABLE
Enable threshold
Input current
rising
falling
1.15
1.18
Threshold - 50mV
–1.2
Threshold + 50mV
–4.6
Hysteresis
µA
µA
3.4
VOLTAGE REFERENCE
Reference
3V < VIN < 6V
0.804
0.829
0.854
V
MOSFET
High side switch resistance
BOOT- PH = 5 V
45
81
mΩ
Low side switch resistance
VIN = 5 V
45
81
mΩ
ERROR AMPLIFIER
Input current
50
nA
Error amp transconductance
-2 µA < I(COMP) < 2 µA
245
uS
Error amp dc gain
VSENSE = 0.8 V
500
V/V
3
MHz
Error amp source/sink
V(COMP) = 1V, 100 mV overdrive
±16
µA
COMP to Iph gm
I(PH) = 0.5 A
7.5
A/V
Minimum unity gain Bandwidth
CURRENT LIMIT
High side sourcing current limit
VIN = 3 V
2
2.75
A
Low Side Sinking Current Limit
VIN = 3 V
–3
–4.5
A
171
°C
12
°C
THERMAL SHUTDOWN
Thermal Shutdown
OT Hysteresis
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Electrical Characteristics (continued)
TJ = –40°C TO 150°C, VIN = 2.95V TO 6V (unless otherwise noted)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
RT/CLK
RT/CLK voltage
R(RT/CLK) = 195 kΩ
0.5
RT/CLK high threshold
1.6
RT/CLK low threshold
0.4
V
2.2
V
0.6
V
2.5
V
BOOT
Boot UVLO
SS Slow Start
Charge current
V(SS) = 0.4 V
SS to VSENSE matching
V(SS) = 0.4 V
0.5
35
mV
SS to reference Crossover
98% reference
1.1
V
SS discharge current (overload)
VSENSE = 0 V
325
µA
SS discharge voltage
VSENSE = 0V
46
mV
SS discharge current (UVLO, EN, thermal fault)
V(SS) = 0.5 V
1.2
mA
100
µs
VSENSE falling
91
% VREF
VSENSE rising
108
% VREF
VIN UVLO to SS start time
2.2
4
µA
FAULT Pin
VSENSE threshold
Output high leakage
VSENSE = VREF, V(FAULT) = 5.5 V
Output low
I(FAULT) = 3 mA
Minimum VIN for valid output
V(FAULT) < 0.5 V at 100 µA
2
nA
0.3
V
1.6
V
7.6 Timing Requirements
MIN
TYP
MAX
UNIT
RT/CLK
Minimum CLK pulse width
75
ns
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PH
ton
Minimum on time
Measured at 10% to 10% of VIN
130
toff
Minimum off time
V(BOOT-PH) ≥ 3 V
0%
ns
RT/CLK
Switching frequency using CLK mode
300
2000
kHz
Switching frequency using RT mode
100
2000
kHz
600
kHz
Switching Frequency
R(RT/CLK) = 195 kΩ
400
500
PLL lock in time
50
µs
RT/CLK falling edge to PH rising edge
delay
90
ns
100
µs
SS Slow Start
VIN UVLO to SS start time
6
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7.8 Typical Characteristics
90
500
VIN = 5V
RT = 200kΩ
Oscillator Frequency (kHz)
On Resistance (mΩ)
80
70
60
50
40
30
High Side VIN = 5V
Low Side VIN = 5V
High Side VIN = 3.3V
Low Side VIN = 3.3V
20
10
0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
475
450
425
400
−50
150
Figure 1. High Side and Low Side RDS(on)
vs Temperature
25
50
75
100
Junction Temperature (°C)
125
150
G002
−4.0
VIN = 5V
VIN = 3.3V
VIN = 3.3V
VIN = 5V
−4.2
Current Limit Threshold (A)
3.4
Current Limit Threshold (A)
0
Figure 2. Frequency vs Temperature
3.5
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
−4.4
−4.6
−4.8
−5.0
−5.2
−5.4
−5.6
−5.8
2.5
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
−6.0
−50
150
−25
0
G003
Figure 3. High Side Current Limit (Sourcing) vs
Junction Temperature
25
50
75
100
Junction Temperature (°C)
150
G004
1.240
VIN = 5V
1.235
250
VENA− Enable (V)
1.230
200
150
100
1.225
1.220
Rising
Falling
1.215
1.210
1.205
1.200
1.195
50
1.190
0
−50
125
Figure 4. Low Side Current Limit (Sinking) vs
Junction Temperature
300
Transconductance (µA)
−25
G001
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
1.185
−50
G005
Figure 5. Error Amplifier Transconductance vs Temperature
VIN = 5V
−25
0
25
50
75
100
Junction Temperature (°C)
125
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G006
Figure 6. EN Pin Voltage vs Temperature
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Typical Characteristics (continued)
−0.1
−3.24
VIN = 5V
VIN = 5V
−3.26
−0.3
ENA− Enable Hyst (µA)
ENA− Enable Current (µA)
−0.2
−0.4
−0.5
−0.6
−0.7
−0.8
−3.28
−3.30
−3.32
−3.34
−3.36
−3.38
−0.9
−1.0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
−3.40
−50
150
−25
Figure 7. EN Pin Pullup
vs Temperature (VEN = Threshold -50 mV)
150
G008
−2.3
2.70
Input Voltage (V)
−2.2
−2.4
−2.5
−2.6
−2.7
2.68
2.64
2.62
2.60
2.58
−2.9
2.56
0
25
50
75
100
Junction Temperature (°C)
125
VIN = 5V
2.66
−2.8
−25
Rising
Falling
2.74
2.72
−3.0
−50
2.54
−50
150
−25
0
G009
Figure 9. SS Charge Current vs Temperature
25
50
75
100
Junction Temperature (°C)
150
G010
400
EN = 0V
EN = Open
VSENSE = 0.9V
380
Supply Current (µA)
2.0
1.5
1.0
0.5
360
340
320
VIN = 5V
VIN = 3.3V
0.0
−50
125
Figure 10. Input Start and Stop Voltage vs Temperature
2.5
−25
0
25
50
75
100
Junction Temperature (°C)
125
VIN = 5V
VIN = 3.3V
150
300
−50
G011
Figure 11. Shutdown Supply Current vs Temperature
8
125
2.76
VIN = 5V
−2.1
SS Current (µA)
25
50
75
100
Junction Temperature (°C)
Figure 8. EN Pin Hysteresis Current
vs Temperature
−2.0
Shutdown Current (µA)
0
G007
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G012
Figure 12. VIN Supply Current vs Temperature
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Typical Characteristics (continued)
110
0.834
VIN = 5V
Fault Threshold (% VREF)
Voltage Reference (V)
0.833
0.832
0.831
0.830
0.829
0.828
0.827
0.826
105
100
VIN = 5V
95
90
85
VSENSE Rising
VSENSE Falling
0.825
0.824
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
80
−50
150
Figure 13. Voltage Reference vs Temperature
0
25
50
75
100
Junction Temperature (°C)
125
150
G014
Figure 14. Fault Threshold vs Temperature
160
36
VIN = 5V
VIN = 5V
SS to VSENSE Offset (mV)
140
On Resistance (Ω)
−25
G013
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
35
34
33
32
31
30
−50
G015
Figure 15. Fault On-Resistance vs Temperature
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G016
Figure 16. SS to VSENSE Offset vs Temperature
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8 Detailed Description
8.1 Overview
The TPS55010 is a half bridge transformer driver designed to implement a high efficiency, low power isolated
supply. The primary side feedback implemented using two resistors and a primary side capacitor provides
excellent regulation over line and load compared to an open loop push pull converter.
The half bridge power stage consists of two integrated n-channel MOSFETs with 45 mΩ on resistance. The drive
voltage for the integrated high side MOSFET is supplied by a capacitor between the BOOT and PH pins. The
switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase
lock loop (PLL) on the RT/CLK pin that is used to synchronize the high side power switch turn on to a falling
edge of an external system clock. The wide switching frequency of 100 kHz to 2000 kHz (300kHz to 2000kHz in
CLK mode) allows for efficiency, size optimization or noise avoidance when selecting the switching frequency.
The TPS55010 has a typical default start up voltage of 2.6 V. The EN pin has an internal pull-up current source
that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition,
the pull up current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS55010 is typically 360 µA when not switching and under no load. When the device
is disabled, the supply current is less than 5 µA. The slow start (SS) pin is used to minimize inrush currents
during start up.
8.2 Functional Block Diagram
FAULT
EN
VIN
Shutdown
91%
Enable
Comparator
Logic
Thermal
Shutdown
UVLO
Shutdown
Shutdown
Logic
Enable
Threshold
108%
Boot
Charge
Voltage
Reference
VSENSE
Minimum
Clamp
Pulse
Skip
ERROR
AMPLIFIER
Boot
UVLO
PWM
Comparator
Current
Sense
BOOT
PWM
Latch
R
SS
Q
Logic
S
Shutdown
Logic
S
COMP
Slope
Compensation
PH
Current
Limit
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
RT/CLK
10
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GND
THERMAL
PAD
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8.3 Feature Description
8.3.1 Fixed Frequency PWM Control
The TPS55010 uses an adjustable fixed frequency, peak current mode control. The primary voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the high side power switch is turned off and the low side power switch is turned on. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level. The TPS55010 adds a compensating ramp to the switch
current signal. This slope compensation prevents sub-harmonic oscillations as duty cycle increases.
8.3.2 Half Bridge and Bootstrap Voltage
The TPS55010 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric and a voltage rating of 10 V or higher is
recommended because of the stable characteristics over temperature and voltage.
8.3.3 Error Amplifier
The TPS55010 uses a transconductance error amplifier. The amplifier compares the VSENSE voltage to the
lower of the SS pin voltage or the internal 0.829 V voltage reference. The transconductance of the error amplifier
is 245 µA/V. The frequency compensation components are placed between the COMP pin and ground.
8.3.4 Voltage Reference
The voltage reference system produces a precise ±3.0% voltage reference over temperature by scaling the
output of a temperature-stable band gap circuit. The band gap and scaling circuits produce 0.829 V at the noninverting input of the error amplifier.
8.3.5 Adjusting the Output Voltage
The primary side voltage is set with a resistor divider from the primary side capacitor to the VSENSE pin. It is
recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the RLS resistor and use
Equation 1 to calculate RHS. The output voltage is a function of the primary voltage, transformer turns ratio and
forward voltage of the diode.
æV
- 0.829V ö÷
÷÷
RHS = RLS × ççç PRI
çè
0.829V
ø÷
(1)
spacer
N
VOUT = VPRI × SEC - Vfd
NPRI
(2)
spacer
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Feature Description (continued)
VIN
Npri:Nsec
PH
VFD
VO
CO
TPS55010
VSENSE
-
RHS
+
0.829V
VPRI
RLS
GND
CPRI
Figure 17. Setting the Output Voltage
8.3.6 Enable and Adjusting Undervoltage Lockout
The TPS55010 is disabled when the VIN pin voltage falls below 2.6 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 18 to adjust the input voltage UVLO by using
two external resistors. The EN pin has an internal pull-up current source of 1.2 µA that provides the default
condition of the TPS55010 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an
additional 3.4 µA of hysteresis is added. When the EN pin is pulled below 1.18 V, the hysteresis current is
removed.
TPS55010
VIN
I1
Ihys
RUVLO1
EN
RUVLO2
VENA
Figure 18. Adjustable Under Voltage Lock Out
RUVLO1 =
æ
ö
çç VENfalling ÷÷
÷÷ - V
VSTART çç
STOP
÷
çV
çè ENrising ø÷÷
æ V
ö
ç
ENfalling ÷÷
I1 × çç1÷÷ + IHYS
çç V
÷
ENrising ø÷
è
(3)
spacer
RUVLO2 =
12
RUVLO1 × VENfalling
VSTOP - VENfalling + RUVLO1 × (I1 + IHYS )
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Feature Description (continued)
8.3.7 Adjusting Slow Start Time
A capacitor on the SS pin to ground implements a slow start time to minimize inrush current during startup. The
TPS55010 regulates to the lower of the SS pin and the internal reference voltage. The TPS55010 has an internal
pull-up current source of 2.2 µA which charges the external slow start capacitor. Equation 5 calculates the
required slow start capacitor value where TSS is the desired slow start time in ms, Iss is the internal slow start
charging current of 2.2 µA, and VREF is the internal voltage reference of 0.829 V.
If during normal operation, the VIN goes below the UVLO, EN pin pulled below 1.18 V, or a thermal shutdown
event occurs, the TPS55010 stops switching. When the VIN goes above UVLO, EN is released or pulled high, or
a thermal shutdown is exited, then SS is discharged to below 40 mV before reinitiating a powering up sequence.
The VSENSE voltage will follow the SS pin voltage with a 35 mV offset up to 85% of the internal voltage
reference. When the SS voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS voltage to the internal voltage reference. If no slow start time
is needed, the SS pin can be left open. The slow start capacitor should be less than 0.47 µF.
CSS (nF) =
TSS (ms) × ISS (uA)
VREF (V)
(5)
8.3.8 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS55010 is adjustable over a wide range from 100 kHz to 2000 kHz by placing
a maximum of 1070 kΩ and minimum of 42.2 kΩ, respectively, on the RT/CLK pin. An internal amplifier holds this
pin at a fixed voltage when using an external resistor to ground to set the switching frequency. The RT/CLK is
typically 0.5 V. To determine the timing resistance for a given switching frequency, use Equation 6.
To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of
the efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum
controllable on time is typically 130 ns.
RT (kW) =
156000
fsw (kHz)1.0793
(6)
8.3.9 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in
Figure 19. The square wave amplitude must transition lower than 0.4V and higher than 2.2V on the RT/CLK pin
and have a high time greater than 75 ns. The synchronization frequency range is 300 kHz to 2000 kHz. The
rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal.
The external synchronization circuit should be designed in such a way that the device has the default frequency
set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is
recommended to use a frequency set resistor connected as shown in Figure 19 through another resistor (e.g 50
Ω) to ground for clock signal that are not Hi-Z or tri-state during the off state. The RT resistor value should set
the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization
signal through a 10 pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK
threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage source is
removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since
there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the
external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the external CLK frequency within 50 microseconds.
When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5V voltage and the resistor will then set the switching frequency.
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Feature Description (continued)
TPS55010
TPS55010
RT/CLK
RT/CLK
PLL
PLL
RT
Hi-Z
Clock
Source
Clock
Source
RT
Figure 19. Synchronizing to a System Clock
8.3.10 Overcurrent Protection
The TPS55010 implements a cycle by cycle current limit. During each switching cycle the high side switch
current is compared to the voltage on the COMP pin. When the instantaneous switch current intersects the
COMP voltage, the high side switch is turned off. During overcurrent conditions that pull the output voltage low,
the error amplifier responds by driving the COMP pin high, increasing the switch current. The error amplifier
output is clamped internally. This clamp functions as a switch current limit.
8.3.11 Reverse Overcurrent Protection
The TPS55010 implements low side current protection by detecting the voltage across the low side MOSFET.
When the converter sinks current through its low side FET, the control circuit turns off the low side MOSFET if
the reverse current is more than 4.5 A
8.3.12 FAULT Pin
The FAULT pin output is an open drain MOSFET. The output is pulled low when the VSENSE voltage is below
91% or rising above 108% of the nominal internal reference voltage. It is recommended to use a pull-up resistor
between the values of 1kΩ and 100kΩ to a voltage source that is 6 V or less. The FAULT pin is in a valid state
once the VIN input voltage is greater than 1.6 V. The FAULT pin is pulled low, if the input UVLO or thermal
shutdown is asserted, or the EN pin is pulled low.
8.3.13 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 171°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 159°C, the device reinitiates the power up sequence
by discharging the SS pin to below 40 mV. The thermal shutdown hysteresis is 12°C.
8.4 Device Functional Modes
8.4.1 Operation of the Fly-Buck™ Converter
Figure 20 shows a simplified schematic and the two primary operational states of the Fly-Buck converter. The
power supply is a variation of a Flyback converter and consists of a half bridge power stage SHS and SLS,
transformer, primary side capacitor, diode and output capacitor. The output voltage is regulated indirectly by
using the primary side capacitor voltage, VPRI, as feedback. The Fly-Buck is a portmanteau of flyback and buck
since the transformer is connected as a flyback converter and the input to output voltage relationship is similar to
a buck derived converter, assuming the converter is operating in steady state and the transformer has negligible
leakage inductance.
The CPRI and LPRI are charged by the input voltage source VIN during the time the high side switch SHS is on.
During this time, diode D1 is reversed biased and the load current is supplied by output capacitor CO.
14
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Device Functional Modes (continued)
During the off time of SHS, SLS conducts and the voltage on CPRI continues to increase during a portion of the SLS
conduction time. The voltage increase is due to the energy transfer from LPRI to CPRI. For the remaining portion of
the SLS conduction time, the CPRI voltage decreases because of current in LPRI reverses; see the ILPRI and VPRI
waveforms in Figure 21. By neglecting the diode voltage drop, conduction dead time and leakage inductance, the
input to output voltage conversion ratio can be derived as shown in Equation 7 from the flux balance in LPRI. It
can be seen in Equation 7 that the input to output relationship is the same as a buck-derived converter with
transformer isolation. The dc voltage VPRI on the primary side capacitor in Equation 8 has the same linear
relationship to the input voltage as a buck converter.
SHS
D1
T1
D1
T1
CIN
SLS
NPRI
NSEC
CO
_
+
SHS
VIN C
IN
NPRI
NSEC
CO
+
VPRI
_
VO
SHS
+
VPRI
_
CPRI
D x Ts
_
SLS
+
VO
D1
T1
CPRI
NPRI
CIN SLS
NSEC
CO
_
+
VPRI
_
+
VO
CPRI
(1 - D) x Ts
Figure 20. Output Voltage Conversion Ratio
VO
VIN
=
NSEC
×D
NPRI
(7)
spacer
VPRI
VIN
=D
(8)
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Device Functional Modes (continued)
SHS
SLS
ILpri_pospk
ILpri
Im_valley
ILpri_negpk
Vpri
ID1_pk
ID1
DTs
(1-D) x Ts
Figure 21. Simplified Voltage and Current Waveforms
16
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9 Application And Implementation
9.1 Application Information
The following design example illustrates how to determine the components for a single output isolated power
supply. TI offers an EVM (TPS55010EVM-009) with user guide (SLVU459) and excel calculator tool (SLVC363)
to expedite the design process. Additionally the PMP6813 and PMP6838 reference designs show the small
solution size possible with the TPS55010. The support material is available on the TPS55010 product folder at
www.ti.com.
9.2 Typical Applications
RC
CC
CHF
Figure 22. 5 V to 5 V Isolated Power Supply Schematic
Table 1. Reference Design for Common Applications
5 V to 5 V at 0.2 A
3.3 V to 5 V at 0.2 A
5 V to 3.3 V at 0.3 A
3.3 V to 3.3 V at 0.3 A
CIN
47 µF X5R 6.3V
100 µF X5R 6.3V
47 µF X5R 6.3V
100 µF X5R 6.3V
COUT
2 x 10 µF X5R 10V
47 µF X5R 6.3V
22 µF X5R 6.3V
47 µF X5R 6.3V
CPRI
47 µF X5R 10V
100 µF X5R 6.3V
100 µF X5R 6.3V
100 µF X5R 6.3V
CBOOT
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
CSS
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
0.1 µF X5R 10V
CCOMP
5.6 nF
3.9 nF
3.3 nF
3.9 nF
CHF
82 pF
68 pF
68 pF
100 pF
RCOMP
10.5 kΩ
16.9 kΩ
18.2 kΩ
17.4kΩ
RHS
16.5 kΩ
16.5 kΩ
8.25 kΩ
8.25 kΩ
RLS
10.0 kΩ
10.0 kΩ
10.0 kΩ
10.0 kΩ
RT
280 kΩ (350kHz)
332 kΩ (300kHz)
402 kΩ (250kHz)
511 kΩ (200kHz)
T1 (See the SLVU459 BOM)
750311880
750311880
750311880
750311880
D1
B120
B120
B120
B120
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9.2.1 Design Guide – Step-by-Step Design Procedure
Table 2. Design Parameters
PARAMETER
VALUE
Input Voltage
5 V nominal (4.5 V to 5.5 V)
Output Voltage
5V
Output Voltage Ripple
