TPS552882-Q1
ZHCSMV3A – DECEMBER 2020 – REVISED DECEMBER 2021
TPS552882-Q1 36V 16A 降压/升压转换器
1 特性
3 说明
• 符合 AEC-Q100 标准：
– 器件温度等级 1：–40°C 至 +125°C 环境工作
温度范围
• 宽输入和输出电压范围
– 宽输入电压范围：2.7V 至 36V
– 宽输出电压范围：0.8V 至 22V
• 在整个负载范围内具有高效率
– VIN = 12V、VOUT = 20V 且 IOUT = 3A 时效率为
97%
• 避免频率干扰和串扰
– 可选的时钟同步
– 可编程开关频率范围为 200kHz 至 2.2MHz
• 降低 EMI
– 可选可编程扩展频谱
– 无引线封装
• 丰富的保护特性
– 输出过压保护
– 利用断续模式实现输出短路保护
– 热关断保护
– 可编程平均电感器电流限制高达 16A
• 小解决方案尺寸
– 开关频率高达 2.2MHz（最大值）
– 具有可湿性侧面选项的 4.0mm × 3.5mm
HotRod™ QFN 封装
• 电缆上压降的可调输出电压补偿
• 轻负载状态下的可编程 PFM 和 FPWM 模式
• 感应电阻器的可编程输出电流限制
• ±1% 基准电压精度
• 固定 4ms 软启动时间
• 使用 TPS552882-Q1 并借助 WEBENCH® Power
Designer 创建定制设计方案
TPS552882-Q1 是一款同步四开关降压/升压转换器，
能够将输出电压稳定在等于、高于或低于输入电压的某
一电压值上。TPS552882-Q1 在 2.7V 至 36V 的宽输
入电压范围内工作，可输出 0.8V 至 22V 电压以支持各
种不同的应用。
2 应用
• USB PD
• 汽车信息娱乐系统与仪表组
• 汽车充电器
TPS552882-Q1 集成了两个 16A MOSFET，其中的升
压腿可实现解决方案尺寸和效率间的平衡。
TPS552882-Q1 使用外部电阻分压器，通过 1.2V 内部
基准电压来设置输出电压。TPS552882-Q1 能够通过
12V 输入电压提供 100W 的功率。
TPS552882-Q1 采用平均电流模式控制方案。开关频
率可通过外部电阻在 200kHz 至 2.2MHz 之间进行编
程，并且可与外部时钟同步。TPS552882-Q1 还提供
可选的扩频，从而更大限度地减少峰值 EMI。
TPS552882-Q1 提供输出过压保护、平均电感器电流
限制、逐周期峰值电流限制和输出短路保护。
TPS552882-Q1 还使用持续过载情况下的可选输出电
流限制和断续模式保护来确保安全运行。
TPS552882-Q1 可以使用具有高开关频率的小型电感
器和电容器。此器件采用 4.0mm × 3.5mm QFN 封
装。
器件信息
器件型号
封装(1)
封装尺寸
TPS552882-Q1
VQFN-HR
4.00mm × 3.50mm
(1)
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
L1
4.7µH
C5
0.1µF
C4
0.1µF
DR1H DR1L BOOT1 SW1
VIN = 2.7V to 36V
SW2
VIN
PGND
PG
CC
R8
R1
AGND
ISP
ON
MODE
R7
10PŸ
C2
C3
VCC
4.7µF
EN/UVLO
VOUT = 0.8V to 20V
VOUT
C1
OFF
BOOT2
TPS552882-Q1
ISN
FB
COMP
C8
DITH/SYNC
CDC
FSW
ILIM
C6
R4
R5
R3
R2
C7
R2
典型应用电路
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSFQ8
TPS552882-Q1
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ZHCSMV3A – DECEMBER 2020 – REVISED DECEMBER 2021
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 9
7 Detailed Description......................................................12
7.1 Overview................................................................... 12
7.2 Functional Block Diagram......................................... 13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................19
8 Application and Implementation.................................. 21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 接收文档更新通知................................................... 32
11.3 支持资源..................................................................32
11.4 Trademarks............................................................. 32
11.5 术语表..................................................................... 32
11.6 静电放电警告...........................................................32
12 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
Changes from Revision * (December 2020) to Revision A (December 2021)
Page
• 添加了可湿性侧面选项........................................................................................................................................1
2
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BOOT2
20
SW2
21
2
18
COMP
VIN
3
17
ILIM
EN/UVLO
4
16
CDC
PG
5
15
MODE
26
SW2
VOUT
VCC
25
DR1H
22
19
PGND
1
24
DR1L
23
SW1
BOOT1
5 Pin Configuration and Functions
6
CC
14
FB
12
ISN
ISP
11
VOUT
10
AGND
PGND
FSW
8
13
9
7
DITH/SYNC
图 5-1. 26-pin VQFN-HR RPM Transparent (Top View)
表 5-1. Pin Functions
PIN
NO.
NAME
1
DR1L
2
3
I/O
DESCRIPTION
O
Gate driver output for low-side MOSFET in buck side
DR1H
O
Gate driver output for high-side MOSFET in buck side
VIN
PWR
Power supply to the IC from input voltage
4
EN/UVLO
I
Enable logic input and programmable input voltage undervoltage lockout (UVLO) input. Logic high
level enables the device. Logic low level disables the device and turns it into shutdown mode. After
the voltage at the EN/UVLO pin is above the logic high voltage of 1.15 V, this pin acts as
programmable UVLO input with 1.23-V internal reference.
5
PG
O
Power good indication. When the output voltage is above 95% of the setting output voltage, this pin
outputs high impedance. When the output voltage is below 90% of the setting output voltage, this pin
outputs low level
6
CC
O
Constant current output indication
I
Dithering frequency setting and synchronous clock input. Use a capacitor between this pin and
ground to set the dithering frequency. When this pin is short to ground or pulled above 1.2 V, there is
no dithering function. An external clock can be applied at this pin to synchronize the switching
frequency.
The switching frequency is programmed by a resistor between this pin and the AGND pin.
7
8
DITH/SYNC
FSW
I
9, 24
PGND
PWR
Power ground of the IC. It is connected to the source of the low-side MOSFET.
10
AGND
PWR
Signal ground of the IC
11, 26
VOUT
PWR
Output of the buck-boost converter
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表 5-1. Pin Functions (continued)
PIN
NO.
NAME
12
ISP
DESCRIPTION
I
Positive input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
13
ISN
I
Negative input of the current sense amplifier. An optional current sense resistor connected between
the ISP pin and the ISN pin can limit the output current. If the sensed voltage reaches the current
limit setting value in the register, a slow constant current control loop becomes active and starts to
regulate the voltage between the ISP pin and the ISN pin. Connecting the ISP pin and the ISN pin
together with the VOUT pin can disable the output current limit function.
14
FB
I
Connect to the center of a resistor divider to program the output voltage.
15
MODE
I
Setting the operation modes of the TPS55288x to select PFM mode or forced PWM mode in light
load condition and to select the internal LDO or external 5 V for VCC by a resistor between this pin
and AGND.
16
CDC
O
Voltage output proportional to the sensed voltage between the ISP pin and the ISN pin. Use a
resistor between this pin and AGND to increase the output voltage to compensate voltage droop
across the cable caused by the cable resistance.
17
ILIM
O
Average inductor current limit setting pin. Connect an external resistor between this pin and the
AGND pin.
18
COMP
I
Output of the internal error amplifier. Connect the loop compensation network between this pin and
the AGND pin.
19
VCC
O
Output of the internal regulator. A ceramic capacitor of more than 4.7 μF is required between this
pin and the AGND pin.
20
BOOT2
O
Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW2 pin.
SW2
I
The switching node pin of the boost side. It is connected to the drain of the internal low-side power
MOSFET and the source of internal high-side power MOSFET.
22
BOOT1
I
Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1 µF must be
connected between this pin and the SW1 pin.
23
SW1
I
The switching node pin of the buck side. It is connected to the drain of the external low-side power
MOSFET and the source of external high-side power MOSFET.
21, 25
4
I/O
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VIN, SW1
DRH1, BOOT1
Voltage range
at terminals(2)
MIN
MAX
–0.3
40
UNIT
V
SW1–0.3
SW1+6
V
VCC, DRL1, PG, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/
SYNC
–0.3
6
V
VOUT, SW2, ISP, ISN
–0.3
25
V
VOUT-6
VOUT+6
V
-0.3
20
V
SW2–0.3
SW2+6
V
ISP, ISN
EN
BOOT2
–0.3
VCC+0.3
V
TJ
DRL1, CC, ILIM, FSW, COMP, FB, MODE, CDC, DITH/SYNC
Operating Junction, TJ (3)
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground terminal.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.2 ESD Ratings
VALUE
V(ESD) (1) Electrostatic discharge
V(ESD) (1) Electrostatic discharge
(1)
(2)
(3)
Human-body model (HBM), per AEC
Q100-002(2)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011, all pins (3)
±500
Charged-device model (CDM), per AEC Q100-011, corner pins (3)
±750
V
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
VIN
Input voltage range
2.7
VOUT
Output voltage range
0.8
L
Effective inductance range
CIN
Effective input capacitance range
4.7
22
COUT
Effective output capacitance range
10
100
TJ
Operating junction temperature
1
–40
MAX
36
4.7
UNIT
V
22
V
10
µH
µF
1000
µF
150
°C
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6.4 Thermal Information
TPS552882-Q1
THERMAL
METRIC(1)
TPS552882-Q1
VQFN-HR (RPM)-26 PINS VQFN-HR (RPM)-26 PINS
Standard
EVM(2)
UNIT
RθJA
Junction-to-ambient thermal resistance
47.5
25.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.8
N/A
°C/W
RθJB
Junction-to-board thermal resistance
12.8
N/A
°C/W
ΨJT
Junction-to-top characterization parameter
0.5
0.6
°C/W
ΨJB
Junction-to-board characterization parameter
12.7
11.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.8
N/A
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Simulated on TPS552882-Q1EVM-045, 4-layer, 2-oz/2-oz/2-oz/2-oz copper 112-mm×71-mm PCB.
6.5 Electrical Characteristics
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
Input voltage range
VVIN_UVLO
2.7
Under voltage lockout threshold
36
V
VIN rising
2.8
2.9
3.0
V
VIN falling
2.6
2.65
2.7
V
Quiescent current into the VIN pin
IC enabled, no load, no switching. VIN
= 3 V to 24 V, VOUT = 0.8 V, VFB =
VREF + 0.1 V, RFSW=100 kΩ, TJ up to
125°C
760
860
µA
Quiescent current into the VOUT pin
IC enabled, no load, no switching, VIN
= 2.9 V, VOUT = 3 V to 20 V, VFB =
VREF + 0.1 V, RFSW=100 kΩ, TJ up to
125°C
760
860
µA
ISD
Shutdown current into VIN pin
IC disabled, VIN = 2.9 V to 14 V, TJ up
to 125°C
7
10
µA
VCC
Internal regulator output
IVCC = 50 mA, VIN = 8 V, VOUT = 20 V
IQ
VCC_DO
VCC dropout
5.2
5.4
V
VIN = 5.0 V, VOUT = 20 V, IVCC = 60 mA
5.0
200
320
mV
VIN = 14 V, VOUT = 5.0 V, IVCC = 60 mA
110
170
mV
1.15
V
EN/UVLO
VEN_H
EN Logic high threshold
VCC = 2.7 V to 5.5 V
VEN_L
EN Logic low threshold
VCC = 2.7 V to 5.5 V
0.4
VEN_HYS
Enable threshold hysteresis
VCC = 2.7 V to 5.5 V
0.05
0.12
VUVLO
UVLO rising threshold at the EN/UVLO
VCC = 3.0 V to 5.5 V
pin
1.20
1.23
VUVLO_HYS
UVLO threshold hysteresis
VCC = 3.0 V to 5.5 V
8
14
20
mV
IUVLO
Sourcing current at the EN/UVLO pin
VUVLO = 1.3 V
4.5
5
5.5
µA
22
V
24.5
V
100
nA
20
µA
V
V
1.26
V
OUTPUT
6
VOUT
Output voltage range
0.8
VOVP
Output overvoltage protection
threshold
VOVP_HYS
Over voltage protection hysteresis
IFB_LKG
Leakage current at the FB pin
TJ up to 125°C
IVOUT_LKG
Leakage current into the VOUT pin
IC disabled, VOUT = 20 V, VSW2 = 0 V,
TJ up to 125°C
22.5
23.5
1
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6.5 Electrical Characteristics (continued)
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.188
1.2
1.212
V
REFERENCE VOLTAGE
VREF
Reference voltage at the FB pin
POWER SWITCH
RDS(on)
Low-side MOSFET on resistance on
boost side
VOUT = 20 V, VCC = 5.2 V
7.1
mΩ
High-side MOSFET on resistance on
boost side
VOUT = 20 V, VCC = 5.2 V
7.6
mΩ
INTERNAL CLOCK
RFSW = 100 kΩ
180
200
220
kHz
RFSW = 9.09 kΩ
2000
2200
2400
kHz
100
145
ns
90
130
ns
fSW
Switching frequency
tOFF_min
Min. off time
Boost mode
tON_min
Min. on-time
Buck mode
VFSW
Voltage at the FSW pin
1
V
CURRENT LIMIT
ILIM_AVG
ILIM_PK
VILIM
VSNS
Average inductor current limit
Peak inductor current limit at high side
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 500 kHz, FPWM
14
16.5
19
A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 500 kHz, PFM
14
16.5
19
A
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V,
fSW = 2.2 MHz, FPWM
4
5.5
A
RILIM = 60 kΩ, VIN = 5 V, VOUT = 14 V,
fSW = 2.2 MHz, PFM
4
5.5
A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 500 kHz, FPWM
25
A
RILIM = 20 kΩ, VIN = 8 V, VOUT = 20 V,
fSW = 500 kHz, PFM
25
A
Voltage at the ILIM pin
VOUT = 3 V
Current loop regulation voltage
between the ISP and ISN pins
VISN = 2 V to 21 V
48
0.6
50
52
mV
V
VISN = 2 V to 21 V
28
30
32
mV
0.95
1
1.05
40
75
mV
7.5
7.87
µA
External output feedback, RCDC = 20
kΩ, VISP – VISN = 0 mV
0
0.3
µA
External output feedback, RCDC =
floating, VISP – VISN = 50 mV
0
0.3
µA
CABLE VOLTAGE DROP COMPENSATION
VCDC
RCDC = 20 kΩ or floating, VISP – VISN
= 50 mV
Voltage at the CDC pin
RCDC = 20 kΩ or floating, VISP – VISN
= 2 mV
External output feedback, RCDC = 20
kΩ, VISP – VISN = 50 mV
IFB_CDC
FB pin sinking current
7.23
V
ERROR AMPLIFIER
ISINK
COMP pin sink current
VFB = VREF + 400 mV, VCOMP = 1.5 V,
VCC = 5 V
20
µA
ISOURCE
COMP pin source current
VFB = VREF - 400 mV, VCOMP = 1.5 V,
VCC = 5 V
60
µA
VCCLPH
High clamp voltage at the COMP pin
1.8
V
VCCLPL
Low clamp voltage at the COMP pin
0.7
V
GEA
Error amplifier transconductance
190
µA/V
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6.5 Electrical Characteristics (continued)
TJ = -40°C to 125°C, VIN = 12 V and VOUT = 20 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3
4
5
UNIT
SOFT START
tSS
Soft-start time
ms
DR1H GATE DRIVER
VDR1H_L
Low-state voltage drop
VDR1H – VSW1, 100-mA sinking
0.1
V
VDR1H_H
High-state voltage drop
VBOOT1 – VDR1H, 100-mA sourcing
0.2
V
DR1L GATE DRIVER
VDR1L_L
Low-state voltage drop
100-mA sinking
0.1
V
VDR1L_H
High-state voltage drop
VCC – VDR1L, 100-mA sourcing
0.2
V
SPREAD SPECTRUM
IDITH_CHG
Dithering charge current
VDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ;
voltage rising from 0.85 V
2
µA
IDITH_DIS
Dithering discharge current
VDITH/SYNC = 1.0 V, RFSW = 49.9 kΩ;
voltage falling from 1.15 V
2
µA
VDITH_H
Dither high threshold
1.07
V
VDITH_L
Dither low threshold
0.93
V
SYNCHRONOUS CLOCK
VSNYC_H
Sync clock high voltage threshold
VSYNC_L
Sync clock low voltage threshold
0.4
1.2
V
V
tSYNC_MIN
Minimum sync clock pulse width
50
ns
HICCUP
tHICCUP
Hiccup off time
76
ms
MODE RESISTANCE DETECTION
IMODE
Sourcing current from the MODE pin
VMODE_DT1
VMODE_DT2
VMODE = 2.5 V
Detection threshold voltage at the
MODE pin
VMODE_DT3
9
10
11
µA
0.571
0.614
0.657
V
0.322
0.351
0.380
V
0.169
0.189
0.209
V
100
nA
0.2
V
100
nA
0.2
V
LOGIC INTERFACE
IPG_H
Leakage current into PG pin when
outputting high impedance
VPG_L
Output low voltage range of the PG pin Sinking 4-mA current
ICC_H
Leakage current into CC pin when
outputting high impedance
VCC_L
Output low voltage range of the CC pin Sinking 4-mA current
0.1
TSD
Thermal shutdown threshold
TJ rising
175
°C
TSD_HYS
Thermal shutdown hysteresis
TJ falling below TSD
20
°C
VPG = 5 V
0.1
VCC = 5 V
PROTECTION
8
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6.6 Typical Characteristics
100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
VIN = 12 V, TA = 25°C, fSW = 400 kHz, unless otherwise noted.
50%
40%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
10%
0
0.0001
2 3 5 710
0.01
0.1 0.2 0.5 1
Output Current (A)
2 3 5 710
D002
图 6-2. Efficiency vs Output Current,
VOUT = 5 V, PFM
100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
0.001
D001
图 6-1. Efficiency vs Output Current,
VOUT = 5 V, FPWM
50%
40%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
2 3 5 710
0.001
D003
图 6-3. Efficiency vs Output Current,
VOUT = 9 V, FPWM
0.01
0.1 0.2 0.5 1
Output Current (A)
2 3 5 710
D004
图 6-4. Efficiency vs Output Current,
VOUT = 9 V, PFM
100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
50%
40%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
10%
2 3 5 710
图 6-5. Efficiency vs Output Current,
VOUT = 12 V, FPWM
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
0
0.0001
D005
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
2 3 5 710
D006
图 6-6. Efficiency vs Output Current,
VOUT = 12 V, PFM
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90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
90%
Efficiency
100%
50%
40%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
10%
0
0.0001
2 3 5 710
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
90%
Efficiency
0.01
0.1 0.2 0.5 1
Output Current (A)
2 3 5 710
D008
图 6-8. Efficiency vs Output Current,
VOUT = 15 V, PFM
100%
50%
40%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
10%
0
0.0001
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
10%
0
0.0001
2 3 5 710
0.001
0.01
0.1 0.2 0.5 1
Output Current (A)
D009
2 3 5 710
D010
图 6-10. Efficiency vs Output Current,
VOUT = 20 V, PFM
2200
VIN = 20 V, VOUT = 5 V
VIN = 12 V, VOUT = 12 V
VIN = 5 V, VOUT = 20 V
2000
1800
1600
Frequency (kHz)
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
20
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
图 6-9. Efficiency vs Output Current,
VOUT = 20 V, FPWM
Current Limit (A)
0.001
D007
图 6-7. Efficiency vs Output Current,
VOUT = 15 V, FPWM
1400
1200
1000
800
600
400
200
0
30
40
50
60
70
Resistance (k:)
80
90
100
图 6-11. Average Inductor Current Limit vs Setting
Resistance
10
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 20 V
20%
0
10
20
30
40
50
60
Resistance (k:)
70
80
90
100
图 6-12. Switching Frequency vs Setting
Resistance
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780
1.212
775
Quiescent Current (PA)
1.218
VREF (V)
1.206
1.2
1.194
770
765
760
755
1.188
1.182
-40
750
-20
0
20
40
60
80
Temperature (qC)
100
120
Into VIN, VIN = 24 V, VOUT = 3 V
Into VOUT, VIN = 3.1 V, VIN = 20 V
745
-40
140
图 6-13. Reference Voltage vs Temperature (VREF =
1.2 V)
-20
0
20
40
60
80
Temperature (qC)
100
120
140
D017
图 6-14. Quiescent Current vs Temperature
7.5
1.2355
1.235
1.2345
7
UVLO Threshold (V)
Shutdown Current (PA)
7.25
6.75
6.5
6.25
1.234
1.2335
1.233
1.2325
1.232
1.2315
1.231
6
1.2305
5.75
-40
-20
0
20
40
60
80
Temperature (qC)
100
120
1.23
-40
140
-20
0
D018
图 6-15. Shutdown Current vs Temperature
20
40
60
80
Temperature (qC)
100
120
140
D019
图 6-16. ENABLE/UVLO Rising Threshold vs
Temperature
1.6
2500
1.2
CDC Voltage (V)
Switching Frequency (Hz)
1.4
2000
1500
1000
fSW = 200 kHz
fSW = 2200 kHz
1
0.8
0.6
0.4
500
0.2
0
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
1
D020
图 6-17. Switching Frequency vs Temperature
2
3
4
5
Output Current (A)
6
7
8
D021
图 6-18. CDC Voltage vs Output Current with
RSENSE = 10 mΩ
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7 Detailed Description
7.1 Overview
The TPS552882-Q1 is a 16-A buck-boost DC-to-DC converter with the two boost MOSFETs integrated. The
TPS552882-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and 0.8-V to 22-V output voltage. It
can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage
and the set output voltage. The TPS552882-Q1 operates in buck mode when the input voltage is greater than
the output voltage and in boost mode when the input voltage is less than the output voltage. When the input
voltage is close to the output voltage, the TPS552882-Q1 operates in one-cycle buck and one-cycle boost mode
alternately.
The TPS552882-Q1 uses an average current mode control scheme. Current mode control provides simplified
loop compensation, rapid response to the load transients, and inherent line voltage rejection. An error amplifier
compares the feedback voltage with the internal reference voltage. The output of the error amplifier determines
the average inductor current.
An internal oscillator can be configured to operate over a wide range of frequency from 200 kHz to 2.2 MHz. The
internal oscillator can also synchronize to an external clock applied to the DITH/SYNC pin. To minimize EMI, the
TPS552882-Q1 can dither the switching frequency at ±7% of the set frequency.
The TPS552882-Q1 works in fixed-frequency PWM mode at moderate to heavy load currents. In light load
condition, the TPS552882-Q1 can be configured to automatically transition to PFM mode or be forced in PWM
mode by either connecting a resistor at the MODE pin or setting the corresponding bit in an internal register.
On TPS552882-Q1, you can use an external resistor divider to program the output voltage. The TPS552882-Q1
also can limit the output current by placing a current sense resistor in the output path. These two functions
support the programmable power supply (PPS) feature of the USB-PD.
The TPS552882-Q1 provides average inductor current limit set by a resistor at the ILIM pin. In addition, it
provides cycle-by-cycle peak inductor current limit during transient to protect the device against overcurrent
condition beyond the capability of the device.
A precision voltage threshold of 1.23 V with 5-µA sourcing current at the EN/UVLO pin supports programmable
input undervoltage lockout (UVLO) with hysteresis. The output overvoltage protection (OVP) feature turns off the
high-side FETs to prevent damage to the devices powered by the TPS552882-Q1.
The device provides hiccup mode option to reduce the heating in the power components when output short
circuit happens. When the hiccup mode is enabled, the TPS552882-Q1 turns off for 76 ms and restarts at soft
start-up.
12
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7.2 Functional Block Diagram
L1
VIN
C3
C8
SW1
C4
BOOT1
BOOT2
SW2
R1
VIN
LDO
C1
VOUT
VOUT
VOUT
C2
Current
Sense
VCC
I-V
C5
CDC
R7
DL
I_limit
ISP
Buck-Boost
Control
DH
ISN
Iref
CC or FB
Gm
Gm
MODE
ADC
BOOST
BUCK
COMP
R3
DAC
CC
R2
Vref
PGND
PG
Logic Core
C6
EN/UVLO
Iref
DAC
VSYNC/DITH
1.0V
Vref
AGND
I_limit
VCC
VIN UVLO
VIN
VOUT OVP
VOUT
ILIM
FSW
R4
fMOD
R5
Thermal
DITH/SYNC
C7
7.3 Feature Description
7.3.1 VCC Power Supply
An internal LDO to supply the TPS552882-Q1 outputs regulated 5.2-V voltage at the VCC pin with 60-mA output
current capability. When VIN is less than VOUT, the internal LDO selects the power supply source by comparing
VIN to a rising threshold of 6.2 V with 0.3-V hysteresis. When VIN is higher than 6.2 V, the supply for LDO is VIN.
When VIN is lower than 5.9 V, the supply for LDO is VOUT. When VOUT is less than VIN, the internal LDO selects
the power supply source by comparing VOUT to a rising threshold of 6.2 V with 0.3-V hysteresis. When VOUT is
higher than 6.2 V, the supply for LDO is VOUT. When VOUT is lower than 5.9 V, the supply for LDO is VIN. 表 7-1
shows the supply source selection for the internal LDO.
表 7-1. VCC Power Supply Logic
VIN
VOUT
INPUT for VCC LDO
VIN > 6.2 V
VOUT>VIN
VIN
VIN < 5.9 V
VOUT>VIN
VOUT
VIN > VOUT
VOUT> 6.2 V
VOUT
VIN > VOUT
VOUT< 5.9 V
VIN
To minimize the power dissipation of the internal LDO when both input voltage and output voltage are high, an
external 5-V power source can be applied at the VCC pin to supply the TPS552882-Q1. The external 5-V power
supply must have at least 100-mA output current capability and must be within the 4.75-V to 5.5-V regulation
range. To use an external power supply for VCC, a resistor with proper resistance must be connected to the
MODE pin.
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7.3.2 Operation Mode Setting
By placing different resistors between the MODE pin and the AGND pin, the TPS552882-Q1 selects the internal
power supply or external power supply for VCC, and also selects the PFM mode or forced PWM mode in light
load conditions.表 7-2 shows the resistance values for each selection.
表 7-2. VCC Source and PFM/PWM Programming
RESISTOR VALUE (kΩ)
VCC SOURCE
OPERATING MODE AT LIGHT LOAD
0
Internal
PWM
24.9
Internal
PFM
51.1
External
PWM
Open
External
PFM
7.3.3 Input Undervoltage Lockout
When the input voltage is below 2.6 V, the TPS552882-Q1 is disabled. When the input voltage is above 3 V, the
TPS552882-Q1 can be enabled by pulling the EN pin to a high voltage above 1.3 V.
7.3.4 Enable and Programmable UVLO
The TPS552882-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage
at the VIN pin is above the input UVLO rising threshold of 3 V and the EN/UVLO pin is pulled above 1.15 V but
less than the enable UVLO threshold of 1.23 V, the TPS552882-Q1 is enabled but still in standby mode. The
TPS552882-Q1 starts to detect the resistance between the MODE pin and ground. After that, the TPS55288x
selects the power supply for VCC and the PFM or FPWM mode for light load condition accordingly.
The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout
with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23 V, the TPS552882Q1 is enabled for switching operation. A hysteresis current IUVLO_HYS of 5 μA is sourced out of the EN/UVLO pin
to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input
voltage.
By using resistor divider as shown in 图 7-1, the turnon threshold is calculated using 方程式 1.
8+0(78.1 _10) = 878.1 × (1 +
R1
)
42
(1)
where
• VUVLO is the UVLO threshold of 1.23 V at the EN/UVLO pin
The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/
UVLO resistor divider and is given by the 方程式 2.
¿8+0(78.1 ) = +78.1 _*;5 × 41
(2)
where
• IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above
VUVLO
14
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VIN
IUVLO_HYS
R1
EN/UVLO
R2
Enable
C1
UVLO Comparator
1.23V
图 7-1. Programmable UVLO With Resistor Divider at the EN/UVLO Pin
Using an NMOS FET together with resistor divider can implement both logic enable and programmable UVLO as
shown in 图 7-2. The EN logic high level must be greater than enable threshold plus the Vth of the NMOSFET
Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor divider during
shutdown mode.
VIN
R1
IUVLO_HYS
EN
EN/UVLO
R2
Enable
C1
UVLO Comparator
1.23V
图 7-2. Logic Enable and Programmable UVLO
7.3.5 Soft Start
When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable
UVLO threshold, the TPS552882-Q1 starts to ramp up the output voltage by ramping an internal reference
voltage from 0 V to a voltage which is set by 1.2 V on the TPS552882-Q1 within 4 ms.
7.3.6 Shutdown
When the EN pin voltage is pulled below 0.4 V, the TPS552882-Q1 is in shutdown mode, and all functions are
disabled.
7.3.7 Switching Frequency
The TPS552882-Q1 uses a fixed frequency average current control scheme. The switching frequency is
between 200 kHz and 2.2 MHz set by placing a resistor at the FSW pin. An internal amplifier holds this pin at a
fixed voltage of 1 V. The setting resistance is between maximum of 100 kΩ and minimum of 9.09 kΩ. Use 方程式
3 to calculate the resistance by a given switching frequency.
1000
(MHz)
0.05 × 4(59 + 20
(3)
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where
• RFSW is the resistance at the FSW pin
For noise-sensitive applications, the TPS552882-Q1 can be synchronized to an external clock signal applied to
the DITH/SYNC pin. The duty cycle of the external clock is recommended in the range of 30% to 70%. A resistor
also must be connected to the FSW pin when the TPS552882-Q1 is switching by the external clock. The
external clock frequency at the DITH/SYNC pin must have lower than 0.4-V low level voltage and must be within
±30% of the corresponding frequency set by the resistor. 图 7-3 is a recommended configuration.
External Clock
DITH/SYNC
FSW
RFSW
图 7-3. External Clock Configuration
7.3.8 Switching Frequency Dithering
The TPS552882-Q1 provides an optional switching frequency dithering that is enabled by connecting a capacitor
from the DITH/SYNC pin to ground. 图 7-4 illustrates the dithering circuit. By charging and discharging the
capacitor, a triangular waveform centered at 1 V is generated at the DITH/SYNC pin. The triangular waveform
modulates the oscillator frequency by ±7% of the nominal frequency set by the resistance at the FSW pin. The
capacitance at the DITH/SYNC pin sets the modulation frequency. A small capacitance modulates the oscillator
frequency at a fast rate than a large capacitance. For the dithering circuit to effectively reduce peak EMI, the
modulation rate normally is below 1 kHz. Equation 4 calculates the capacitance required to set the modulation
frequency, FMOD.
%&+6* =
1
(()
2.8 × 4(59 × (/1&
(4)
where
• RFSW is the switching frequency setting resistance (Ω) at the FSW pin
• FMOD is the modulation frequency (Hz) of the dithering
Connecting the DITH/SYNC pin below 0.4 V or above 1.2 V disables switching frequency dithering. The dithering
function also is disabled when an external synchronous clock is used.
1.07V
1.0V
0.93V
FMOD
DITH/SYNC
CDITH
FSW
RFSW
图 7-4. Switching Frequency Dithering
16
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7.3.9 Inductor Current Limit
The TPS552882-Q1 implements both peak current and average inductor current limit by a resistor connected to
the ILIM pin. The average current mode control loop uses the current sense information at the high-side
MOSFET of the boost leg to clamp the maximum average inductor current to 16.5 A (typical) when the resistor is
20 kΩ. Use large resistance to get smaller average inductor current limit. Use 方程式 5 to calculate the
resistance for a desired average inductor current limit.
+#8)_.+/+6 =
min(1,0.6 × 8176 ) × 330000
(#)
4 +.+/
(5)
where
• IAVG_LIMIT is the average inductor current limit
• RILIM is the resistance (Ω) between the ILIM pin and analog ground
Besides the average current limit, a peak current limit protection is implemented during transient to protect the
device against over current condition beyond the capability of the device.
7.3.10 Internal Charge Path
Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally recharged by VCC through both the external and internal bootstrap diodes when the low-side MOSFET is turned
on. When the TPS55288 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is
constantly on. An internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2,
charges the bootstrap capacitor to VCC so that the high-side MOSFET remains on.
7.3.11 Output Voltage Setting
There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage.
The TPS552882-Q1 uses an external resistor divider to change the feedback ratio with fixed 1.2-V reference
voltages at the FB pin.
When using external output voltage feedback resistor divider as shown in 图 7-5. Use 方程式 6 to calculate the
output voltage with the reference voltage at the FB pin.
V176 = 84'( × (1 +
4($_72
)
4($_$6
(6)
RSNS
VOUT
ISP
VOUT
RFB_UP
ISN
FB
RFB_BT
图 7-5. Output Voltage Setting by External Resistor Divider
TI recommends using 100 kΩ for the up resistor RFB_UP. The reference voltage VREF at the FB pin is 1.2 V.
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7.3.12 Output Current Indication and Cable Voltage Drop Compensation
The TPS55288 outputs a voltage at the CDC pin proportional to the sensed voltage across a output current
sensing resistor between the ISP pin and the ISN pin. 方程式 7 shows the exact voltage at the CDC pin related
to the sensed output current.
V%&% = 20 × (8+52 F 8+50 )
(7)
To compensate the voltage drop across a cable from the terminal of the USB port to its powered device, the
TPS552882-Q1 can lift its output voltage in proportion to the load current by placing a resistor between the CDC
pin and AGND pin.
When using external output voltage feedback on the TPS552882-Q1, the output voltage rises in proportional to
the current sourcing from the CDC pin through the resistor at the CDC pin. It is recommended to use 100-kΩ
resistance for the up resistor of the resistor divider. 方程式 8 shows the output voltage rise versus the sensed
output current, resistance at the CDC pin and the up resistor of the output voltage feedback resistor divider.
V176_%&% = 3 × 4($_72 × (
8+52 F 8+50
)
4%&%
(8)
where
• RFB_UP is the up resistor of the resistor divider between the output and the FB/INT pin
• RCDC is the resistor at the CDC pin
When RFB_UP is 100 kΩ, the output voltage rise versus the sensed output current and the resistor at the CDC
pin is shown in 图 7-6
VOUT_CDC(V)
0.8
RCDC=20K
0.75V
0.7
0.6
0.5
RCDC=30K
0.5V
0.4
0.3
RCDC=75K
0.2V
0.2
RCDC=150K
0.1
0.1V
RCDC=floating
10
20
30
40
50
VISP ± VISN
(mV)
图 7-6. Output Voltage Rise versus Output Current
7.3.13 Integrated Gate Drivers
The TPS552882-Q1 provides two N-channel MOSFET gate drivers for buck side. Each driver is capable of
sourcing 1-A and sinking 1.8-A peak current. In buck operation, the DR1H pin and the DR1L pin are switched by
the PWM controller. In boost mode, the DR1H pin remains at continuously high voltage to turn on the high-side
MOSFET of the buck side, and the DR1L pin remains at continuously low voltage to turn off the low-side
MOSFET of the buck side.
In DCM buck mode operation, the DR1L turns off the low-side FET when the inductor current drops to zero.
The low-side gate driver is powered from the VCC pin, and the high-side gate driver is powered from the
bootstrap capacitor CBOOT1, which is between the BOOT1 pin and the SW1 pin.
18
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7.3.14 Output Current Limit
The output current limit is programmable by placing a current sensing resistor between the ISP pin and ISN pin.
The voltage limit between the ISP pin and the ISN pin is set to 50 mV. Thus a smaller resistance gets higher
current limit and a bigger resistance gets lower current limit.
Connecting the ISP pin and ISN pin together to the VOUT pin disables the current limit function.
7.3.15 Overvoltage Protection
The TPS552882-Q1 has output overvoltage protection. When the output voltage at the VOUT pin is detected
above 23.5 V typically, the TPS552882-Q1 turns off two high-side FETs and turns on two low-side FETs until its
output voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function
prevents overvoltage on the output and secures the circuits connected to the output from excessive overvoltage.
7.3.16 Output Short Circuit Protection
In addition to the average inductor current limit, the TPS552882-Q1 implements the output short-circuit
protection by entering the hiccup mode. When the output short circuit happens, the TPS552882-Q1 goes into
output current limit first. If the output voltage is below 0.8 V and the average inductor current is above the setting
value, the TPS552882-Q1 shuts down the switching for 76 ms (typical) and restarts the soft start repeatedly. The
hiccup mode helps reduce the total power dissipation on the TPS552882-Q1 in the output short-circuit or
overcurrent condition.
7.3.17 Thermal Shutdown
The TPS552882-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal
junction temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers
values remain unchanged when thermal shutdown is triggered. The converter automatically restarts when the
junction temperature drops below the thermal shutdown hysteresis of 20°C below the thermal shutdown
threshold.
7.4 Device Functional Modes
In light load condition, the TPS552882-Q1 can work in PFM or forced PWM mode to meet different application
requirements. The PFM mode decreases switching frequency to reduce the switching loss thus it gets high
efficiency at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired
low switching frequency but the efficiency becomes lower than that of PFM mode.
7.4.1 PWM Mode
In FPWM mode, the TPS552882-Q1 keeps the switching frequency unchanged in light load condition. When the
load current decreases, the output of the internal error amplifier decreases as well to reduce the average
inductor current down to deliver less power from input to output. When the output current further reduces, the
current through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned
off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs
to zero. The power flow is from output side to input side. The efficiency is low in this condition. However, with the
fixed switching frequency, there is no audible noise or other problems that might be caused by low switching
frequency in light load condition.
7.4.2 Power Save Mode
The TPS552882-Q1 improves the efficiency at light load condition with the PFM mode. By connecting an
appropriate resistor at the MODE pin or enabling the PFM function in the internal register, the TPS552882-Q1
can work in PFM mode at light load condition. When the TPS552882-Q1 operates at light load condition, the
output of the internal error amplifier decreases to make the inductor peak current down to deliver less power to
the load. When the output current further reduces, the current through the inductor will decrease to zero during
the switch-off time. When the TPS552882-Q1 works in buck mode, once the inductor current becomes zero, the
low-side switch of the buck side is turned off to prevent the reverse current from output to ground. When the
TPS552882-Q1 works in boost mode, once the inductor current becomes zero, the high side-switch of the boost
side is turned off to prevent the reverse current from output to input. The TPS552882-Q1 resumes switching until
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the output voltage drops. Thus the PFM mode reduces switching cycles and eliminates the power loss by the
reverse inductor current to get high efficiency in light load condition.
20
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8 Application and Implementation
Note
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The TPS552882-Q1 can operate over a wide range of 2.7-V to 36-V input voltage and output 0.8 V to 22 V. It
can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage
and the setting output voltage. The TPS552882-Q1 operates in buck mode when the input voltage is greater
than the output voltage and in boost mode when the input voltage is less than the output voltage. When the input
voltage is close to the output voltage, the TPS552882-Q1 operates in one-cycle buck and one-cycle boost mode
alternately. The switching frequency is set by an external resistor. To reduce the switching power loss in high
power conditions, it is recommended to set the switching frequency below 500 kHz. If a system requires higher
switching frequency above 500 kHz, it is recommended to set the lower switch current limit for better thermal
performance.
8.2 Typical Application
The TPS552882-Q1 provides a small size solution for USB PD power supply application with the input voltage
ranging from 9 V to 36 V.
L1
4.7µH
C5
C4
0.1µF
DR1H
VIN = 9V to 36V
DR1L
BOOT1
0.1µF
SW1
SW2
BOOT2
VOUT = 5V
VIN
VOUT
C1
R7
10PŸ
C2
4 x 10µF
C3
4.7µF
VCC
4 x 22µF
PGND
R1
PG
100kŸ
AGND
CC
ISP
ON
EN/UVLO
TPS552882-Q1
ISN
OFF
MODE
FB
R8
6.19kŸ
COMP
DITH/SYNC
C8
C6
CDC
R4
150kŸ
ILIM
FSW
0.01µF
R5
19.9kŸ
R2
R3
R2
29.4kŸ
C7
49.9kŸ
图 8-1. 5-V Power Supply With 9-V to 36-V Input Voltage
8.2.1 Design Requirements
The design parameters are listed in 表 8-1:
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表 8-1. Design Parameters
PARAMETERS
VALUES
Input voltage
9 V to 36 V
Output voltage
5 V to 20 V
Output current limit
5A
Output voltage ripple
±50 mV
Operating mode at light load
PFM
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS552882-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency
The switching frequency of the TPS552882-Q1 is set by a resistor at the FSW pin. Use 方程式 3 to calculate the
resistance for the desired frequency. To reduce the switching power loss with such a high current application, a
1% standard resistor of 49.9 kΩ is selected for 400-kHz switching frequency for this application.
8.2.2.3 Output Voltage Setting
An external resistor divider is used to program the output voltage.
8.2.2.4 Inductor Selection
Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications: inductance, saturation current, and DC resistance.
The TPS552882-Q1 is designed to work with inductor values between 1 µH and 10 µH. The inductor selection is
based on consideration of both buck and boost modes of operation.
For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum input voltage. In CCM, 方程式 9 shows the relationship between the inductance
and the inductor ripple current.
L=
kVIN(MAX) -VOUT o×VOUT
¨IL(P-P) ×fSW ×VIN:MAX;
(9)
where
• VIN(MAX) is the maximum input voltage
• VOUT is the output voltage
• ΔIL(P-P) is the peak to peak ripple current of the inductor
22
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• fSW is the switching frequency
For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals half of the
maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum
inductor current at the maximum output voltage. In CCM, 方 程 式 10 shows the relationship between the
inductance and the inductor ripple current.
L=
VIN ×kVOUT(MAX) -VIN o
¨IL(P-P) ×fSW ×VOUT(MAX)
(10)
where
•
•
•
•
VIN is the input voltage
VOUT(MAX) is the maximum output voltage
ΔIL(P-P) is the peak to peak ripple current of the inductor
fSW is the switching frequency
For a certain inductor, the inductor ripple current achieves maximum value when VIN equals to the half of the
maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller
inductance gets larger inductor current ripple.
For this application example, a 4.7-µH inductor is selected, which produces approximate maximum inductor
current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average
inductor current in boost mode.
In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can
be calculated with 方程式 11.
IL(DC) =
VOUT ×IOUT
VIN ×
(11)
where
•
•
•
•
VOUT is the output voltage
IOUT is the output current
VIN is the input voltage
η is the power conversion efficiency
For a given maximum output current of the buck-boost converter TPS552882-Q1, the maximum inductor DC
current happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the
TPS552882-Q1 higher than the calculated maximum inductor DC current to make sure the TPS552882-Q1 has
the desired output current capability.
In boost mode, the inductor ripple current is calculated with 方程式 12.
¨IL(P-P) =
VIN ×:VOUT-VIN ;
L×fSW ×VOUT
(12)
where
•
•
•
•
•
ΔIL(P-P) is the inductor ripple current
L is the inductor value
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
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Therefore, the inductor peak current is calculated with 方程式 13.
IL(P) = IL(DC) +
¨IL(P-P)
2
(13)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The
selected inductor must have higher saturation current than the calculated peak current.
The conversion efficiency is dependent on the resistance of its current path. The switching loss associated with
the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the inductor
DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss. 表 8-2
lists recommended inductors for the TPS552882-Q1. In this application example, the Coilcraft inductor
XAL1010-472 is selected for its small size, high saturation current, and small DCR.
表 8-2. Recommended Inductors
(1)
PART NUMBER
L (µH)
DCR
(MAXIMUM)
(mΩ)
SATURATION
CURRENT / HEAT
RATING CURRENT (A)
SIZE (L x W x H mm)
VENDOR(1)
XAL1010-472ME
4.7
10
25.4/17.5
11.3 × 10 × 10
Coilcraft
IHLP5050EZER4R7
4.7
10.1
17.8/15.3
13.5 × 12.9 × 5
Vishay
125CDMCCDS-4R7MC
4.7
10
22/14
13.5 × 12.6 × 5
Sumida
See the Third-Party Products Disclaimer.
8.2.2.5 Input Capacitor
In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given
by 方程式 14.
VOUT ×:VIN -VOUT ;
ICIN:RMS; = IOUT ר
VIN ×VIN
(14)
where
• ICIN(RMS) is the RMS current through the input capacitor
• IOUT is the output current
The maximum RMS current occurs at the output voltage is half of the input voltage, which gives ICIN(RMS) = IOUT /
2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20 µF
effective capacitance is a good starting point for this application.
8.2.2.6 Output Capacitor
In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by 方程式 15, where the minimum input voltage and the maximum output voltage correspond to the
maximum capacitor current.
VOUT
ICOUT:RMS; = IOUT ר
-1
VIN
(15)
where
• ICOUT(RMS) is the RMS current through the output capacitor
• IOUT is the output current
24
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In this example, the maximum output ripple RMS current is 5.5 A.
The ESR of the output capacitor causes an output voltage ripple given by 方程式 16 in boost mode.
VRIPPLE(ESR) =
IOUT ×VOUT
×RCOUT
VIN
(16)
where
• RCOUT is the ESR of the output capacitance
The capacitance also causes a capacitive output voltage ripple given by 方程式 17 in boost mode. When input
voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest
output voltage ripple caused by the capacitance.
VRIPPLE(CAP) =
VIN
p
VOUT
COUT ×fSW
IOUT × l1-
(17)
Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR,
high ripple current, and small output voltage ripple. From the required output voltage ripple, use 方程式 16 and
方程式 17 to calculate the minimum required effective capacitance of the COUT.
8.2.2.7 Output Current Limit Sense Resistor
The output current limit is implemented by putting a current sense resistor between the ISP and ISN pins. The
value of the limit voltage between the ISP and ISN pins is 50 mV. The current sense resistor between the ISP
and ISN pins should be selected to ensure that the output current limit is set high enough for output. The output
current limit setting resistor is given by 方程式 18.
RSNS =
VSNS
IOUT_LIMIT
(18)
where
• VSNS is the current limit setting voltage between the ISP and ISN pin
• IOUT_LIMIT is the desired output current limit
Because the power dissipation is large, make sure the current sense resistor has enough power dissipation
capability with large package.
8.2.2.8 Loop Stability
The TPS55288 uses average current control scheme. The inner current loop uses internal compensation and
requires the inductor value must be larger than 1.2/fSW. The outer voltage loop requires an external
compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation
network comprised of resistor and ceramic capacitors is connected to the COMP pin.
The TPS55288 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require
loop compensations. The restrictive one of both compensations is selected as the overall compensation from a
loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost
mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ).
The power stage in boost mode can be modeled by 方程式 19.
s
s
RLOAD ×:1-D; l1+ 2N×fESRZ p × l1- 2N×fRHPZ p
GPS (s) =
×
s
2×RSENSE
1+
2N×fP
(19)
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where
• RLOAD is the output load resistance
• D is the switching duty cycle in boost mode
• RSENSE is the equivalent internal current sense resistor, which is 0.055 Ω
The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use 方程式
20 to 方程式 22 to calculate them.
fP =
2
2N×RLOAD ×COUT
fESRZ =
fRHPZ =
(20)
1
2N×RCOUT ×COUT
(21)
RLOAD ×:1-D;2
2N×L
(22)
The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the
control portion of the loop. The transfer function of the control portion is shown by 方程式 23.
GEA ×REA ×VREF
GC (s) =
×
VOUT
l1+
l1+
s
p
2N×fCOMZ
s
s
p × l1 +
p
2N×fCOMP2
2N×f COMP1
(23)
where
•
•
•
•
•
•
GEA is the transconductance of the error amplifier
REA is the output resistance of the error amplifier
VREF is the reference voltage input to the error amplifier
VOUT is the output voltage
fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network
fCOMZ is the zero’s frequency of the compensation network
The total open-loop gain is the product of GPS(s) and GC(s). The next step is to choose the loop crossover
frequency, fC, at which the total open-loop gain is 1, namely 0 dB. The higher in frequency that the loop gain
stays above 0 dB before crossing over, the faster the loop response. It is generally accepted that the loop gain
cross over 0 dB at the frequency no higher than the lower of either 1/10 of the switching frequency, fSW or 1/5 of
the RHPZ frequency, fRHPZ.
Then, set the value of RC, CC and CP by 方程式 24 to 方程式 26.
RC =
2N×VOUT ×RSENSE ×COUT ×fC
:1-D;×VREF ×GEA
(24)
where
• fC is the selected crossover frequency
CC =
CP =
26
RLOAD ×COUT
2×RC
(25)
RCOUT ×COUT
RC
(26)
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If the calculated CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output
voltage ringing during the line and load transient.
8.2.3 Application Curves
图 8-2. Switching Waveforms in VIN = 12 V, VOUT = 5 图 8-3. Switching Waveforms in VIN = 12 V, VOUT = 5
V, IO = 5 A, FPWM
V, IO = 0 A, PFM
图 8-4. Switching Waveforms in VIN = 12 V, VOUT =
12 V, IO = 5 A, FPWM
图 8-5. Switching Waveforms in VIN = 12 V, VOUT =
12 V, IO = 0 A, PFM
图 8-6. Switching Waveforms in VIN = 12 V, VOUT =
20 V, IO = 5 A, FPWM
图 8-7. Switching Waveforms in VIN = 12 V, VOUT =
20 V, IO = 0 A, PFM
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图 8-8. Start-up Waveforms in VIN = 12 V, VOUT = 5
V, IO = 5 A, FPWM
图 8-9. Shutdown Waveforms in VIN = 12 V, VOUT = 5
V, IO = 5 A, FPWM
图 8-10. Line Transient Waveforms in VIN = 9 V to
20 V, VOUT = 12 V, IO = 5 A with 200-μs Slew Rate,
FPWM
图 8-11. Load Transient Waveforms in VIN = 12 V,
VOUT = 5 V, IO = 2.5 A to 5 A with 20-μs Slew Rate,
FPWM
图 8-12. Output Current Limit Waveforms in VIN = 12 V, VOUT = 5 V, RLOAD = 0.9 Ω, RSNS = 10 mΩ, FPWM
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.7 V to 36 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum
electrolytic capacitor with a value of 100 μF.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and
noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation of
high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential.
Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane
under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN
pin and the PGND to reduce the input supply current ripple.
The most critical current path for buck converter portion is from the switching FET at the buck side, through the
rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET.
This high current path contains nanosecond rise time and fall time, and should be kept as short as possible.
Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND
terminal of the rectifier FET.
The most critical current path for boost converter portion is from the switching FET at the boost side, through the
rectifier FET at boost side, then the output capacitors, and back to ground of the switching FET. This high current
path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output
capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the
SW2 pin and the VOUT pin.
The traces from the output current sensing resistor to the ISP pin and the ISN pin must be in parallel and close
to each other to avoid noise coupling.
The PGND plane and the AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the
noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal
control circuit.
To get good thermal performance, it is recommended to use thermal vias beneath the TPS552882-Q1
connecting the PGND pin to the PGND plane, and the VOUT pin to a large VOUT area separately.
30
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10.2 Layout Example
trace on bottom layer
AGND plane on an inner layer
The first inner layer is the PGND plane
VOUT
AGND plane connects to PGND plane at the terminal of the capacitor at the VCC pin
AGND
PGND
19
18
17
16
15
14
13
12
20
11
26
21
25
24
9
23
NMOSFET
VIN
10
22
1
8
2
3
4
5
6
7
NMOSFET
PGND
AGND
图 10-1. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS552882-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11.6 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
32
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS552882-Q1
TPS552882-Q1
www.ti.com.cn
ZHCSMV3A – DECEMBER 2020 – REVISED DECEMBER 2021
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPS552882-Q1
33
PACKAGE OPTION ADDENDUM
www.ti.com
22-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS552882QRPMRQ1
ACTIVE
VQFN-HR
RPM
26
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
2882Q
TPS552882QWRPMRQ1
ACTIVE
VQFN-HR
RPM
26
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
52882W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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