TPS55340EVM-147

User's Guide SLVU742A – June 2012 – Revised August 2013 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module This user’s guide contains information for the TPS55340EVM-147 evaluation module (also called PWR147) as well as the TPS55340 DC/DC converter. The document includes the performance specifications, schematic, and the bill of materials for the TPS55340EVM-147. 1 2 3 4 5 6 Contents Background .................................................................................................................. 2 Performance Specification Summary ..................................................................................... 2 Modifications ................................................................................................................. 3 Test Setup and Results .................................................................................................... 3 Board Layout ............................................................................................................... 12 Schematic and Bill of Materials .......................................................................................... 15 List of Figures 1 TPS55340EVM-147 Efficiency ............................................................................................ 4 2 TPS55340EVM-147 Output Voltage Load Regulation ................................................................. 5 3 TPS55340EVM-147 Output Voltage Line Regulation .................................................................. 5 4 TPS55340EVM-147 VIN = 6V Transient Response ..................................................................... 6 5 TPS55340EVM-147 VIN = 18V Transient Response ................................................................... TPS55340EVM-147 Loop Response ..................................................................................... TPS55340EVM-147 VIN = 6V Output Ripple ............................................................................ TPS55340EVM-147 VIN = 18V Output Ripple ........................................................................... TPS55340EVM-147 DCM Output Ripple ................................................................................ TPS55340EVM-147 VIN = 18V Pulse-Skipping.......................................................................... TPS55340EVM-147 VIN = 6V Input Voltage Ripple ..................................................................... TPS55340EVM-147 VIN = 18V Input Voltage Ripple .................................................................. TPS55340EVM-147 Power Up With EN ............................................................................... TPS55340EVM-147 Power Down With EN ............................................................................ TPS55340EVM-147 Power Up With VIN ................................................................................ TPS55340EVM-147 Power Down With VIN ............................................................................ TPS55340EVM-147 Top-Side Assembly ............................................................................... TPS55340EVM-147 Top-Side Layout .................................................................................. TPS55340EVM-147 Internal Layer-1 Layout .......................................................................... TPS55340EVM-147 Internal Layer-2 Layout .......................................................................... TPS55340EVM-147 Bottom-Side Layout .............................................................................. TPS55340EVM-147 Schematic.......................................................................................... 6 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 7 8 8 9 9 10 10 11 11 12 13 13 14 14 15 15 List of Tables 1 Input Voltage and Output Current Summary ............................................................................ 2 2 Performance Specification Summary..................................................................................... 2 3 EVM Connectors and Test Points ........................................................................................ 4 4 TPS55340EVM-147 Bill of Materials .................................................................................... 16 SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 1 Background 1 www.ti.com Background The TPS55340 DC/DC converter is in typical applications a step-up boost converter, however this EVM uses it in a SEPIC topology. Rated input voltage and output current range for the evaluation module are given in Table 1. This evaluation module demonstrates the performance of the TPS55340 in an example application and can accommodate evaluation of other SEPIC applications supported by the TPS55340. This design shows a small printed-circuit-board area that can be achieved when designing with the TPS55340 regulator. However, appropriate sizing of the inductor and diode for the desired application can further reduce the board area. The switching frequency is externally set at a nominal 500kHz. The 40V, 5A, low-side MOSFET is incorporated inside the TPS55340 package along with the gate drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS55340 to achieve high efficiencies. The compensation components are external to the integrated circuit (IC). In this example application the absolute maximum input voltage for the TPS55340EVM-147 is 26V. Table 1. Input Voltage and Output Current Summary 2 EVM Input Voltage Range Maximum Output Current TPS55340EVM-147 VIN = 6V to 18V IOUTmax = 1A Performance Specification Summary Table 2 provides a summary of the TPS55340EVM-147 performance specifications. Specifications are given for an input voltage of VIN = 6V and VIN = 18V with an output voltage of 12V, unless otherwise specified. The ambient temperature is 25°C for all measurements, unless otherwise noted. Table 2. Performance Specification Summary Specification Test Conditions VIN voltage range Min Typ 6 12 Output voltage set point Line regulation Unit 18 12 IOUT = 500mA, VIN = 6V to 18V V V ±0.1% Operating frequency 500 Output current range .001 kHz 1 A Output over current limit (1) VIN = 6V 1.5 2.6 A Output over current limit (1) VIN = 18V 1.9 3.4 A Load regulation IOUT = 1mA to 1A, VIN = 6V to 18V IOUT = 250mA to 750mA, VIN = 6V Voltage change IOUT = 750mA to 250mA, VIN = 6V Voltage change Load transient response ±0.1% –480 Recovery time Recovery time mV 1 ms 480 mV 1 ms Loop bandwidth IOUT = 1A, VIN = 6V 6.3 kHz Phase margin IOUT = 1A, VIN = 6V 59.3 ° Loop bandwidth IOUT = 1A, VIN = 18V 13.2 kHz Phase margin IOUT = 1A, VIN = 18V 66.5 Output ripple voltage IOUT = 1A, VIN = 6V Output ripple voltage IOUT = 1A, VIN = 18V Maximum efficiency TPS55340EVM-147, VIN = 6V, IOUT = 350mA 92.1% Maximum efficiency TPS55340EVM-147, VIN = 18V, IOUT = 1A 92.1% (1) 2 Max ° 60 mVpp 40 mVpp The over current limit is dependent on the input voltage and based on peak current limit of the TPS55340. TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Modifications www.ti.com 3 Modifications These evaluation modules provide access to the features of the TPS55340. Some modifications to this module are possible. 3.1 Output Voltage Set Point The resistor divider network of R1 and R2 sets the output voltage. Keep R2 fixed at or close to 10kΩ. To change the output voltage of the EVM, change the value of resistor R1. Calculate the value of R1 for a specific output voltage by using Equation 1. æ V ö R1 = R2 ´ ç OUT - 1÷ è 1.229V ø (1) Note that VIN must be in a range so that the on-time is greater than the minimum controllable on-time (77ns typical), and the maximum duty cycle is less than 89% minimum and 93% typical. After adjusting the output voltage the maximum input voltage must be taken into consideration. The voltage on the internal FET, the SW pin, is equal to the sum of the input voltage and the output voltage. By using Equation 2 you can determine the recommended maximum input voltage. VIN max=38V-VOUT 3.2 (2) Maximum Output Current After adjusting input or output voltage settings, verify the maximum output current per Equation 3 below, where ILIM is the peak current limit of the TPS55340 and VF is the forward voltage drop of the external schottky diode (D1). This equation combines Equations 40, 42, and 44 from the datasheet. § · VIN min VOUT +VF × ¨ I LIM min¸ 2×fSW ×L VOUT +VF +VIN min ¹ © IOUT max= § · VOUT +1¸ ¨ © VIN min×EST ¹ 3.3 (3) Slow-Start Time The slow-start time can be adjusted by changing the value of C3. The EVM uses C3 = 0.047 µF as recommended on the data sheet to avoid any overshoot during start-up. A larger capacitance increases the slow-start time while a smaller capacitance decreases it. 3.4 Other Modifications Please see data sheet recommendations and equations when changing the switching frequency, input/output voltage range, input inductor, output capacitors or compensation. 4 Test Setup and Results This section describes how to properly connect, set up, and use the TPS55340EVM-147 evaluation module. Included are test results typical for the evaluation module covering efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, start-up and shut-down. SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 3 Test Setup and Results 4.1 www.ti.com Input/Output Connections The TPS55340EVM-147 is provided with input/output connectors and test points as shown in Table 3. Connect a power supply capable of supplying 5A to J6 through a pair of 20 AWG wires. The jumper across JP1 in the ON position (1-2) must be in place. Connect the load to J7 through a pair of 20 AWG wires. The maximum load current capability must be at least 1A. Wire lengths must be minimized to reduce losses in the wires. Header J1 provides a place to monitor the VIN input voltages with J3 providing a convenient ground reference. Use J2 to monitor the output voltage with J4 as the ground reference. Table 3. EVM Connectors and Test Points Reference Designator 2-pin header for VIN input voltage connections J2 2-pin header for VOUT input voltage connections J3,J4 4.2 Function J1 2-pin header for GND connections J5 2-pin header for synchronizing signal and ground J6 VIN input voltage connector. (See Table 1 for VIN range.) JP1 3-pin header for enable. Install jumper from pins 1-2 to enable or from pins 2-3 to disable. TP1 SW test point TP2 Test point between voltage divider network and output. Used for loop response measurements. TP3 COMP test point TP4 Output voltage test point at VOUT connector TP5 GND test point at VOUT connector Efficiency The efficiency of this EVM peaks at a load current of about 300mA at 6V input and 1A at 18V input, then decreases as the load current increases toward full load. Figure 1 shows the efficiency for the TPS55340EVM-147 at an ambient temperature of 25°C. 100 90 80 Efficiency (%) 70 60 50 40 30 20 VIN = 6V VIN = 12V VIN = 18V 10 0 0 0.5 Output Current (A) 1 G001 Figure 1. TPS55340EVM-147 Efficiency The efficiency may be lower at higher ambient temperatures, due to temperature variation in the drain-tosource resistance of the internal MOSFET. 4 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 4.3 Output Voltage Load Regulation Figure 2 shows the load regulation for the TPS55340EVM-147. 0.5 0.4 Output Voltage Deviation (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 VIN = 6V VIN = 12V VIN = 18V −0.4 −0.5 0 0.5 Output Current (A) 1 G002 Figure 2. TPS55340EVM-147 Output Voltage Load Regulation Measurements are for an ambient temperature of 25°C. 4.4 Output Voltage Line Regulation Figure 3 shows the line regulation for the TPS55340EVM-147 with a 24Ω (500mA) load. 0.5 0.4 Output Voltage Deviation (%) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 IOUT = 500mA −0.5 6 7 8 9 10 11 12 13 Output Current (A) 14 15 16 17 18 G003 Figure 3. TPS55340EVM-147 Output Voltage Line Regulation SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 5 Test Setup and Results 4.5 www.ti.com Load Transients Figure 4 and Figure 5 show the TPS55340EVM-147 response to load transients. The current step is from 25% to 75% of maximum rated load at a 6V input and a 18V input respectively. The current step slew rate is 10 mA/µs. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. C3: IOUT (500 mA/div) C4: VOUT AC Coupled (200 mV/div) Timebase = 500 µs/div Figure 4. TPS55340EVM-147 VIN = 6V Transient Response C3: IOUT (500 mA/div) C4: VOUT AC Coupled (200 mV/div) Timebase = 500 µs/div Figure 5. TPS55340EVM-147 VIN = 18V Transient Response 6 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 4.6 Loop Characteristics Figure 6 shows the TPS55340EVM-147 loop-response characteristics. Gain and phase plots are shown for VIN voltages of 6V and 18V with load currents of 1A. Gain (dB) 40 20 60 0 0 −20 −60 −40 −120 −60 100 1k 10k Frequency (Hz) 100k Phase (°) 180 VIN = 6V Gain VIN = 6V Phase VIN = 18V Gain 120 VIN = 18V Phase 60 −180 1M G006 Figure 6. TPS55340EVM-147 Loop Response 4.7 Output Voltage Ripple Figure 7 shows the TPS55340EVM-147 output voltage ripple and inductor current ripple. The output current is the rated full load of 1A and VIN = 6V. The ripple voltage is measured directly across the output capacitors. C2: SW (10.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VOUT AC Coupled (50 mV/div) Timebase = 2.00 µs/div Figure 7. TPS55340EVM-147 VIN = 6V Output Ripple SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 7 Test Setup and Results www.ti.com Figure 8 shows the TPS55340EVM-147 output voltage ripple and inductor current ripple. The output current is the rated full load of 1A and VIN = 18V. The ripple voltage is measured directly across the output capacitors. C2: SW (20.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VOUT AC Coupled (50 mV/div) Timebase = 2.00 µs/div Figure 8. TPS55340EVM-147 VIN = 18V Output Ripple Figure 9 shows the TPS55340EVM-147 output voltage ripple, inductor current ripple and switching waveform while operating in discontinuous conduction mode (DCM). The input voltage is 12V and the output is loaded with 60Ω. C2: SW (20.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VOUT AC Coupled (20 mV/div) Timebase (2.00 µs/div) Figure 9. TPS55340EVM-147 DCM Output Ripple 8 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Test Setup and Results www.ti.com 4.8 Pulse-Skipping Operation The TPS55340 features pulse-skipping for output regulation when operating at light loads. Figure 9 shows the output voltage ripple and the pulse-skipping at SW. The input voltage is 18V. C2: SW (20.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VOUT AC Coupled (50 mV/div) Timebase = 2.00 µs/div Figure 10. TPS55340EVM-147 VIN = 18V Pulse-Skipping 4.9 Input Voltage Ripple Figure 11 shows the TPS55340EVM-147 input voltage ripple. The output current is the rated full load of 1A at VIN = 6V. The ripple is measured directly across the input capacitor C2. C2: SW (10.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VIN AC Coupled (50 mV/div) Timebase = 2.00 µs/div Figure 11. TPS55340EVM-147 VIN = 6V Input Voltage Ripple SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 9 Test Setup and Results www.ti.com Figure 12 shows the TPS55340EVM-147 input voltage ripple. The output current is the rated full load of 1A at VIN = 18V. The ripple is measured directly across the input capacitor C2. C2: SW (20.0 V/div) C3: ILb (1.00 A/div) C4: ILa (1.00 A/div) C1: VIN AC Coupled (50 mV/div) Timebase = 2.00 µs/div Figure 12. TPS55340EVM-147 VIN = 18V Input Voltage Ripple 4.10 Powering Up and Down with EN Figure 13 shows the start-up waveforms for the TPS55340EVM-147. The input voltage is 6V, the EN goes high and the output voltage ramps from 0V to 12V. The load is 120Ω. C3: VIN (2.00 V/div) C4: EN (2.00 V/div) C1: SW (20 V/div) C2: VOUT (5.00 V/div) Timebase = 1.00 ms/div Figure 13. TPS55340EVM-147 Power Up With EN 10 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Test Setup and Results www.ti.com Figure 14 shows the shutdown waveforms for the TPS55340EVM-147. The input voltage is 6V. The EN goes low and the output voltage ramps from 12V to 0V. The load is 120Ω. C3: VIN (5.00 V/div) C4: EN (2.00 V/div) C1: SW (20 V/div) C2: VOUT (5.00 V/div) Timebase = 20.0 ms/div Figure 14. TPS55340EVM-147 Power Down With EN 4.11 Powering Up and Down with VIN Figure 15 shows the start-up waveforms for the TPS55340EVM-147. The input voltage ramps with the input voltage power supply and EN is tied to VIN. VIN ramps up, the converter starts switching and the output voltage ramps to 12V. The load is 120Ω. C3: VIN (2.00 V/div) C1: SW (10.0 V/div) C2: VOUT (5.00 V/div) Timebase = 2.00 ms/div Figure 15. TPS55340EVM-147 Power Up With VIN SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 11 Board Layout www.ti.com Figure 16 shows the shutdown waveforms for the TPS55340EVM-147. The input voltage ramps down with the input voltage power supply and EN is tied to VIN. When VIN is less than the 2.6V typical UVLO, the converter stops switching and the output voltage ramps down. The load is 120Ω. C3: VIN (2.00 V/div) C1: SW (10.0 V/div) C2: VOUT (5.00 V/div) Timebase = 5.00 ms/div Figure 16. TPS55340EVM-147 Power Down With VIN 5 Board Layout This section provides a description of the TPS55340EVM-147 board layout and layer illustrations. 5.1 Layout The board layout for the TPS55340EVM-147 is shown in Figure 17 through Figure 21. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2oz. copper. The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections for the remaining pins of the TPS55340 and a large area filled with ground. The internal layers and bottom are primarily ground with additional fill areas for VIN, and VOUT. The top-side ground traces connect to the bottom and internal ground planes with multiple vias placed around the board. Nine vias directly under the TPS55340 device provide a thermal path from the top-side ground plane to the bottom-side ground plane. Place the output decoupling capacitors (C8-C11) as close to the IC as possible. The copper area of the SW node is kept small to minimize noise. The vias near the diode D1 on the VOUT plane aid with thermal dissipation. Additionally, keep the voltage setpoint resistor divider components close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the J7 output connector. For the TPS55340, an additional input bulk capacitor may be necessary, depending on the EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency set resistor, slow-start capacitor, and compensation components terminate to ground by using a separate ground trace on the top and bottom connected power ground pour only at one point directly under the IC. 12 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Board Layout www.ti.com Figure 17. TPS55340EVM-147 Top-Side Assembly Figure 18. TPS55340EVM-147 Top-Side Layout SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 13 Board Layout www.ti.com Figure 19. TPS55340EVM-147 Internal Layer-1 Layout Figure 20. TPS55340EVM-147 Internal Layer-2 Layout 14 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Schematic and Bill of Materials www.ti.com Figure 21. TPS55340EVM-147 Bottom-Side Layout 6 Schematic and Bill of Materials This section presents the TPS55340EVM-147 schematic and bill of materials. 6.1 Schematic Figure 22 is the schematic for the TPS55340EVM-147. L1 12uH Lb C6 VIN J1 1 2 VIN 6-18V VIN 2 1 C2 10uF R6 0 C8 22uF 1 C9 22uF 1 1 C10 22uF J7 1 2 1 EN SS VIN C3 0.047uF 2 EN OFF VIN 3 NC PGND SW SW PGND TP5 12 11 PGND U1 10 NC TPS55340RTE 9 FREQ R4 95.3k FB 1 SW COMP JP1 ON 1 2 3 4 AGND GND 2 1 SYNC J3 PWPD 17 16 15 14 13 C7 0.1uF 5 6 7 8 TPS55340RTE SYNC J5 SYNC 1 2 VOUT 12V, 1A C11 2 GND SYNC GND J2 D1 TP1 C1 J6 TP4 2.2uF La TP2 R5 49.9 VOUT GND J4 2 1 GND R1 86.6k TP3 R3 2.37k C5 R2 10k 1 C4 0.1uF 1 Not Populated Figure 22. TPS55340EVM-147 Schematic SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module Copyright © 2012–2013, Texas Instruments Incorporated 15 Schematic and Bill of Materials 6.2 www.ti.com Bill of Materials Table 4 presents the bill of materials for the TPS55340EVM-147. Table 4. TPS55340EVM-147 Bill of Materials QTY RefDes Value Description Size Part Number MFR 0 C1 Open Capacitor, Ceramic, 35V, X7R, 10% 1210 STD STD 1 C2 10uF Capacitor, Ceramic, 36V, X7R, 10% 1210 GRM32ER7YA106KA12L Murata 1 C3 0.047uF Capacitor, Ceramic, 10V, X7R, 10% 0603 STD STD 1 C4 0.1uF Capacitor, Ceramic, 10v, X7R, 10% 0603 STD STD 0 C5 Open Capacitor, Ceramic, 10V, X7R, 10% 0603 STD STD 1 C6 2.2uF Capacitor, Ceramic, 50V, X7R, 10% 1210 STD STD 1 C7 0.1uF Capacitor, Ceramic, 50V, X7R, 10% 0603 STD STD 3 C8-C10 22uF Capacitor, Ceramic, 50V, X7R, 10% 1210 STD STD 0 C11 Open Capacitor, Ceramic, 50V, X7R, 10% 1210 GRM32ER71H475KA88L Murata 1 D1 B340B Diode, Schottky Barrier Rectifier, 3-A, 40-V SMB B340B-13-F Diodes Inc 5 J1-5 PEC025AAN Header, Male 2-pin, 100mil spacing 0.100 x 2 inch PEC025AAN Suffins 2 J6-7 ED555/2DS Terminal BLock, 2-pin, 6-A, 3.5mm 0.27 x 0.25 inch ED555/205 OST 1 JP1 PEC035AAN Header, Male 3-pin, 100mil spacing 0.100 x 3 inch PEC035AAN Sullins 1 L1 12uH Inductor, SMT, 6.8A, 74milliohm, ±20% 0.484 x 0.484 inch MSD1260 -123ML Coilcraft 1 R1 86.6k Resistor, Chip, 1/16W, 1% 0603 STD STD 1 R2 10.0k Resistor, Chip, 1/16W, 1% 0603 STD 1 R3 2.37k Resistor, Chip, 1/16W, 1% 0603 STD 1 R4 95.3k Resistor, Chip, 1/16W, 1% 0603 STD 1 R5 49.9 Resistor, Chip, 1/16W, 1% 0603 STD 1 R6 0 Resistor, Chip, 1/16W, 1% 0603 STD 1 SH1 Short jumper, 100mil 0.100 inch 929950-00 1 TP5 5001 Test Point, Black, Thru Hole Color Keyed 0.100 x 0.100 inch Keystone 3 TP2-4 5000 Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 inch Keystone 0 TP1 Open Test Point, Red, Thru Hole Color Keyed 0.100 x 0.100 inch Keystone TPS55340RTE IC, 5A 40V Boost Converter with Soft-start and QFN-16 Programmable Switching Frequency TPS55340RTE TI PCB, 2.6 In x 1.5 In x 0.062 In PWR147 Any 1 U1 1 – 3M Notes: 1. These assemblies are ESD sensitive, ESD precautions shall be observed. 2. These assemblies must be clean and free from flux and all contaminants. Use of no clean flux is not acceptable. 3. These assemblies must comply with workmanship standards IPC-A-610 Class 2. 4. Ref designators marked with an asterisk ('**') cannot be substituted. All other components can be substituted with equivalent MFG's components. 6.3 Reference 1. TPS55340, Integrated 5-A 40-V Boost/SEPIC/Flyback Converter with Adjustable Switching Frequency data sheet (SLVSBD4) 16 TPS55340EVM-147, 6V to 18V Input, 12V Output SEPIC Evaluation Module SLVU742A – June 2012 – Revised August 2013 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. 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Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment. FCC Interference Statement for Class A EVM devices This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help. For EVMs annotated as IC – INDUSTRY CANADA Compliant This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Concerning EVMs including radio transmitters This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement. Concernant les EVMs avec appareils radio Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER 【Important Notice for Users of EVMs for RF Products in Japan】 】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 本開発キットは技術基準適合証明を受けておりません。 本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 実験局の免許を取得後ご使用いただく。 技術基準適合証明を取得後ご使用いただく。 なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。 　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・インスツルメンツ株式会社 東京都新宿区西新宿６丁目２４番１号 西新宿三井ビル http://www.tij.co.jp SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product. Your Sole Responsibility and Risk. You acknowledge, represent and agree that: 1. 2. 3. 4. You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes. You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates, contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. Since the EVM is not a completed product, it may not meet all applicable regulatory and safety compliance standards (such as UL, CSA, VDE, CE, RoHS and WEEE) which may normally be associated with similar items. You assume full responsibility to determine and/or assure compliance with any such standards and related certifications as may be applicable. You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even if the EVM should fail to perform as described or expected. You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials. Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable in electronic measurement and diagnostics normally found in development environments should use these EVMs. Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected. Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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