TPS55340PWP

TPS55340 SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 TPS55340 Integrated 5-A Wide Input Range Boost/SEPIC/Flyback DC/DC Regulator 1 Features 3 Description • • • • • • • • • • • The TPS55340 is a monolithic, nonsynchronous, switching regulator with integrated 5-A, 40-V power switch. The device can be configured in several standard switching-regulator topologies, including boost, SEPIC, and isolated flyback. The device has a wide input voltage range to support applications with input voltage from multicell batteries or regulated 3.3-V, 5-V, 12-V, and 24-V power rails. • • 2 Applications • • • • • 3.3-V, 5-V, 12-V, 24-V power conversion Boost, SEPIC, and flyback topologies Thunderbolt port, USB type-C power delivery, power docking for tablets, and portable PCs Industrial power systems ADSL modems The TPS55340 regulates the output voltage with current mode PWM (pulse width modulation) control, and has an internal oscillator. The switching frequency of PWM is set by either an external resistor or by synchronizing to an external clock signal. The user can program the switching frequency from 100 kHz to 1.2 MHz. The device features a programmable soft-start function to limit inrush current during start-up and has other built-in protection features including cycleby-cycle overcurrent limit and thermal shutdown. The TPS55340 is available in a small 3-mm × 3-mm 16-pin QFN as well as 14-pin HTSSOP packages with PowerPAD for enhanced thermal performance. The 5-A, 40-V TPS55340 boost converter in the HTSSOP-14 package is pin-to-pin compatible with the 3-A, 40-V TPS61175, and it extends the maximum input voltage from 18 V to 32 V. Device Information PART NUMBER TPS55340 (1) L VIN D PACKAGE(1) BODY SIZE (NOM) HTSSOP (14) 5.00 mm × 4.40 mm WQFN (16) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. 100 VOUT 95 CI CO TPS55340 VIN SW EN SW FREQ SW RSH SS FB COMP PGND SYNC PGND AGND PGND CSS RFREQ RC RSL 90 Efficiency (%) • Internal 5-A, 40-V low-side MOSFET switch 2.9-V to 32-V input voltage range ±0.7% reference voltage 0.5-mA operating quiescent current 2.7-µA shutdown supply current Fixed frequency current mode PWM control Frequency adjustable from 100 kHz to 1.2 MHz Synchronization capability to external clock Adjustable soft-start time Pulse skipping for higher efficiency at light loads Cycle-by-cycle current limit, thermal shutdown, and UVLO protection QFN-16 (3-mm × 3-mm) and HTSSOP-14 packages with PowerPAD™ Wide –40°C to 150°C operating TJ range Create a custom design using the TPS55340 with the WEBENCH Power Designer 85 VOUT = 24 V fSW = 600 kHz 80 75 70 65 VIN = 15 V VIN = 12 V VIN = 5 V 60 CC 55 50 Typical Application (Boost) 0 0.4 0.8 1.2 1.6 Output Current (A) 2 2.4 G031 Efficiency vs Output Current An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Typical Characteristics................................................ 6 7 Detailed Description........................................................9 7.1 Overview..................................................................... 9 7.2 Functional Block Diagram........................................... 9 7.3 Feature Description.....................................................9 7.4 Device Functional Modes..........................................12 8 Application and Implementation.................................. 13 8.1 Application Information............................................. 13 8.2 Typical Applications.................................................. 13 9 Power Supply Recommendations................................27 10 Layout...........................................................................28 10.1 Layout Guidelines................................................... 28 10.2 Layout Example...................................................... 28 10.3 Thermal Considerations..........................................28 11 Device and Documentation Support..........................29 11.1 Device Support........................................................29 11.2 Receiving Notification of Documentation Updates.. 29 11.3 Support Resources................................................. 29 11.4 Trademarks............................................................. 29 11.5 Electrostatic Discharge Caution.............................. 29 11.6 Glossary.................................................................. 29 12 Mechanical, Packaging, and Orderable Information.................................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2019) to Revision E (September 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document. ................1 Changes from Revision C (October 2014) to Revision D (June 2019) Page • Added text note under pin configuration diagrams. ........................................................................................... 3 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 SW SW NC PGND 5 Pin Configuration and Functions 16 15 14 13 SW 1 12 PGND VIN 2 11 PGND EN 3 10 NC SS 4 9 PowerPAD 1 14 PGND SW 2 13 PGND VIN 3 12 PGND EN 4 11 NC SS 5 10 FREQ 5 6 7 8 SYNC 6 9 FB AGND COMP FB PowerPAD SYNC FREQ SW AGND 7 8 COMP TI recommends connecting NC with AGND. TI recommends connecting NC with AGND. Figure 5-1. RTE Package 16-Pin WQFN Top View Figure 5-2. PWP Package 14-Pin HTSSOP (Top View) Table 5-1. Pin Functions PIN NAME QFN-16 DESCRIPTION HTSSOP-14 AGND 6 7 Signal ground of the IC COMP 7 8 Output of the transconductance error amplifier. An external RC network connected to this pin compensates the regulator feedback loop. EN 3 4 Enable pin. When the voltage of this pin falls below the enable threshold for more than 1 ms, the IC turns off. FB 8 9 Error amplifier input and feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider to program the output voltage. FREQ 9 10 Switching frequency program pin. An external resistor connected between the FREQ pin and AGND sets the switching frequency. NC 10, 14 11 Reserved pin that must be connected to ground PGND 11, 12, 13 12, 13, 14 Power ground of the IC. It is connected to the source of the internal power MOSFET switch. PowerPAD — — The PowerPAD should be soldered to the AGND. If possible, use thermal vias to connect to internal ground plane for improved power dissipation. SS 4 5 Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start timing. SW 1, 15, 16 1, 2 SW is the drain of the internal power MOSFET. Connect SW to the switched side of the boost or SEPIC inductor or the flyback transformer. SYNC 5 6 Switching frequency synchronization pin. An external clock signal can be used to set the switching frequency between 200 kHz and 1.0 MHz. If not used, this pin should be tied to AGND. VIN 2 3 The input supply pin to the IC. Connect VIN to a supply voltage between 2.9 V and 32 V. It is acceptable for the voltage on the pin to be different from the boost power stage input. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 3 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating temperature range (unless otherwise noted)(1) Supply voltages on pin VIN(2) Voltage on pin EN(2) Voltage on pins FB, FREQ, and COMP(2) Voltage on pin SS(2) Voltage on pin SYNC(2) Voltage on pin SW(2) MIN MAX UNIT –0.3 34 V –0.3 34 V –0.3 3 V –0.3 5 V –0.3 7 V –0.3 40 V Operating junction temperature –40 150 °C Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all V(ESD) (1) (2) Electrostatic discharge pins(1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions MIN NOM MAX UNIT VIN Input voltage range 2.9 32 V VOUT Output voltage range VIN 38 V VEN EN voltage range 0 32 V VSYN External switching frequency logic input range 0 5 V TA Operating free-air temperature –40 125 °C TJ Operating junction temperature –40 150 °C 6.4 Thermal Information TPS55340 THERMAL METRIC(1) HTSSOP (14 PINS) RθJA Junction-to-ambient thermal resistance 43.3 43.2 RθJC(top) Junction-to-case (top) thermal resistance 38.7 33.3 RθJB Junction-to-board thermal resistance 14.5 28.3 ψJT Junction-to-top characterization parameter 0.4 1.3 ψJB Junction-to-board characterization parameter 14.5 28.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 3.5 3.9 (1) 4 QFN (16 PINS) UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 6.5 Electrical Characteristics VIN = 5 V, TJ = –40°C to 150°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range 2.9 32 IQ Operating quiescent current into VIN Device nonswitching, VFB = 2 V 0.5 ISD Shutdown current EN = GND 2.7 VUVLO Undervoltage lockout threshold VIN falling Vhys Undervoltage lockout hysteresis V mA 10 µA 2.5 2.7 V 120 140 160 mV ENABLE AND REFERENCE CONTROL VEN EN threshold voltage EN rising input 0.9 1.08 1.30 V VEN EN threshold voltage EN falling input 0.74 0.92 1.125 V VENh EN threshold hysteresis REN EN pulldown resistor 1600 kΩ Toff Shutdown delay, SS discharge VSYNh SYN logic high voltage VSYNl SYN logic low voltage 0.16 400 EN high to low 950 V 1.0 ms 1.2 V 0.4 V VOLTAGE AND CURRENT CONTROL VREF Voltage feedback regulation voltage IFB Voltage feedback input bias current Isink COMP pin sink current Isource COMP pin source current VCCLP COMP pin clamp voltage VCTH COMP pin threshold Gea Error amplifier transconductance Rea Error amplifier output resistance fea Error amplifier crossover frequency 1.204 1.229 1.254 1.220 1.229 1.238 TA = 25°C 1.6 20 VFB = VREF + 200 mV, VCOMP = 1 V 42 µA VFB = VREF – 200 mV, VCOMP = 1 V 42 µA High Clamp, VFB = 1 V 3.1 TA = 25°C Low Clamp, VFB = 1.5 V 0.75 Duty cycle = 0% 1.04 240 360 V nA V V 440 µS 10 MΩ 500 kHz FREQUENCY fSW Frequency Dmax Maximum duty cycle VFREQ FREQ pin voltage Tmin_on Minimum on pulse width RFREQ = 480 kΩ 75 94 130 RFREQ = 80 kΩ 460 577 740 920 1140 1480 89% 96% RFREQ = 40 kΩ VFB = 1.0 V, RFREQ = 80 kΩ kHz 1.25 V RFREQ = 80 kΩ 77 ns VIN = 5 V 60 110 VIN = 3 V 70 120 POWER SWITCH RDS(ON) N-channel MOSFET on-resistance ILN_NFET N-channel leakage current VDS = 25 V, TA = 25°C mΩ 2.1 µA 7.75 A OCP and SS ILIM N-channel MOSFET current limit D = Dmax ISS Soft-start bias current VSS = 0 V 5.25 6.6 6 µA THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold 165 °C Thysteresis Thermal shutdown threshold hysteresis 15 °C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 5 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 6.6 Typical Characteristics VIN = 5 V, TA = 25°C (unless otherwise noted) 8 Current Limit Threshold (A) Transconductance (µA/V) 400 380 360 340 320 7 6 5 4 3 2 300 −50 −25 0 25 50 75 Temperature (°C) 100 125 1 −50 150 Figure 6-1. Error Amplifier Transconductance vs Temperature 125 150 G002 VIN = 3 V Resistance (mΩ) Voltage Reference (V) 100 100 1.228 1.226 1.224 80 60 VIN = 12 V 40 VIN = 5 V 20 1.22 −50 −25 0 25 50 75 Temperature (°C) 100 125 0 −50 150 −25 0 G003 Figure 6-3. Feedback Voltage Reference vs Temperature 25 50 75 Temperature (°C) 1600 1400 1400 1200 Frequency (kHz) 1000 800 600 400 100 Resistance (kΩ) 500 150 G004 800 600 RFREQ = 40 kΩ RFREQ = 80 kΩ RFREQ = 480 kΩ 400 0 −50 G005 Figure 6-5. Frequency vs FREQ Resistance 125 1000 200 200 30 100 Figure 6-4. RDS(ON) vs Temperature 1200 Frequency (kHz) 25 50 75 Temperature (°C) 120 1.222 6 0 Figure 6-2. Switch Current Limit vs Temperature 1.23 0 −25 G001 −25 0 25 50 75 Temperature (°C) 100 125 150 G006 Figure 6-6. Frequency vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 400 700 350 600 RFREQ = 80 kΩ 500 Frequency (kHz) Frequency (kHz) 300 250 200 150 400 100 200 50 100 0 0 5 10 15 20 25 30 Voltage on the VIN Pin (V) 35 0 −50 40 100 125 150 G007 2.66 Input Voltage (V) COMP Voltage (V) 25 50 75 Temperature (°C) 2.7 3 2.5 COMP Pin Clamp High COMP Pin Clamp Low 2 1.5 2.62 UVLO Start UVLO Stop 2.58 2.54 1 −25 0 25 50 75 Temperature (°C) 100 125 2.5 −50 150 −25 0 G008 Figure 6-9. COMP Clamp Voltage vs Temperature 25 50 75 Temperature (°C) 100 125 150 G009 Figure 6-10. Input Voltage UVLO vs Temperature 1.3 100 RFREQ = 80 kΩ EN Voltage Rising EN Voltage Falling Maximum Duty Cycle (%) 1.2 Enable Voltage (V) 0 Figure 6-8. Nonfoldback Frequency vs Foldback Frequency 3.5 1.1 1 0.9 0.8 0.7 −50 −25 D006 Figure 6-7. Minimum Switching Frequency for Quick Recovery from Frequency Foldback 0.5 −50 Non-Foldback Foldback 300 −25 0 25 50 75 Temperature (°C) 100 125 150 99 98 97 96 95 94 −50 G010 Figure 6-11. Enable Voltage vs Temperature −25 0 25 50 75 Temperature (°C) 100 125 150 G011 Figure 6-12. Maximum Duty Cycle vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 7 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 100 8 RFREQ = 80 kΩ 7 Shutdown Current (µA) Minimum On Time (ns) 95 90 85 80 75 70 −50 6 5 4 3 2 −25 0 25 50 75 Temperature (°C) 100 125 1 −50 150 −25 0 25 50 75 Temperature (°C) G012 Figure 6-13. Minimum On-Time vs Temperature 100 125 150 G013 Figure 6-14. Shutdown Current vs Temperature 2.1 Supply Current (mA) 1.8 1.5 Switching Non-Switching 1.2 0.9 0.6 0.3 −50 −25 0 25 50 75 Temperature (°C) 100 125 150 G014 Figure 6-15. Supply Current vs Temperature 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 7 Detailed Description 7.1 Overview The TPS55340 device is a monolithic, nonsynchronous, switching regulator with an integrated 5-A, 40-V power switch. The device can be configured in several standard switching-regulator topologies, including boost, SEPIC, and isolated flyback. The device has a wide input voltage range to support applications with input voltage from multicell batteries or regulated 3.3-V, 5-V, 12-V, and 24-V power rails. 7.2 Functional Block Diagram VIN SW FB Error Amp EN 1.229V Reference COMP PWM Control Ramp Generator Gate Driver Lossless Current Sense S Oscillator SS FREQ SYNC AGND PGND 7.3 Feature Description 7.3.1 Operation If designed as a boost converter, the TPS55340 device regulates the output with current-mode, pulse-widthmodulation (PWM) control. The PWM control circuitry turns on the switch at the beginning of each oscillator clock cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current reaches a threshold level set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased to allow the inductor current to flow to the output. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats every switching cycle. The duty cycle of the converter is determined by the PWM control comparator which compares the error amplifier output and the current signal. The oscillator frequency is programmed by the external resistor or synchronized to an external clock signal. A ramp signal from the oscillator is added to the inductor current ramp to provide slope compensation. Slope compensation is required to avoid subharmonic oscillation that is intrinsic to peak-current mode control at duty cycles higher than 50%. If the inductor value is too small, the internal slope compensation may not be adequate to maintain stability. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 9 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 The PWM control feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network connected to the COMP pin is chosen for feedback loop stability and optimum transient response. 7.3.2 Switching Frequency The switching frequency is set by a resistor (RFREQ) connected to the FREQ pin of the TPS55340. The relationship between the timing resistance RFREQ and frequency is shown in the Figure 6-5. Do not leave this pin open. A resistor must always be connected from the FREQ pin to ground for proper operation. The resistor value required for a desired frequency can be calculated using Equation 1. RFREQ(kΩ) = 57500 × ƒsw(kHz)–1.03 (1) For the given resistor value, the corresponding frequency can be calculated by Equation 2. ƒsw(kHz) = 41600 × RFREQ(kΩ)–0.97 (2) The TPS55340 switching frequency can be synchronized to an external clock signal that is applied to the SYNC pin. The required logic levels of the external clock are shown in Section 6.3. The recommended duty cycle of the clock is in the range of 10% to 90%. A resistor must be connected from the FREQ pin to ground when the converter is synchronized to the external clock and the external clock frequency must be within ±20% of the corresponding frequency set by the resistor. For example, if the frequency programmed by the FREQ pin resistor is 600 kHz, the external clock signal should be in the range of 480 kHz to 720 kHz. With a switching frequency below 280 kHz (typical) after the TPS55340 enters frequency foldback as described in Section 7.3.3, if a load remains when the overcurrent condition is removed, then the output may not recover to the set value. For the output to return to the set value, the load must be removed completely or the TPS55340 power cycled with the EN pin or VIN pin. Select a nominal switching frequency of 350 kHz for quicker recovery from frequency foldback. 7.3.3 Overcurrent Protection and Frequency Foldback The TPS55340 provides cycle-by-cycle overcurrent protection that turns off the power switch once the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the next switch cycle. During an overcurrent event, the output voltage begins to drop as a function of the load on the output. When the FB voltage through the feedback resistors drops lower than 0.9 V, the switching frequency is automatically reduced to 1/4 of the normal value. Figure 6-8 shows the nonfoldback frequency with an 80-kΩ timing resistor and the corresponding foldback frequency. The switching frequency does not return to normal until the overcurrent condition is removed and the FB voltage increases above 0.9 V. The frequency foldback feature is disabled during soft-start. 7.3.3.1 Minimum On-Time and Pulse Skipping The TPS55340 PWM control system has a minimum PWM pulse width of 77 ns (typical). This minimum on-time determines the minimum duty cycle of the PWM for any set switching frequency. When the voltage regulation loop of the TPS55340 requires a minimum on-time pulse width less than 77 ns, the IC enters pulse skipping mode. In this mode, the device will hold the power switch off for several switching cycles to prevent the output voltage from rising above the desired regulated voltage. This operation typically occurs in light load conditions when the PWM operates in discontinuous conduction mode. Pulse skipping increases the output ripple as shown in Figure 8-7. 7.3.4 Voltage Reference and Setting Output Voltage An internal voltage reference provides a precise 1.229-V voltage reference at the error amplifier noninverting input. To set the output voltage, select the FB pin resistor RSH and RSL according to Equation 3. æR ö VOUT = 1.229 V ´ ç SH + 1÷ è R SL ø 10 Submit Document Feedback (3) Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS55340 TPS55340 www.ti.com SLVSBD4E – MAY 2012 – REVISED SEPTEMBER 2021 7.3.5 Soft-Start The TPS55340 has a built-in soft-start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current source (6 µA, typical) charges a capacitor (CSS) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the peak current and duty cycle of PWM controller. Limiting the peak switch current during start-up with a slow ramp on the SS pin will reduce in-rush current and output voltage overshoot. Once the capacitor reaches 1.8 V, the soft-start cycle is completed and the soft-start voltage no longer clamps the error amplifier output. When the EN is pulled low for at least 1 ms, the IC enters the shutdown mode and the SS capacitor is discharged through a 5-kΩ resistor to prepare for the next soft-start sequence. 7.3.6 Slope Compensation The TPS55340 has internal slope compensation to prevent subharmonic oscillations. The sensed current slope of boost converter can be expressed as Equation 4: V Sn = IN ´ RSENSE L (4) The slope compensation dv/dt can be calculated using Equation 5. Se = 0.32 V RFREQ 0.5 mA + 16 ´ (1 - D) ´ 6 pF 6 pF (5) In a converter with current mode control, in addition to the output voltage feedback loop, the inner current loop including the inductor current sampling effect as well as the slope compensation on the small signal response should be taken into account, which can be modeled as seen in Equation 6: He(s) = 1+ éæ S s ´ êç 1 + e Sn êëçè 1 ù ö ÷ ´ (1 - D) - 0.5 ú ÷ úû ø + fsw s2 (p ´ fsw ) 2 (6) where • • • RSENSE (15 mΩ) is the equivalent current sense resistor. RFREQ is timing resistor used to set frequency. D is the duty cycle. Note If Sn