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TPS560430-Q1
SLUSDF5A – JANUARY 2019 – REVISED AUGUST 2019
TPS560430-Q1 SIMPLE SWITCHER® 4-V to 36-V, 600-mA Synchronous Buck Converter
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
Qualified for automotive applications
AEC-Q100 Qualified
- Temperature grade 1: –40°C to 125°C ambient
operating temperature range
- ESD HBM classification level 2
- ESD CDM classification level C5
Configured for rugged automotive applications
– Input voltage range: 4 V to 36 V
– 600-mA continuous output current
– Minimum switching-on time: 60 ns
– Fixed 2.1MHz frequency
– 98% maximum duty cycle
– Support startup with pre-biased output
– Short circuit protection with hiccup mode
– ±0.5% tolerance voltage reference at room
temperature
– Precision enable
Small solution size and ease of use
– Integrated synchronous rectification
– Internal compensation for ease of use
– SOT-23-6 package
Two modes in pin-to-pin compatible package
– PFM and forced PWM (FPWM) options
Create a custom design using the TPS560430-Q1
with the WEBENCH® Power Designer
Camera
On-board charger
Automotive head unit
USB charger
General purpose wide VIN power supplies
3 Description
The TPS560430-Q1 is a wide-VIN, easy to use
synchronous buck converter capable of driving up to
600-mA load current. With a wide input range of 4 V
to 36 V, the device is suitable for a wide range of
automotive applications for power conditioning from
an unregulated source.
TPS560430-Q1 operates at 2.1-MHz switching
frequency to support use of relatively small inductors
for an optimized solution size. It has Eco-mode
version to realize high efficiency at light load and
FPWM version to achieve constant frequency, small
output voltage ripple over the full load range. Softstart and compensation circuits are implemented
internally which allows the device to be used with
minimum external components.
The device has built-in protection features, such as
cycle-by-cycle current limit, hiccup mode short-circuit
protection, and thermal shutdown in case of
excessive power dissipation. The TPS560430-Q1 is
available in SOT-23-6 package.
Device Information
(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS560430-Q1
SOT-23-6
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Output Current
VOUT = 5 V, 2100 kHz, PFM
Simplified Schematic
VIN up to 36 V
VIN
100
CB
90
CIN
CBOOT
EN
VOUT
SW
RFBT
GND
Efficiency (%)
80
L
70
60
50
FB
VIN=8V
VIN=12V
VIN=24V
VIN=36V
COUT
RFBB
40
30
0.001
0.01
0.1
IOUT(A)
1
D001
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS560430-Q1
SLUSDF5A – JANUARY 2019 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (January 2019) to Revision A
•
2
Page
Changed marketing status from Advance Information to Production Data. .......................................................................... 1
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5 Device Comparison Table
ORDERABLE PART NUMBER
Frequency
PFM or FPWM
Output
TPS560430YQDBVRQ1
2.1 MHz
PFM
Adjustable
TPS560430YFQDBVRQ1
2.1 MHz
FPWM
Adjustable
6 Pin Configuration and Functions
DBV Package
6-Pin SOT-23-6
Top View
CB
1
6
SW
GND 2
5
VIN
3
4
EN
FB
Pin Functions
PIN
(1)
TYPE
(1)
DESCRIPTION
NAME
NO
CB
1
P
Bootstrap capacitor connection for high-side FET driver. Connect a high quality 100nF
capacitor from this pin to the SW pin.
GND
2
A
Power ground terminals, connected to the source of low-side FET internally. Connect to system
ground, ground side of CIN and COUT. Path to CIN must be as short as possible.
FB
3
A
Feedback input to the converter. Connect a resistor divider to set the output voltage. Never
short this terminal to ground during operation.
EN
4
A
Precision enable input to the converter. Do not float. High = on, Low = off. Can be tied to VIN.
Precision enable input allows adjustable UVLO by external resistor divider.
VIN
5
P
Supply input terminal to internal bias LDO and high-side FET. Connect to input supply and
input bypass capacitors CIN. Input bypass capacitors must be directly connected to this pin and
GND.
SW
6
P
Switching output of the converter. Internally connected to source of the high-side FET and drain
of the low-side FET. Connect to power inductor.
A = Analog, P = Power, G = Ground.
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40 °C to 125 °C (unless otherwise noted)
PARAMETER
Input Voltages
Output Voltages
MIN
MAX
VIN to GND
–0.3
38
EN to GND
–0.3
VIN + 0.3
FB to GND
–0.3
5.5
SW to GND
–0.3
VIN + 0.3
SW to GND less than 10 ns transient
–3.5
38
CB to SW
–0.3
5.5
–40
150
–65
150
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(2)
(1)
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Human-body model (HBM), per AEC Q100-002
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
PARAMETER
Input Voltages
MIN
MAX
VIN to GND
4
36
EN
0
VIN
FB
0
4.5
(1)
UNIT
V
Output Voltage
VOUT
1.0
95% of VIN
V
Output Current
IOUT
0
600
mA
Temperature
Operating junction temperature range, TJ
–40
+125
°C
(1)
Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific
performance limits. For guaranteed specifications, see Electrical Characteristics
7.4 Thermal Information
THERMAL METRIC
(1)
DBV (6 PINS)
UNIT
Junction-to-ambient thermal resistance
173
°C/W
RθJC_T
Junction-to-case (TOP) thermal resistance
116
°C/W
RθJC_B
Junction-to-case (BOTTOM) thermal resistance
31
°C/W
ψJT
Junction-to-top characterization parameter
20
°C/W
ψJB
Junction-to-board characterization parameter
30
°C/W
RθJA
(1)
(2)
4
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a specified JEDEC board. They do not represent the
performance obtained in an actual application.
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7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN
Operation input voltage
VIN_UVLO
Undervoltage lockout thresholds
4
36
V
Rising threshold
3.55
3.75
4.00
Falling threshold
3.25
3.45
3.65
V
Hysteresis
0.3
80
120
µA
3
10
µA
1.23
1.36
V
1.1
1.22
V
10
200
nA
IQ
Operating quiescent current (nonswitching)
PFM version, VEN = 3.3 V, VFB =
1.1V
ISHDN
Shutdown current
VEN = 0 V
ENABLE (EN PIN)
VEN_H
Enable rising threshold voltage
1.1
VEN_L
Enable falling threshold voltage
0.95
VEN_HYS
Enable hysteresis voltage
IEN
Leakage current at EN pin
0.13
VEN = 3.3 V
V
VOLTAGE REFERENCE (FB PIN)
VREF
Reference voltage
IFB
Leakage current at FB pin
TJ = 25 °C
0.995
1.00
1.005
V
TJ = –40 °C to 125 °C
0.985
1.00
1.015
V
0.2
50
nA
VFB = 1.2 V
CURRENT LIMITS AND HICCUP
IHS_LIMIT
Peak inductor current limit
0.8
1.1
1.4
A
ILS_LIMIT
Valley inductor current limit
0.62
0.8
0.98
A
ILS_ZC
Zero cross current (PFM version)
ILS_NEG
Negative current limit (FPWM
version)
-0.7
-0.5
VHICCUP
Hiccup threshold of FB pin
20
% of reference voltage
40%
mA
-0.3
A
INTEGRATED MOSFETS
RDS_ON_HS
High-side MOSFET ON-resistance
TJ = 25 °C, VIN = 12 V
450
mΩ
RDS_ON_LS
Low-side MOSFET ON-resistance
TJ = 25 °C, VIN = 12 V
240
mΩ
170
°C
12
°C
THERMAL SHUTDOWN
(1)
TSHDN
Thermal shutdown threshold
THYS
Hysteresis
(1)
Ensured by design.
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7.6 Timing Requirements
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
TSS
Internal soft-start time
The time of internal reference to
increase from 10% to 90% of VREF,
VIN = 12 V
1.8
ms
Hiccup time
VIN = 12 V
135
ms
HICCUP
THICCUP
7.7 Switching Characteristics
Limits apply over the recommended operating junction temperature (TJ ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 4 V to 36 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING NODE (SW PIN)
tON_MIN
Minimum turn-on time
IOUT = 600 mA
60
tOFF_MIN
Minimum turn-off time
IOUT = 600 mA
100
ns
ns
tON_MAX
Maximum turn-on time
7.5
µs
OSCILLATOR
fSW
6
Oscillator frequency
2.1-MHz version
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1.785
2.1
2.415
MHz
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7.8 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
VIN = 12 V, TA = 25°C, unless otherwise specified.
60
50
40
FPWM, 8 VIN
FPWM, 12 VIN
FPWM, 24 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
30
20
10
0
0.0001
0.001
0.01
IOUT (A)
0.1
60
50
40
FPWM, 8 VIN
FPWM, 12 VIN
FPWM, 24 VIN
PFM, 8 VIN
PFM, 12 VIN
PFM, 24 VIN
30
20
10
0
0.0001
1
0.001
0.01
IOUT (A)
D011
VOUT = 3.3 V
1
D012
VOUT = 5 V
Figure 1. Efficiency vs Load Current
Figure 2. Efficiency vs Load Current
3.37
3.37
VIN=8V
VIN=12V
VIN=24V
VIN=36V
IOUT=0mA
IOUT=100mA
IOUT=300mA
IOUT=600mA
3.36
VOUT(V)
3.36
VOUT(V)
0.1
3.35
3.34
3.35
3.34
3.33
3.33
0
0.1
0.2
0.3
IOUT(A)
0.4
0.5
0.6
0
5
10
SLUS
VOUT = 3.3 V
FPWM version
15
20
VIN(V)
25
30
40
SLUS
VOUT = 3.3 V
Figure 3. Load Regulation
35
FPM version
Figure 4. Line Regulation
80
1/16/2019
5.4
75
IQ (PA)
VOUT(V)
5
4.6
70
4.2
65
IOUT=0mA
IOUT=100mA
IOUT=300mA
IOUT=600mA
3.8
3.4
4
4.5
5
5.5
VIN(V)
6
VOUT = 5 V
6.5
7
60
-50
SLUS
FPWM version
VFB = 1.1 V
Figure 5. Dropout
0
50
Temperature (qC)
100
150
D007
PFM verison
Figure 6. IQ vs Temperature
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Typical Characteristics (continued)
VIN = 12 V, TA = 25°C, unless otherwise specified.
1.0002
3.9
1
Reference Voltage (V)
VIN UVLO (V)
3.8
3.7
Rising
Falling
3.6
3.5
3.4
3.3
-50
0.9998
0.9996
0.9994
0.9992
0.999
0.9988
0
50
Temperature (qC)
100
150
0.9986
-50
0
50
Temperature (qC)
D008
Figure 7. VIN UVLO vs Temperature
100
150
D009
Figure 8. Reference Voltage vs Temperature
1.2
HS and LS Current Limit (A)
HS
LS
1.1
1
0.9
0.8
0.7
-50
0
50
Temperature (qC)
100
150
D010
Figure 9. HS and LS Current Limit vs Temperature
8
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8 Detailed Description
8.1 Overview
The TPS560430-Q1 converter is an easy to use synchronous step-down DC-DC converter operating from 4-V to
36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution size. The
family has two versions applicable to various applications, refer to Device Comparison Table for detailed
information.
The TPS560430-Q1 employs fixed-frequency peak-current mode control. The device enters PFM Mode at light
load to achieve high efficiency for PFM version. FPWM version is provided to achieve low output voltage ripple,
tight output voltage regulation, and constant switching frequency at light load. The device is internally
compensated, which reduces design time, and requires few external components.
Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for
a wide range of applications. Protection features include thermal shutdown, VIN under-voltage lockout, cycle-bycycle current limit, and hiccup mode short-circuit protection.
The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.
8.2 Functional Block Diagram
EN
VCC
Enable
LDO
VIN
Precision
Enable
CB
HSI Sense
Internal
SS
EA
REF
FB
±
+
RC
TSD
UVLO
CC
PWM CONTROL LOGIC
PFM
Detector
Ton_min/Toff_min
Detector
SW
Slope
Comp
Freq
Foldback
HICCUP
Detector
Zero
Cross
LSI Sense
Oscillator
FB
GND
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8.3 Feature Description
8.3.1 Fixed Frequency Peak Current Mode Control
The following operation description of TPS560430-Q1 will refer to the Functional Block Diagram and to the
waveforms in Figure 10. TPS560430-Q1 is a step-down synchronous buck converter with integrated high-side
(HS) and low-side (LS) switches (synchronous rectifier). The TPS560430-Q1 supplies a regulated output voltage
by turning on the high-side and low side NMOS switches with controlled duty cycle. During high-side switch ON
time, the SW pin voltage swings up to approximately VIN, and the inductor current iL increases with linear slope
(VIN – VOUT) / L. When the high-side switch is turned off by the control logic, the low-side switch is turned on after
an anti-shoot-through dead time. Inductor current discharges through the low-side switch with a slope of –VOUT /
L. The control parameter of a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side
switch ON time and TSW is the switching period. The converter control loop maintains a constant output voltage
by adjusting the duty cycle D. In an idea Buck converter, where losses are ignored, D is proportional to the
output voltage and inversely proportional to the input voltage: D = VOUT / VIN.
VSW
SW Voltage
VIN
D = tON/ TSW
tOFF
tON
t
0
TSW
iL
Inductor Current
ILPK
IOUT
¨LL
t
0
Figure 10. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The TPS560430-Q1 employs fixed-frequency peak-current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak-current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The converter operates with fixed switching frequency at normal load condition. At light-load
condition, the TPS560430-Q1 operates in PFM mode to maintain high efficiency (PFM version) or in FPWM
mode for low output voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM
version).
10
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Feature Description (continued)
8.3.2 Adjustable Output Voltage
A precision 1.0-V reference voltage (VREF) is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It
is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
bottom-side resistor RFBB for the desired divider current and use Device Support to calculate top-side resistor
RFBT. RFBT in the range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be
used if static loading is desired to reduce VOUT offset in PFM operation. Lower RFBT reduces efficiency at very
light load. Less static current goes through a larger RFBT and might be more desirable when light-load efficiency
is critical. But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible
to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and
temperature variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
Figure 11. Output Voltage Setting
R FBT =
V OUT - V REF
V REF
× R FBB
(1)
8.3.3 Enable
The voltage on the EN pin controls the ON or OFF operation of TPS560430-Q1. A voltage of less than 0.95 V
shuts down the device, while a voltage of more than 1.36 V is required to start the converter. The EN pin is an
input and cannot be left open or floating. The simplest way to enable the operation of the TPS560430-Q1 is to
connect the EN to VIN. This allows self-start-up of the TPS560430-Q1 when VIN is within the operating range.
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 12) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection. Kindly note that, the EN pin voltage should never be higher than VIN + 0.3 V. It is not
recommended to apply EN voltage when VIN is 0 V.
VIN
RENT
EN
RENB
Figure 12. System UVLO by Enable Divider
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Feature Description (continued)
8.3.4 Minimum ON-Time, Minimum OFF-Time and Frequency Foldback
Minimum ON-time(TON_MIN) is the smallest duration of time that the high-side switch can be on. TON_MIN is
typically 60 ns in the TPS560430-Q1. Minimum OFF-time( TOFF_MIN) is the smallest duration that the high-side
switch can be off. TOFF_MIN is typically 100 ns. In CCM operation, TON_MIN and TOFF_MIN limit the voltage
conversion range without switching frequency foldback.
The minimum duty cycle without frequency foldback allowed is
DMIN = TON_MIN X fSW
(2)
The maximum duty cycle without frequency foldback allowed is
DMAX = 1 - TOFF_MIN X fSW
(3)
Given a required output voltage, the maximum VIN without frequency foldback can be found by
V IN_MAX =
V OUT
f SW × T ON_MIN
(4)
The minimum VIN without frequency foldback can be calculated by
VIN_MIN =
V OUT
1- f SW × T OFF_MIN
(5)
In the TPS560430-Q1, a frequency foldback scheme is employed once the TON_MIN or TOFF_MIN is triggered,
which may extend the maximum duty cycle or lower the minimum duty cycle.
The on-time decreases while VIN voltage increases. Once the on-time decreases to TON_MIN, the switching
frequency starts to decrease while VIN continues to go up, which lowers the duty cycle further to keep VOUT in
regulation according to Equation 2.
The frequency foldback scheme also works once larger duty cycle is needed under low VIN condition. The
frequency decreases once the device hits its TOFF_MIN, which extends the maximum duty cycle according to
Equation 3. In such condition, the frequency can be as low as about 133 kHz minimum. Wide range of frequency
foldback allows the TPS560430-Q1 output voltage stay in regulation with a much lower supply voltage VIN, which
leads to a lower effective drop-out.
With frequency foldback, VIN_MAX is raised, and VIN_MIN is lowered by decreased fSW.
2.2
2.2
2
1.8
1.6
Frequency(MHz)
Frequency(MHz)
1.9
1.6
1.2
1
0.8
0.6
1.3
0.4
IOUT=0mA
IOUT=300mA
IOUT=600mA
1
16
IOUT=100mA
IOUT=300mA
IOUT=600mA
0.2
0
21
VOUT = 3.3 V
26
VIN(V)
31
36
5
5.25
D001
fSW = 2.1 MHz
VOUT = 5 V
Figure 13. Frequency Foldback at TON_MIN
12
1.4
5.5
5.75
6
VIN(V)
6.25
6.5
6.75
7
SLUS
fSW = 2.1 MHz
Figure 14. Frequency Foldback at TOFF_MIN
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Feature Description (continued)
8.3.5 Bootstrap Voltage
The TPS560430-Q1 provides an integrated bootstrap voltage converter. A small capacitor between the CB and
SW pins provides the gate drive voltage for the high-side MOSFET. The bootstrap capacitor is refreshed when
the high-side MOSFET is off and the low-side switch conducts. The recommended value of the bootstrap
capacitor is 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or
higher is recommended for stable performance over temperature and voltage.
8.3.6 Over Current and Short Circuit Protection
The TPS560430-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak
and valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating.
High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The
high-side switch current is sensed when the high-side is turned on after a set blanking time. The high-side switch
current is compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle.
Please refer to Functional Block Diagram for more details. The peak current of high-side switch is limited by a
clamped maximum peak current threshold Ihigh side_LIMIT which is constant.
The current going through low-side MOSFET is also sensed and monitored. When the low-side switch turns on,
the inductor current begins to ramp down. The low-side switch will not be turned OFF at the end of a switching
cycle if its current is above the low-side current limit ILS_LIMIT. The low-side switch is kept ON so that inductor
current keeps ramping down, until the inductor current ramps below the ILS_LIMIT. Then the low-side switch will be
turned OFF and the high-side switch will be turned on after a dead time. This is somewhat different to the more
typical peak current limit, and results in Equation 6 for the maximum load current.
I OUT_MAX = I LS +
VIN - V OUT
2 × f SW × L
×
V OUT
V IN
(6)
If the feedback voltage is lower than 40% of the VREF, the current of the low-side switch triggers ILS_LIMIT for 256
consecutive cycles, hiccup current protection mode is activated. In hiccup mode, the converter shuts down and
keeps off for a period of hiccup, THICCUP (135 ms typical), before the TPS560430-Q1 tries to start again. If overcurrent or short-circuit fault condition still exist, hiccup repeats until the fault condition is removed. Hiccup mode
reduces power dissipation under severe over-current conditions, prevents over-heating and potential damage to
the device.
For FPWM version, the inductor current is allowed to go negative. When this current exceed the low-side
negative current limit ILS_NEG, the low-side switch is turned off and high-side switch is turned on immediately. This
is used to protect the low-side switch from excessive negative current.
8.3.7 Soft Start
The integrated soft-start circuit prevents input inrush current impacting the TPS560430-Q1 and the input power
supply. Soft-start is achieved by slowly ramping up the target regulation voltage when the device is first enabled
or powered up. The typical soft-start time is 1.8 ms.
The TPS560430-Q1 also employs over-current protection blanking time TOCP_BLK (33 ms typical) at the beginning
of power-up. Without this feature, in applications with a large amount of output capacitors and high VOUT, the
inrush current is large enough to trigger the current-limit protection, which may make the device entering into
hiccup mode. The device tries to restart after the hiccup period, then hit current-limit and enter into hiccup mode
again, so VOUT cannot ramp up to the setting voltage ever. By introducing OCP blanking feature, the hiccup
protection function is disabled during TOCP_BLK, and TPS560430-Q1 charges the VOUT with its maximum limited
current, which maximizes the output current capacity during this period. Kindly note that, the peak current limit
(IHS_LIMIT) and valley current limit (ILS_LIMIT) protection function are still available during TOCP_BLK, so there is no
concern of inductor current running away.
8.3.8 Thermal Shutdown
The TPS560430-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C. Both high-side and low-side FETs stop switching in thermal shutdown. Once the die temperature
falls below 158°C, the device reinitiates the power up sequence controlled by the internal soft-start circuitry.
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8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS560430-Q1. When VEN is below 0.95 V, the
device is in shutdown mode. The TPS560430-Q1 also employs VIN under voltage lock out protection (UVLO). If
VIN voltage is below its UVLO threshold 3.25 V, the converter is turned off.
8.4.2 Active Mode
The TPS560430-Q1 is in Active Mode when both VEN and VIN are above their respective operating threshold.
The simplest way to enable the TPS560430-Q1 is to connect the EN pin to VIN pin. This allows self-startup when
the input voltage is in the operating range: 4.0 V to 36 V. Please refer to Enable section for details on setting
these operating levels.
In Active Mode, depending on the load current, the TPS560430-Q1 will be in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple (for both PFM and FPWM versions).
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation (only for PFM version).
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM version).
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM version).
8.4.3 CCM Mode
Continuous Conduction Mode (CCM) operation is employed in the TPS560430-Q1 when the load current is
higher than half of the peak-to-peak inductor current. In CCM operation, the frequency of operation is fixed,
output voltage ripple is at a minimum in this mode and the maximum output current of 600 mA can be supplied
by the TPS560430-Q1.
8.4.4 Light-Load Operation (PFM Version)
For PFM version, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
TPS560430-Q1 operates in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode
(DEM). In DCM operation, the low-side switch is turned off when the inductor current drops to ILS_ZC (20 mA
typical) to improve efficiency. Both switching losses and conduction losses are reduced in DCM, compared to
forced PWM operation at light load.
At even lighter current load, Pulse Frequency Modulation (PFM) mode is activated to maintain high efficiency
operation. When either the minimum high-side switch ON time tON_MIN or the minimum peak inductor current
IPEAK_MIN (150mA typical) is reached, the switching frequency decreases to maintain regulation. In PFM mode,
switching frequency is decreased by the control loop to maintain output voltage regulation when load current
reduces. Switching loss is further reduced in PFM operation due to less frequent switching actions.
8.4.5 Light-Load Operation (FPWM Version)
For FPWM version, TPS560430-Q1 is locked in PWM mode at full load range. This operation is maintained, even
in no-load condition, by allowing the inductor current to reverse its normal direction. This mode trades off reduced
light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS560430-Q1 is a step down DC-to-DC converter. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 600 mA. The following design procedure can be used to
select components for the TPS560430-Q1. Alternately, the WEBENCH® software may be used to generate
complete designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and
accesses comprehensive databases of components. Please go to ti.com for more details.
9.2 Typical Application
The TPS560430-Q1 only requires a few external components to convert from a wide voltage range supply to a
fixed output voltage. Figure 15 shows a basic schematic.
VIN 12 V
VIN
CB
EN
SW
CBOOT
0.1 µF L
10 µH
CIN
2.2 µF
VOUT 5 V
RFBT
88.7 NŸ
GND
COUT
22 µF
FB
RFBB
22.1 NŸ
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Figure 15. Application Circuit
The external components have to fulfill the needs of the application and the stability criteria of the device's
control loop. Table 1 can be used to simplify the output filter component selection.
Table 1. L and COUT Typical Values
fSW (MHz)
2.1
VOUT (V)
L (µH)
COUT (µF)
RFBT (kΩ)
RFBB (kΩ)
3.3
6.8
5
10
10 µF / 10 V
51
22.1
10 µF / 10 V
88.7
12
18
22.1
10 µF / 25 V
243
22.1
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9.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 2 as the input parameters.
Table 2. Design Example Parameters
PARAMETER
Input voltage, VIN
VALUE
12 V typical, range from 6 V to 36 V
Output voltage, VOUT
5 V ±3%
Maximum output current, IOUT_MAX
600 mA
Minimum output current, IOUT_MIN
30 mA
Output overshoot/ undershoot (0mA to 600mA )
5%
Output voltage ripple
0.5%
Operating frequency
2.1 MHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS560430-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.2.2 Output Voltage Set-Point
The output voltage of the TPS560430-Q1 device is externally adjustable using a resistor divider network. The
divider network is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 7 is used
to determine the output voltage of the converter:
R FBT =
V OUT - V REF
V REF
× R FBB
(7)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1.0 V, the
RFBT value can then be calculated using Equation 7. The formula yields to a value 88.4 kΩ, a standard value of
88.7 kΩ is selected.
9.2.2.3 Switching Frequency
The higher switching frequency allows for lower value inductors and smaller output capacitors, which results in
smaller solution size and lower component cost. However higher switching frequency brings more switching loss,
which makes the solution less efficient and produce more heat. The switching frequency is also limited by the
minimum on-time of the integrated power switch, the input voltage, the output voltage and the frequency shift
limitation as mentioned in Minimum ON-Time, Minimum OFF-Time and Frequency Foldback section. For this
example, a switching frequency of 2.1 MHz is selected.
9.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the RMS current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 9 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the amount
of inductor ripple current relative to the maximum output current of the device. A reasonable value of KIND should
be 20% to 60%. During an instantaneous over current operation event, the RMS and peak inductor current can
be high. The inductor current rating should be a bit higher than current limit.
ûL L
L MIN =
V OUT × V IN_MAX - V OUT
V IN_MAX × L × f SW
VIN_MAX - V OUT
I OUT × K IND
×
(8)
V OUT
VIN_MAX × f SW
(9)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more inductor core loss since the current ripple is larger. Larger
inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak current
mode control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple
improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 8.6µH. Choose the
nearest standard 8.2-µH ferrite inductor with a capability of 1-A RMS current and 1.5-A saturation current.
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9.2.2.5 Output Capacitor Selection
The device is designed to be used with a wide variety of LC filters. It is generally desired to use as little output
capacitance as possible to keep cost and size down. The output capacitor (s), COUT, should be chosen with care
since it directly affects the steady state output voltage ripple, loop stability, output voltage overshoot and
undershoot during load current transient. The output voltage ripple is essentially composed of two parts. One is
caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output
capacitors:
û9 OUT_ESR
ûL L × ESR = K IND × I OUT × ESR
(10)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
û9 OUT_C
ûL L
. IND × I OUT
8 × f SW × C OUT
8 × f SW × C OUT
(11)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of the two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a large load step happens, output
capacitors provide the required charge before the inductor current can slew up to the appropriate level. The
converter’s control loop usually needs 8 or more clock cycles to regulate the inductor current equal to the new
load level. The output capacitance must be large enough to supply the current difference for 8 clock cycles to
maintain the output voltage within the specified range. Equation 12 shows the minimum output capacitance
needed for specified VOUT overshoot and undershoot.
C OUT >
8 × I OH - I OL
1
×
2 f SW × û9 OUT_SHOOT
(12)
where
• KIND = Ripple ratio of the inductor current (ΔiL / IOUT)
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VOUT_SHOOT = Target output voltage overshoot or undershoot
For this design example, the target output ripple is 30 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 30 mV, and
chose KIND = 0.4. Equation 10 yields ESR no larger than 125 mΩ and Equation 11 yields COUT no smaller than
0.91 µF. For the target overshoot and undershoot limitation of this design, ΔVOUT_SHOOT = 5% × VOUT = 250 mV.
The COUT can be calculated to be no smaller than 4.3 µF by Equation 12. In summary, the most stringent criteria
for the output capacitor is 4.3 µF. Consider of derating, one 10-µF, 10-V, X7R ceramic capacitor with 10-mΩ
ESR is used.
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9.2.2.6 Input Capacitor Selection
The TPS560430-Q1 device requires high frequency input decoupling capacitor(s). The typical recommended
value for the high frequency decoupling capacitor is 2.2 µF or higher. A high-quality ceramic type X5R or X7R
with sufficiency voltage rating is recommended. The voltage rating must be greater than the maximum input
voltage. To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage
is recommended. For this design, one 2.2-µF, X7R dielectric capacitor rated for 50 V is used for the input
decoupling capacitor. The equivalent series resistance (ESR) is approximately 10 mΩ, and the current rating is 1
A. Include a capacitor with a value of 0.1 µF for high-frequency filtering and place it as close as possible to the
device pins.
9.2.2.7 Bootstrap Capacitor
Every TPS560430-Q1 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitor is
0.1 µF and rated at 16 V or higher. The bootstrap capacitor is located between the SW pin and the CB pin. The
bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature
stability.
9.2.2.8 Under Voltage Lockout Set-Point
The system under voltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO
level.
VIN_RISING = V ENH ×
R ENT + R ENB
R ENB
(13)
The EN rising threshold (VENH) for TPS560430-Q1 is set to be 1.23 V (typical). Choose the value of RENB to be
200 kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT
can be calculated using Equation 14:
§ V IN_RISING
·
R ENT = ¨
- 1 ¸ × R ENB
¨ V ENH
¸
©
¹
(14)
The above equation yields a value of 775.6 kΩ, a standard value of 768 kΩ is selected. The resulting falling
UVLO threshold, equals 5.3 V, can be calculated by Equation 15, where EN hysteresis voltage, VEN_HYS, is 0.13
V (typical).
VIN_FALLING = V ENH - V EN_HYS ×
R ENT + R ENB
R ENB
(15)
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW = 2.1 MHz, L = 8.2 µH, COUT = 10 µF,
TA = 25 °C
VSW[5V/div]
VSW[5V/div]
VOUT(AC)[10mV/div]
iL[200mA/div]
iL[200mA/div]
VOUT(AC)[10mV/div]
Time[1us/div]
Time[1us/div]
IOUT = 0 mA
FPWM Version
IOUT = 600 mA
Figure 16. Ripple at No Load
FPWM Version
Figure 17. Ripple at Full Load
VIN[10V/div]
EN[2V/div]
VOUT[2V/div]
VOUT[2V/div]
iL[500mA/div]
iL[500mA/div]
Time[100ms/div]
Time[1ms/div]
IOUT = 600 mA
FPWM Version
IOUT = 600 mA
Figure 18. Start Up by VIN
FPWM Version
Figure 19. Start-Up by EN
IOUT[200mA/div]
VOUT[2V/div]
VOUT(AC)[200mV/div]
iL[500mA/div]
Time[200µs/div]
IOUT = 0 to 600
mA, 100 mA / µs
FPWM Version
Time[100ms/div]
IOUT = 0 mA to
short
Figure 20. Load Transient
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FPWM Version
Figure 21. Short Protection
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Unless otherwise specified the following conditions apply: VIN = 12 V, VOUT = 5 V, fSW = 2.1 MHz, L = 8.2 µH, COUT = 10 µF,
TA = 25 °C
VOUT[2V/div]
iL[500mA/div]
Time[100ms/div]
IOUT = short to 0 mA
FPWM Version
Figure 22. Short Recovery
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10 Power Supply Recommendations
The TPS560430-Q1 is designed to operate from an input voltage supply range between 4.0 V and 36 V. This
input supply should be well regulated and able to withstand maximum input current and maintain a stable
voltage. The resistance of the input supply rail should be low enough that an input current transient does not
cause a high enough drop at the TPS560430-Q1 supply voltage that can cause a false UVLO fault triggering and
system reset. If the input supply is located more than a few inches from the TPS560430-Q1 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not
critical, but a 10-µF or 22-µF electrolytic capacitor is a typical choice.
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and GND pins. Grounding for
both the input and output capacitors should consist of localized top side planes that connect to the GND pin.
2. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to
the FB pin. If VOUT accuracy at the load is important, make sure VOUT sense is made at the load. Route VOUT
sense path away from noisy nodes and preferably through a layer on the other side of a shielded layer.
3. Use ground plane in one of the middle layers as noise shielding and heat dissipation path if possible.
4. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
5. Provide adequate device heat-sinking. GND, VIN and SW pins provide the main heat dissipation path, make
the GND, VIN and SW plane area as large as possible. Use an array of heat-sinking vias to connect the top
side ground plane to the ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these
thermal vias can also be connected to inner layer heat-spreading ground planes. Ensure enough copper area
is used for heat-sinking to keep the junction temperature below 125 °C.
11.1.1 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
ceramic bypass capacitor(s) as close as possible to the VIN and GND pins is the key to EMI reduction.
The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current
conduction path to minimize parasitic resistance. The output capacitors should be placed close to the VOUT end
of the inductor and closely grounded to GND pin.
11.1.2 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider close
to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider closer to the FB pin reduces the trace
length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace from
VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
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11.2 Layout Example
VOUT
Output Bypass
Capacitor
Output
Inductor
BOOT
Capacitor
GND
CB
SW
GND
VIN
FB
EN
VIN
Input Bypass
Capacitor
Output Voltage
Set Resistor
GND
VIA (Connect to GND Plane)
Figure 23. Layout
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23
TPS560430-Q1
SLUSDF5A – JANUARY 2019 – REVISED AUGUST 2019
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS560430-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• AN-1149 Layout Guidelines for Switching Power Supplies
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS560430-Q1
TPS560430-Q1
www.ti.com
SLUSDF5A – JANUARY 2019 – REVISED AUGUST 2019
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: TPS560430-Q1
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS560430YFQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1RTF
TPS560430YQDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1RSF
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
