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TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
采用 SOT563 封装的 TPS562231 4.5V 至 17V 输入、2A 同步降压转换器
1 特性
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3 说明
TPS562231 是一款采用 SOT563 封装的简单易用型
2A 同步降压转换器。
2A 转换器集成了 95mΩ 和 55mΩ FET
D-CAP3™模式控制，用于快速瞬态响应
输入电压范围：4.5V 至 17V
输出电压范围：0.6V 至 7V
脉冲跳跃模式
850kHz 开关频率
小于 2µA（典型值）的低关断电流
2% 反馈电压精度 (25ºC)
从预偏置输出电压中启动
逐周期过流限制
断续模式过流保护
非锁存 UVP 和 TSD 保护
6 引脚 SOT563 封装
精密使能端
与 TPS563231 引脚对引脚兼容
该器件经过优化，最大限度地减少了运行所需的外部组
件并可实现低待机电流。
这些开关模式电源 (SMPS) 器件采用 D-CAP3 模式控
制，该模式控制可提供快速瞬态响应，并同时支持诸如
高分子聚合物等低等效串联电阻 (ESR) 输出电容以及
超低 ESR 陶瓷电容器（无需外部补偿组件）。
在轻载运行期间，TPS562231 在脉冲跳跃模式 (PSM)
下运行，从而保持高效率。TPS562231 采用 6 引脚
1.6mm × 1.6mm SOT563 (DRL) 封装，额定结温范围
为 –40°C 至 125°C。
器件信息(1)
器件型号
2 应用
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TPS562231
封装
封装尺寸（标称值）
DRL (6)
1.60mm x 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
标准 12V 电源轨
数字电视电源
嵌入式系统
网络家庭终端设备
数字机顶盒 (STB)
监控
电表
空白
SPACER
简化电路原理图
TPS562231 效率
VIN
VIN
100
BST
CBST
CIN
L
VOUT
RFBT
GND
80
SW
FB
COUT
RFBB
Efficiency(%)
EN
60
40
20
0.001
Vo=1.05V
Vo=1.8V
Vo=3.3V
Vo=5V
0.01
0.1
Iout(A)
1
2
TPS5
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDA4
TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性 ..........................................................................
应用 ..........................................................................
说明 ..........................................................................
修订历史记录 ...........................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 器件和文档支持 ..................................................... 18
11.1
11.2
11.3
11.4
11.5
11.6
器件支持 ...............................................................
接收文档更新通知 .................................................
社区资源................................................................
商标 .......................................................................
静电放电警告.........................................................
Glossary ................................................................
18
18
18
18
18
18
12 机械、封装和可订购信息 ....................................... 19
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (March 2019) to Revision B
•
Page
Changed FB I/O Type from 'O' to 'I'........................................................................................................................................ 4
Changes from Original (February 2019) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“初始发行版”。........................................................................................................... 1
2
Copyright © 2019, Texas Instruments Incorporated
TPS562231
www.ti.com.cn
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
5 Pin Configuration and Functions
DRL Package
6-Pin SOT563
Top View
VIN
1
6
FB
SW
2
5
EN
GND
3
4
BST
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BST
4
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
BST and SW pins.
EN
5
I
Enable input control. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust
the input undervoltage lockout with EN resistor divider.
FB
6
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
GND
3
—
Power ground terminals, connected to the source of low-side FET internally. Connect to
system ground, ground side of CIN and COUT. Path to CIN must as short as possible.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
1
I
Input voltage supply pin. The drain terminal of high-side power NFET.
Copyright © 2019, Texas Instruments Incorporated
3
TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
VIN
–0.3
19
V
BST
–0.3
24.5
V
BST (10 ns transient)
–0.3
26.5
V
BST to SW
–0.3
5.5
V
FB
–0.3
5.5
V
EN
-0.3
VIN + 0.3
SW
–2
19
V
SW (10 ns transient)
–3.5
21
V
Operating junction
temperature
TJ
–40
150
°C
Storage temperature
Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
Operating junction
temperature
4
MIN
MAX
VIN
4.5
17
BST
–0.1
22
BST to SW
–0.1
5
EN
–0.1
VIN
FB
–0.1
4.5
SW
–1.8
17
TJ
–40
125
UNIT
V
V
°C
Copyright © 2019, Texas Instruments Incorporated
TPS562231
www.ti.com.cn
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
6.4 Thermal Information
TPS562231
THERMAL METRIC (1)
DRL
UNIT
6 PINS
θJA
Junction-to-ambient thermal resistance
135.8
°C/W
θJC(top)
Junction-to-case (top) thermal resistance
45.5
°C/W
θJB
Junction-to-board thermal resistance
23.8
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
24.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2019, Texas Instruments Incorporated
5
TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
220
300
µA
2
12
µA
4.0
4.3
POWER SUPPLY (VIN PIN)
IVIN
Operating – non-switching
supply current
VEN = 5 V, VFB = 0.7 V
IVINSDN
Shutdown supply current
VEN = 0 V
VIN_UVLO
Undervoltage lockout
thresholds
Rising threshold
Falling threshold
3.3
Hysteresis
3.6
V
0.4
ENABLE (EN PIN)
VENH
EN high-level input voltage
VENL
EN low-level input voltage
REN
EN pin resistance to GND
1.1
1.24
1.42
1
1.13
1.3
VEN = 12 V
1000
V
V
kΩ
VOLTAGE REFERENCE (FB PIN)
VIN = 4.5 V to 17 V, TJ = 25 °C
588
600
612
mV
VREF
Reference voltage
IFB
VFB input current
VFB = 0.6 V
RDSON_H
High-side switch resistance
TJ = 25°C, VBST – VSW = 5.5 V
95
mΩ
RDSON_L
Low-side switch resistance
TJ = 25°C
55
mΩ
VIN = 4.5 V to 17 V, TJ = –40°C to 125°C
600
0
mV
±100
nA
MOSFET
CURRENT LIMIT
IOC_LS
Low side FET source current
limit
IZC
Zero cross current detection
2.3
TPS562231
2.8
0
3.3
A
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
Hysteresis
160
25
°C
ON-TIME TIMER CONTROL
tON(MIN)
tOFF(MIN)
Minimum on time (1)
80
ns
VFB = 0.5 V
250
ns
Soft-start time
Internal soft-start time
1.5
ms
Switching frequency
VIN = 12 V, VOUT = 3.3 V, CCM mode
850
kHz
65
%
Minimum off time
(1)
SOFT START
Tss
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP falling threshold
THICCUP_WAIT
UVP propagation delay
0.6
ms
THICCUP_RE
Hiccup time before restart
24
ms
(1)
6
Hiccup detect
Not production tested.
版权 © 2019, Texas Instruments Incorporated
TPS562231
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ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
230
610
608
Reference Voltage VREF (V)
Quiescent Current IQ (µA)
225
220
215
210
205
606
604
602
600
598
596
594
200
-50
-25
0
25
50
75
Temperature (°C)
100
125
592
-40
150
-20
0
20
Iq-S
图 1. IQ vs Junction Temperature
40
60
80
Temperature(qC)
100
120
140
Refe
图 2. VREF Voltage vs Junction Temperature
4.3
1.3
EN Threshold VEN (V)
VIN UVLO Threshold (V)
4.2
4.1
4
Rising
Falling
3.9
3.8
1.25
1.2
Rising
Falling
1.15
3.7
3.6
-50
-25
0
25
50
75
Temperature (°C)
100
125
1.1
-50
150
0
25
50
75
Temperature (°C)
100
125
150
en-S
图 4. EN Pin UVLO vs Junction Temperature
140
3
120
HS and LS FET RDSON
LS Fet Valley Current Limit Isc_cl(A)
图 3. VIN UVLO vs Junction Temperature
3.04
2.96
2.92
HS
LS
100
80
60
2.88
2.84
-50
-25
vin-
-25
0
25
50
75
Temperature(qC)
100
125
150
图 5. Current Limit vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
Vall
40
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
rdso
图 6. RDS-ON vs Junction Temperature
7
TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
Typical Characteristics (接
接下页)
VIN = 12 V (unless otherwise noted)
100
100
80
Efficiency(%)
Efficiency(%)
80
60
40
40
Vin=5V
Vin=9V
Vin=12V
Vin=17V
20
0
0.001
0.01
0.1
1
Vin=5V
Vin=9V
Vin=12V
Vin=17V
20
0.001
2
Iout(A)
60
0.01
0.1
1
2
Iout(A)
TPS5
图 7. TPS562231 VOUT = 1.05 V Efficiency
TPS5
图 8. TPS562231 VOUT = 1.8 V Efficiency
100
100
90
Efficiency(%)
Efficiency(%)
80
60
40
Vin=5V
Vin=9V
Vin=12V
Vin=17V
20
0.001
0.01
0.1
1
70
60
40
0.001
0.1
1
2
Iout(A)
TPS5
图 10. TPS562231 VOUT = 5 V Efficiency
3.339
3.36
3.336
3.35
3.333
3.34
3.33
3.33
3.327
3.32
Vout(V)
VOUT(V)
0.01
TPS5
图 9. TPS562231 VOUT = 3.3 V Efficiency
3.324
3.321
3.318
3.31
3.3
3.29
3.315
3.28
3.312
Vin=9V
Vin=12V
Vin=17V
3.309
3.27
0
0.2
0.4
Io=0A
Io=1A
Io=2A
3.26
3.306
0.6
0.8
1
1.2
Iout(A)
1.4
1.6
1.8
图 11. TPS562231 VOUT = 3.3V Load Regulation
8
7.5V
9V
12V
17V
50
2
Iout(A)
80
2
TPS5
3.25
4
6
8
10
12
14
16
Vin(V)
18
TPS5
图 12. TPS562231 VOUT = 3.3 V Line Regulation
版权 © 2019, Texas Instruments Incorporated
TPS562231
www.ti.com.cn
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
7 Detailed Description
7.1 Overview
The TPS562231 is a 2-A synchronous step-down converter. The proprietary D-CAP3 mode control supports low
ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without complex
external compensation circuits. The fast transient response of D-CAP3 mode control can reduce the output
capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 5
1 VIN
VUVP
+
UVP
Hiccup
Control Logic
VREG5
Regulator
UVLO
FB 6
Voltage
Reference
+
+
+
4 BST
PWM
SS
Soft Start
HS
+
Internal Ramp
2 SW
One-Shot
XCON
VREG5
Ripple Injection
TSD
OCL
threshold
LS
OCL
+
3 GND
+
ZC
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS562231 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP3 mode control. The D-CAP3 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal onshot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VOUT, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The on-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference
voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP3 mode control.
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Feature Description (接
接下页)
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS562231 has an internal 1.5-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage from 0 V to 0.6 V linearly.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.3 Over Current and Short Circuit Protection
The TPS562231 is protected from over-current conditions by cycle-by-cycle current limit on the valley of the
inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.
The current going through low-side (LS) MOSFET is sensed and monitored. When the LS MOSFET turns on, the
inductor current begins to ramp down. The LS MOSFET will not be turned OFF if its current is above the LS
current limit ILS_LIMIT even the feedback voltage, VFB, drops below the reference voltage VREF. The LS MOSFET is
kept ON so that inductor current keeps ramping down, until the inductor current ramps below the LS current limit
ILS_LIMIT. Then the LS MOSFET is turned OFF and the HS switch is turned on after a dead time.
As the inductor current is limited by ILS_LIMT, the output voltage tends to drop as the inductor current may be
smaller than the load current. Hiccup current protection mode is activated once the VFB drops below the UVP
threshold after a delay time (600 µs typically). In hiccup mode, the regulator is shut down and kept off for 24 ms
typically before the TPS562231 try to start again. If over-current or short-circuit fault condition still exist, hiccup
will repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current
conditions, prevents over-heating and potential damage to the device.
7.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 160°C),
the device is shut off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPS562231. When VEN is below its threshold (1.13 V
typically), the device is in shutdown mode. The switching regulator is turned off and the quiescent current drops
to 2.0 µA typically. The TPS562231 also employ VIN under voltage lock out protection. If VIN voltage is below its
UVLO threshold (3.6 V typically), the regulator is turned off.
7.4.2 Continuous Conduction Mode (CCM)
Continuous Conduction Mode (CCM) operation is employed when the load current is higher than half of the
peak-to-peak inductor current. In CCM operation, the frequency of operation is pseud fixed, output voltage ripple
will be at a minimum in this mode and the maximum output current of 2 A can be supplied.
10
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TPS562231
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ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
Device Functional Modes (接
接下页)
7.4.3 Pulse Skip Mode (PSM, TPS562231)
The TPS562231 is designed with Advanced Eco-mode™ to maintain high light load efficiency. As the output
current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point
that its rippled valley touches zero level, which is the boundary between continuous conduction mode (CCM) and
discontinuous conduction mode (DCM). The low-side MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases the converter runs into discontinuous conduction mode. The ontime is kept almost the same as it was in the continuous conduction mode so that it takes longer time to
discharge the output capacitor with smaller load current to the level of the reference voltage. This makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high. The transition
point to the light load operation current IOUT_LL can be calculated in 公式 1.
(V
VOUT ) u VOUT
1
u IN
IOUT _ LL
2 u L u fSW
VIN
(1)
As the load current continues to decrease, the switching frequency also decreases. The on-time starts to
decrease once the switching frequency is lower than 250 kHz. The on-time can be about 22% reduced at most
for extremely light load condition. This function is employed to achieve smaller ripple at extremely light load
condition.
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ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The devices are typical step-down DC-DC converters. It typically uses to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 2 A. The following design procedure can be used to select
component values for the TPS562231. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
The TPS562231 only require a few external components to convert from a higher variable voltage supply to a
fixed output voltage. 图 13 shows a basic schematic of 3.3-V output application. This section provides the design
procedure.
VIN 12 V
BST
VIN
CIN
10 µF
CBOOT
0.1 µF
VOUT
3.3 V
L 3.3 µH
SW
EN
RFBT
45.3 NŸ
COUT
47 µF
FB
GND
RFBB
10 NŸ
图 13. TPS562231 3.3V/2-A Reference Design
8.2.1 Design Requirements
表 1 shows the design parameters for this application.
表 1. Design Parameters
PARAMETER
Input voltage range
Output voltage
Transient response, 2-A load step
EXAMPLE VALUE
4.5 to 17 V
3.3 V
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
2A
Operating frequency
850 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. 1% tolerance or better divider
resistors is recommended. Start by using 公式 2 to calculate VOUT.
12
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TPS562231
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ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the FB input current will be more noticeable.
§
RFBT ·
VOUT
0.6 u ¨ 1
¸
RFBB ¹
©
(2)
Choose the value of RFBB to be 10 kΩ. With the desired output voltage set to 3.3 V and the VREF = 0.6 V, the
RFBT value can then be calculated using 公式 2. The formula yields to a value 45.3 kΩ of RFBT.
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
2S L u COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP3 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of 公式 3 is located below the high
frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate
phase margin for a stable circuit. To meet this requirement use the values recommended in 表 2.
表 2. Recommended Component Values
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
C8 + C9 (µF)
1
6.65
10.0
1
1.2
4.7
20 to 68
1.05
7.5
10.0
1
1.2
4.7
20 to 68
1.2
10
10.0
1.2
1.5
4.7
20 to 68
1.5
15
10.0
1.5
1.5
4.7
20 to 68
1.8
20
10.0
1.5
2.2
4.7
20 to 68
2.5
31.6
10.0
2.2
2.2
4.7
20 to 68
3.3
45.3
10.0
2.2
3.3
4.7
20 to 68
5
73.2
10.0
3.3
4.7
4.7
20 to 68
6.5
97.6
10.0
3.3
4.7
4.7
20 to 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using 公式 4, 公式 5, and
公式 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or
heating current rating must be greater than the calculated RMS current.
VIN _ MAX VOUT
VOUT
IL _ PP
u
VIN _ MAX
L u fSW
(4)
IL _ PK
IL _ RMS
IOUT
2
IOUT
IL _ PP
2
(5)
1 2
IL _ PP
12
(6)
For this design example, the calculated peak current is 2.43 A and the calculated RMS current is 2.01A. The
inductor used is a WE 74437349033 with a peak current rating of 13.5 A and an RMS current rating of 5 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS562231 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use 公式 7 to
determine the required RMS current rating for the output capacitor.
IC _ RMS
VOUT u VIN _ MAX
VOUT
12 u VIN _ MAX u L u fSW
版权 © 2019, Texas Instruments Incorporated
(7)
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For this design two Murata GRM21BR61A226ME44L 22-µF/10-V output capacitors are used in parallel. The
typical ESR is 3mΩ each. The calculated RMS current is 0.39 A and each output capacitor is rated for 5 A.
8.2.2.3 Input Capacitor Selection
The TPS562231 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10-µF for the decoupling capacitor. An additional 0.1-µF
capacitor from VIN pin to GND pin is also recommended to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage, 25 V or higher voltage rating is
recommended.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BST to SW pin for proper operation. 10 V or higher
voltage rating is recommended.
14
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TPS562231
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ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
8.2.3 Application Curves
VSW [5V/div]
VSW [5V/div]
VOUT [5mV/div ]
VOUT [10mV/div ]
IL [1A/div]
IL [1A/div]
Time [1 s/div]
Time [2 s/div]
图 14. CCM Mode
图 15. DCM Mode
VSW [5V/div]
VIN [5V/div]
VOUT [10mV/div ]
VOUT [1V/div ]
IL [1A/div]
IL [2A/div]
Time [1ms/div]
Time [2ms/div]
图 17. Start-up by VIN
图 16. PSM Mode
VOUT [100mV/div ]
VEN [2V/div]
VOUT [1V/div ]
Iout [1A/div]
IL [2A/div]
IO
Time [400 s/div]
Time [1ms/div]
图 18. Start-up by EN
版权 © 2019, Texas Instruments Incorporated
图 19. Load Transient
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TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
VOUT [1V/div ]
VOUT [1V/div ]
IL [2A/div]
IL [2A/div]
Time [20ms/div]
Time [20ms/div]
图 20. Short Protection
图 21. Short Recovery
9 Power Supply Recommendations
TPS562231 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 70%. Using that criteria, the minimum recommended input voltage is VO / 0.7.
16
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TPS562231
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
VIN
GND
CIN
SW
RFBB
VIN
FB
SW
EN
GND
BST
RFBT
EN
Control
CBST
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
图 22. TPS562231 Layout
版权 © 2019, Texas Instruments Incorporated
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TPS562231
ZHCSJF5B – FEBRUARY 2019 – REVISED OCTOBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 商标
D-CAP3, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
18
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TPS562231
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS562231DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2231
TPS562231DRLT
ACTIVE
SOT-5X3
DRL
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
2231
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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