TPS563207S
SLUSED9 – TPS563207S
OCTOBER 2020
SLUSED9 – OCTOBER 2020
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TPS563207S 4.3-V to 17-V Input, 3-A FCCM Mode
Synchronous Buck Converter in SOT563
1 Features
3 Description
•
The TPS563207S is a simple, easy-to-use, 3-A
synchronous buck converter in a SOT563 package.
•
•
•
•
•
•
•
•
•
•
•
•
3-A converter with integrated 95-mΩ and 57-mΩ
FETs
D-CAP2™ mode control with fast transient
response
Input voltage range: 4.3 V to 17 V
Output voltage range: 0.806 V to 7 V
Continuous current mode (FCCM mode)
Typical 580-kHz switching frequency
Low shutdown current of less than 3 µA
1.5% feedback voltage accuracy (25°C)
Provide pre-bias function
Cycle-by-cycle overcurrent limit
Hiccup-mode overcurrent protection
Non-latch UVP and TSD protections
Fixed soft start: 1.2 ms
2 Applications
•
•
•
•
•
Digital set-top box (STB)
SMPS power supply for TV
Smart speaker
Wired networking
Surveillance
The device is optimized to operate with minimum
external components.
This switch mode power supply (SMPS) device
employs D-CAP2™ mode control, providing a fast
transient response and supporting both low-equivalent
series resistance (ESR) output capacitors such as
specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
The TPS563207S operates in FCCM mode, which
maintains small ripple even at light loads. The
TPS563207S is available in a 6-pin 1.6-mm × 1.6-mm
SOT563 (DRL) package, and specified from a –40°C
to 125°C junction temperature.
Device Information
PART NUMBER
PACKAGE
TPS563207S
(1)
(1)
SOT563
BODY SIZE (NOM)
1.60 mm × 1.60 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
Simplified Schematic
Vout = 1.05 V
Vout = 3.3 V
Vout = 5 V
20%
10%
0
0.001
0.01
0.1
Output Current (A)
1
3
3207
TPS563207S Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Instruments
Incorporated
intellectual
property
matters
and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 6
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Receiving Notification of Documentation Updates..17
12.2 Support Resources................................................. 17
12.3 Trademarks............................................................. 17
12.4 Electrostatic Discharge Caution..............................17
12.5 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
DATE
REVISION
NOTES
October 2020
*
Initial release
5 Device Comparison Table
2
PART NUMBER
WORK MODE IN LIGHT LOADING
TPS563207S
FCCM
TPS563202S
ECO
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6 Pin Configuration and Functions
VIN
1
6
FB
SW
2
5
EN
GND
3
4
BST
Figure 6-1. 6-Pin SOT563 DRL Package (Top View)
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VIN
1
I
Input voltage supply pin
SW
2
O
Switch node connection between high-side NFET and low-side NFET
GND
3
—
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive FB to this GND at a single point.
BST
4
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1-µF capacitor between
BST and SW pin.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
FB
6
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input voltage
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
BST
–0.3
25
V
BST (10 ns transient)
–0.3
27
V
BST (vs SW)
–0.3
6.5
V
FB
–0.3
6.5
V
–2
19
V
–3.5
21
V
SW
SW (10 ns transient)
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
VI
Input voltage range
TJ
NOM
MAX
4.3
17
BST
–0.1
23
BST (10 ns transient)
–0.1
26
BST (vs SW)
–0.1
6
EN
–0.1
17
FB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Operating junction temperature
UNIT
V
V
°C
7.4 Thermal Information
TPS563207S
THERMAL METRIC(1)
DRL
UNIT
6 PINS
RθJA
4
Junction-to-ambient thermal resistance
board(2)
137.0
°C/W
RθJA_effective
Junction-to-ambient thermal resistance with TI EVM
65.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.2
°C/W
RθJB
Junction-to-board thermal resistance
22.0
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
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TPS563207S
THERMAL METRIC(1)
DRL
UNIT
6 PINS
ψJB
(1)
(2)
Junction-to-board characterization parameter
21.8
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
This RθJA_effective is tested on TPS563207SEVM board (2 layer, copper thickness is 2 oz) at VIN = 12 V, VOUT = 5 V, IOUT = 3 A , TA =
25°C.
7.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
590
750
µA
1
3
µA
1.35
1.6
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 1 V
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
0.9
1.05
REN
EN pin resistance to GND
VEN = 12 V
225
400
794
V
V
900
kΩ
806
818
mV
0
±0.1
µA
VFB VOLTAGE
VFBTH
VFB threshold voltage
TA = 25°C
IFB
VFB input current
VFB = 1 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
95
mΩ
RDS(on)l
Low-side switch resistance
TA = 25°C
57
mΩ
MOSFET
CURRENT LIMIT
Iocl
Low side current limit
Inductor valley current set point.
INocl_l_sink
Low side FET sink current
limit
Inductor Negative valley current set point.
3.3
4.4
5.6
A
1
1.5
2
A
THERMAL SHUTDOWN
Thermal shutdown
threshold(1)
TSDN
Shutdown temperature
172
°C
Hysteresis
37
Minimum off time
VFB = 0.5 V
220
Soft-start time
Internal soft-start time， test Vout from 10% to 90%
1.2
ms
Switching frequency
VO = 1.05 V
580
kHz
ON-TIME TIMER CONTROL
tOFF(MIN)
310
ns
SOFT START
Tss
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE
VUVP
Output UVP threshold
Hiccup detect (H > L)
65%
THICCUP_WAIT Hiccup on time
THICCUP_RE
Hiccup time before restart
2.2
ms
18.3
ms
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage
(1)
4.0
3.3
3.6
4.3
V
0.4
Not production tested.
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7.6 Typical Characteristics
0.7
814
0.65
812
FB Voltage (mV)
Buck Quiescent Current (mA)
VIN = 12 V (unless otherwise noted)
0.6
0.55
0.5
0.45
-20
10
40
70
Junction Temperature (oC)
100
800
-50
130
1.4
1.16
1.38
1.12
1.08
100
130
Vref
1.36
1.34
1.04
1.32
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
1.3
-40
140
-20
0
ENOF
Figure 7-3. EN Pin EN Off Voltage vs Junction
Temperature
150
90
Low Side Rdson (m:)
100
130
110
90
70
20
40
60
80
100
Junction Temperature (°C)
120
140
ENON
Figure 7-4. EN Pin EN On Voltage vs Junction
Temperature
170
50
-40
10
40
70
Junction Temperature (°C)
Figure 7-2. FB Voltage vs Junction Temperature
1.2
1
-40
-20
IQ
EN On Voltage (V)
EN Off Voltage (V)
806
802
Figure 7-1. Supply Current vs Junction
Temperature
High Side Rdson (m:)
808
804
0.4
-50
80
70
60
50
40
-20
0
20
40
60
80
100
Junction Temperature (°C)
120
Figure 7-5. High-Side Rds-On vs Junction
Temperature
6
810
140
30
-40
-20
HSR
0
20
40
60
80
100
Junction Temperature (°C)
120
140
LSR
Figure 7-6. Low-Side Rds-On vs Junction
Temperature
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630
630
600
600
Switching Frequency(kHz)
Switching Frequency(kHz)
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570
540
Vout = 1.05V
Vout = 3.3V
Vout = 5V
510
480
6
8
10
12
Input Voltage(V)
14
16
18
Vout = 1.05V
Vout = 3.3V
Vout = 5V
510
0
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
90%
50%
40%
10%
0
0.001
0.01
0.1
Output Current (A)
1
0
0.001
3
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
10%
0
0.001
0.01
0.1
Output Current (A)
1
0.01
0.1
Output Current (A)
3
1p05
40%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
20%
10%
0
0.001
1p5e
Figure 7-11. VOUT = 1.5-V Efficiency, L = 2.2 μH
1
50%
30%
3
freq
Figure 7-10. VOUT = 1.05-V Efficiency, L = 1.5 μH
90%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
3
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
0p95
40%
2.7
40%
10%
50%
2.4
50%
100%
20%
1.2 1.5 1.8 2.1
Output Current(A)
20%
Figure 7-9. VOUT = 0.95-V Efficiency, L = 1.5 µH
30%
0.9
30%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
20%
0.6
Figure 7-8. Switching Frequency vs Output Current
100%
30%
0.3
freq
Figure 7-7. Switching Frequency vs Input Voltage
Efficiency
540
480
4
Efficiency
570
0.01
0.1
Output Current (A)
1
3
1p8e
Figure 7-12. VOUT = 1.8-V Efficiency, L = 2.2 μH
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100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
SLUSED9 – OCTOBER 2020
50%
40%
30%
10%
0
0.001
0.01
0.1
Output Current (A)
1
Vin = 9V
Vin = 12V
Vin = 17V
20%
10%
3
0
0.001
3p3e
Figure 7-13. VOUT = 3.3-V Efficiency, L = 3.3 μH
8
40%
30%
Vin = 5 V
Vin = 9 V
Vin = 12 V
Vin = 17 V
20%
50%
0.01
0.1
Output Current(A)
1
3
5eff
Figure 7-14. VOUT = 5-V Efficiency, L = 4.7 μH
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8 Detailed Description
8.1 Overview
The TPS563207S is a 3-A synchronous buck converter. The proprietary D-CAP2 mode control supports lowESR output capacitors, such as specialty polymer capacitors and multi-layer ceramic capacitors, without
complex external compensation circuits. The fast transient response of D-CAP2 mode control can reduce the
output capacitance required to meet a specific level of performance.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563207S is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one-shot timer expires. This one-shot duration is set proportionally to the converter input voltage, VIN, and
inversely proportional to the output voltage, V O, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to
reference voltage to simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2
mode control.
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8.3.2 Soft Start and Pre-Biased Soft Start
The TPS563207S has an internal 1.2-ms soft start. When the EN pin becomes high, the internal soft-start
function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at start-up, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage V FB. This scheme ensures that the
converters ramp up smoothly into regulation point.
8.3.3 Current Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain-to-source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current I out. If the monitored current is
above the OCL level, the converter keeps the low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current is higher than
the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current can be higher than the current available
from the converter. This can cause the output voltage to fall. When the FB voltage falls below the UVP threshold
voltage, the UVP comparator detects it. The device will then shut down after the UVP delay time (typically 24 µs)
and re-start after the hiccup time (typically 18.3 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
The TPS563207S also implements the negative overcurrent protection which can prevent inductor current run
away. When the inductor valley current hits the negative overcurrent threshold, the low-side FET will turn off,
then high-side FET will turn on.
8.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than the UVLO threshold
voltage, the device is shut off. This protection is non-latching.
8.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
8.4 Device Functional Modes
8.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS563207S can operate in their normal switching modes. In continuous conduction mode (CCM), the
TPS563207S operates at a quasi-fixed frequency of 580 kHz.
8.4.2 Standby Operation
The TPS563207S can be placed in standby mode by asserting the EN pin low. In standby mode, high side and
low side both turn off, and Iq is less than 3 µA.
10
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TPS563207S device is a typical buck DC-DC converter. It is typically used to convert a higher DC voltage to
a lower DC voltage with a maximum available output current of 3 A. The following design procedure can be used
to select component values for the TPS563207S. Alternately, the WEBENCH® software can be used to generate
a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
9.2 Typical Application
The application schematic in Figure 9-1 was developed to meet the previous requirements. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 9-1 shows the TPS563207S 4.3-V to 17-V input, 1.05-V output converter schematics.
Figure 9-1. TPS563207S 1.05-V/3-A Reference Design
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9.2.1 Design Requirements
Table 9-1 shows the design parameters for this application.
Table 9-1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
4.3 to 17 V
Output voltage
1.05 V
Transient response, 1.5-A load step
ΔVout = ±5%
Input ripple voltage
100 mV
Output ripple voltage
20 mV
Output current rating
3A
Operating frequency
580 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%
tolerance or better divider resistors. Start by using Equation 1 to calculate VOUT.
To improve efficiency at very light loads, consider using larger value resistors. Too high of resistance will be more
susceptible to noise and voltage errors from the FB input current will be more noticeable.
Vout=0.806 x (1 + RFBT/RFBB)
(1)
9.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
fP
1
2S LOUT u COUT
(2)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement, use the values recommended in Table 9-2.
Table 9-2. Recommended Component Values
12
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
TYP L1 (μH)
0.85
0.55
10.0
0.9
1.2
10.0
C8 + C9 (µF)
CFF (pF)
MIN
TYP
MAX
1.5
20
44
110
-
1.5
20
44
110
-
1
2.4
10.0
1.5
20
44
110
-
1.05
3
10.0
1.5
20
44
110
-
1.2
4.9
10.0
2.2
20
44
110
-
1.5
8.6
10.0
2.2
20
44
110
-
1.8
12.3
10.0
2.2
20
44
110
-
2.5
21
10.0
2.2
20
44
110
10-220
3.3
31
10.0
3.3
20
44
110
10-220
5
52
10.0
4.7
20
44
110
10-220
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Table 9-2. Recommended Component Values (continued)
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
TYP L1 (μH)
6.5
70.5
10.0
6.8
C8 + C9 (µF)
MIN
TYP
MAX
20
44
110
CFF (pF)
10-220
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 3,
Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
IlP
P
IlPEAK
ILO(RMS)
VIN(MAX) VOUT
VOUT
u
VIN(MAX)
LO u fSW
IO
(3)
IlP P
2
IO2
(4)
1
IlP
12
2
P
(5)
The selection of minimum inductor must keep IIP-P smaller than 2 A.
For this design example, the calculated peak current is 3.68 A and the calculated RMS current is 3.03 A. The
inductor used is a WE 74437349015.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563207S is intended for
use with ceramic or other low-ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation
6 to determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(6)
For this design, two MuRata GRM21BR61A226ME44L 22-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
9.2.2.3 Input Capacitor Selection
The TPS563207S requires an input decoupling capacitor and a bulk capacitor, depending on the application. TI
recommends a ceramic capacitor over 10 µF for the decoupling capacitor. A 0.1-µF capacitor (C3) from pin 3 to
ground is suggested to add to filtering high frequency noise. The capacitor voltage rating needs to be greater
than the maximum input voltage.
9.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the BST to SW pin for proper operation. TI recommends
to use a ceramic capacitor.
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9.2.3 Application Curves
1.07
1.07
1.06
1.06
Output Voltage(V)
Output Voltage(V)
Below waveforms are tested at VIN = 12 V, unless otherwise noted.
1.05
1.04
1.05
1.04
1.03
1.03
0
0.5
1
1.5
2
Output Current(A)
2.5
3
4
Load
Figure 9-2. Load Regulation with Different Loading
6
8
10
12
Input Voltage(V)
14
16
18
Load
Figure 9-3. Load Regulation with Different Input
Voltage
Vin = 5V/div
Vin = 100mV/div
Vout = 500mV/div
Iout = 2A/div
VSW = 5V/div
SW = 5V/div
IL = 2A/div
1 us/div
10 ms/div
Figure 9-4. Input Voltage Ripple Iout = 3 A
Figure 9-5. Hiccup (Short Vout Test)
Vout = 20mV/div
Vout = 20mV/div
Iout = 2A/div
SW = 5V/div
SW = 5V/div
Iout = 2A/div
14
1 us/div
1 us/div
Figure 9-6. Output Voltage Ripple, Iout = 10 mA
Figure 9-7. Output Voltage Ripple, Iout = 3 A
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Vout = 50mV/div
Vout = 50mV/div
Iout = 2A/div
Iout = 2A/div
400 us/div
400 us/div
Figure 9-8. Transient Load Response, Iout = 0.3 to
2.7 A
Figure 9-9. Transient Load Response, Iout = 1.5 to
3A
Vin = 5V/div
Vin = 5V/div
VEN = 2V/div
VEN = 2V/div
Vout = 500mV/div
Vout = 500mV/div
2 ms/div
2 ms/div
Figure 9-10. Start-Up Relative to EN
Figure 9-11. Shutdown Relative to EN
Vin = 5V/div
Vin = 5V/div
VEN = 5V/div
VEN = 5V/div
Vout = 500mV/div
Vout = 500mV/div
2 ms/div
2 ms/div
Figure 9-12. Start-Up Relative to VIN
Figure 9-13. Shutdown Relative to VIN
10 Power Supply Recommendations
The TPS563207S is designed to operate from input supply voltage in the range of 4.3 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 75%. Using that criteria, the minimum recommended input voltage is VO / 0.75.
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11 Layout
11.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the FB node should be as small as possible to avoid noise coupling.
10.The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
11.2 Layout Example
VIN
GND
CIN
SW
RFBB
VIN
FB
SW
EN
GND
BST
RFBT
EN
Control
CBST
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
VIA (Connected to SW)
Figure 11-1. TPS563207S Layout
16
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
D-CAP2™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS563207SDRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
S307
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
