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TPS563201, TPS563208
SLVSD90 – DECEMBER 2015
TPS56320x 4.5-V to 17-V Input, 3-A Synchronous Step-Down Voltage Regulator in SOT-23
1 Features
3 Description
•
The TPS563201 and TPS563208 are simple, easy-touse, 3 A synchronous step-down converters in SOT23 package.
1
•
•
•
•
•
•
•
•
•
•
•
•
TPS563201 and TPS563208 3-A Converter
Integrated 95-mΩ and 57-mΩ FETs
D-CAP2™ Mode Control with fast transient
response
Input Voltage Range: 4.5 V to 17 V
Output Voltage Range: 0.76 V to 7 V
Pulse-skip mode (TPS563201) or Continuous
Current Mode (TPS563208)
580-kHz Switching Frequency
Low Shutdown Current Less than 10 µA
2% Feedback Voltage Accuracy (25 ºC)
Startup from Pre-Biased Output Voltage
Cycle-by-Cycle Overcurrent Limit
Hiccup-mode Overcurrent Protection
Non-Latch UVP and TSD Protections
Fixed Soft Start: 1.0 ms
The devices are optimized to operate with minimum
external component counts and also optimized to
achieve low standby current.
These switch mode power supply (SMPS) devices
employ D-CAP2 mode control providing a fast
transient response and supporting both lowequivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors
with
no
external
compensation
components.
TPS563201 operates in pulse skip mode, which
maintains high efficiency during light load operation.
The TPS563201 and TPS563208 are available in a 6pin 1.6-mm × 2.9-mm SOT (DDC) package, and
specified from a –40°C to 125°C junction
temperature.
2 Applications
•
•
•
•
•
Device Information(1)
Digital TV Power Supply
High Definition Blu-ray™ Disc Players
Networking Home Terminal
Digital Set Top Box (STB)
Surveillance
PART NUMBER
TPS563201
TPS563208
PACKAGE
DDC (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
TPS563201 Efficiency
100%
90%
TPS563201
2
VOUT
COUT
3
VIN
CIN
GND VBST
SW
EN
VIN
VFB
6
5
4
80%
70%
EN
VOUT
Efficiency
1
60%
50%
40%
VOUT = 1.05 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
30%
20%
10%
0.001
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D023
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS563201, TPS563208
SLVSD90 – DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
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SLVSD90 – DECEMBER 2015
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
6
VBST
SW
2
5
EN
VIN
3
4
VFB
Pin Functions
PIN
NAME
I/O
NO.
DESCRIPTION
GND
1
—
Ground pin Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
3
I
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
4
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
VBST
6
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
VBST
–0.3
25
V
VBST (10 ns transient)
–0.3
27
V
VBST (vs SW)
–0.3
6.5
V
VFB
–0.3
6.5
V
V
SW
–2
19
–3.5
21
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
SW (10 ns transient)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLVSD90 – DECEMBER 2015
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
VI
Input voltage range
TJ
NOM
MAX
4.5
17
VBST
–0.1
23
VBST (10 ns transient)
–0.1
26
VBST (vs SW)
–0.1
6.0
EN
–0.1
17
VFB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Operating junction temperature
UNIT
V
V
°C
6.4 Thermal Information
TPS56320x
THERMAL METRIC (1)
DDC (SOT)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
92.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.5
°C/W
RθJB
Junction-to-board thermal resistance
15.5
°C/W
ψJT
Junction-to-top characterization parameter
2.5
°C/W
ψJB
Junction-to-board characterization parameter
15.5
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLVSD90 – DECEMBER 2015
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
TPS563201
380
520
TPS563208
590
750
1
10
UNIT
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 0.8 V
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
µA
µA
LOGIC THRESHOLD
VENH
EN high-level input voltage
EN
VENL
EN low-level input voltage
EN
REN
EN pin resistance to GND
VEN = 12 V
1.6
225
V
400
0.8
V
900
kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB threshold voltage
VO = 1.05 V, IO = 10 mA, Eco-mode™ operation
VFB threshold voltage
VO = 1.05 V, continuous mode operation
VFB input current
VFB = 0.8 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – SW = 5.5 V
95
mΩ
RDS(on)l
Low-side switch resistance
TA = 25°C
57
mΩ
VFBTH
IVFB
774
749
mV
768
787
mV
0
±0.1
µA
MOSFET
CURRENT LIMIT
Iocl
Current limit
DC current, VOUT = 1.05 V, L1 = 1.5 µH
3.3
4.2
5.1
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
172
°C
Hysteresis
37
Minimum off time
VFB = 0.5 V
220
Soft-start time
Internal soft-start time
1.0
ms
Switching frequency
VIN = 12 V, VO = 1.05 V, FCCM mode
580
kHz
ON-TIME TIMER CONTROL
tOFF(MIN)
310
ns
SOFT START
Tss
FREQUENCY
Fsw
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
THICCUP_WAIT
Hiccup on time
Hiccup detect (H > L)
65%
1.8
ms
THICCUP_RE
Hiccup time before restart
15
ms
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage
(1)
4.0
3.3
4.3
3.6
V
0.4
Not production tested.
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.764
0.55
0.763
0.5
FB Voltage (V)
Buck Quiescent Current (mA)
0.6
0.45
0.4
0.762
0.761
0.76
0.35
0.3
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
0.759
-40
140
-20
0
D001
Figure 1. TPS563201 Supply Current vs Junction
Temperature
20
40
60
80
100
Junction Temperature (qC)
120
140
D002
Figure 2. VFB Voltage vs Junction Temperature
1.23
1.5
EN Pin UVLO - High (V)
EN Pin UVLO - Low (V)
1.2
1.17
1.14
1.11
1.08
1.47
1.44
1.41
1.38
1.05
1.02
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
1.35
-40
140
0
170
100
150
90
130
110
90
70
20
40
60
80
100
Junction Temperature (qC)
120
140
D004
Figure 4. EN Pin UVLO High Voltage vs Junction
Temperature
Low Side Rds_on (m:)
High-Side Rds_on (m:)
Figure 3. EN Pin UVLO Low Voltage vs Junction
Temperature
80
70
60
50
40
50
-40
-20
0
20
40
60
80
100
Junction Temperature (qC)
120
140
30
-40
-20
0
D005
Figure 5. High-Side Rds-On vs Junction Temperature
6
-20
D003
20
40
60
80
100
Junction Temperature (qC)
120
140
D006
Figure 6. Low-Side Rds-On vs Junction Temperature
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SLVSD90 – DECEMBER 2015
Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
600
VOUT = 1.8 V
VOUT = 3.3 V
VOUT = 5 V
600
Switching Frequency (kHz)
Switching Frequency (kHz)
620
580
560
540
500
VOUT = 1.05 V
VOUT = 3.3 V
VOUT = 5 V
400
300
200
100
520
0
0.001
500
4
6
8
10
12
Input Voltage (V)
14
16
18
0.005
D007
IOUT = 10 mA
90%
90%
80%
80%
70%
70%
Efficiency
Efficiency
100%
60%
50%
40%
2 3
D008
60%
50%
40%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
30%
20%
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
30%
20%
10%
0.001
2 3
0.005
D009
Figure 9. TPS563201 VOUT = 1.05 V Efficiency, L = 2.2 µH
100%
90%
90%
80%
80%
70%
70%
60%
50%
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D010
Figure 10. TPS563201 VOUT = 1.5 V Efficiency, L = 2.2 µH
100%
Efficiency
Efficiency
1
Figure 8. TPS563201 Switching Frequency vs Output
Current
100%
60%
50%
40%
40%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
30%
20%
10%
0.001
0.5
VIN = 12 V
Figure 7. TPS563208 Switching Frequency vs Input Voltage
10%
0.001
0.02 0.05 0.1 0.2
Output Current (A)
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
30%
20%
2 3
10%
0.001
0.005
D011
Figure 11. TPS563201 VOUT = 1.8 V Efficiency, L = 2.2 µH
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D012
Figure 12. TPS563201 VOUT = 3.3 V Efficiency, L = 2.2 µH
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
100%
90%
90%
80%
80%
70%
Efficiency
Efficiency
70%
60%
50%
40%
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
0
0.001
2 3
90%
80%
80%
70%
70%
60%
60%
Efficiency
Efficiency
90%
50%
40%
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D014
Figure 14. TPS563208 VOUT = 1.05 V Efficiency, L = 2.2 µH
100%
30%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
0
0.001
2 3
0.005
D015
Figure 15. TPS563208 VOUT = 1.5 V Efficiency, L = 2.2 µH
90%
90%
80%
80%
70%
70%
60%
60%
Efficiency
100%
50%
40%
30%
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D016
Figure 16. TPS563208 VOUT = 1.8 V Efficiency, L = 2.2 µH
100%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
0
0.001
0.005
D013
100%
0
0.001
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
10%
Figure 13. TPS563201 VOUT = 5 V Efficiency, L = 3.3 µH
Efficiency
40%
20%
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
0.005
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
20%
VIN = 9 V
VIN = 12 V
VIN = 15 V
10%
2 3
0
0.001
0.005
D017
Figure 17. TPS563208 VOUT = 3.3 V Efficiency, L = 2.2 µH
8
50%
30%
30%
10%
0.001
60%
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D018
Figure 18. TPS563208 VOUT = 5 V Efficiency, L = 3.3 µH
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7 Detailed Description
7.1 Overview
The TPS563201 and TPS563208 are 3-A synchronous step-down converters. The proprietary D-CAP2 mode
control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic
capacitors without complex external compensation circuits. The fast transient response of D-CAP2 mode control
can reduce the output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN
5
VUVP
VOVP
VFB
+
UVP
±
Hiccup
Control Logic
+
OVP
±
3
VIN
6
VBST
2
SW
1
GND
VREG5
Regulator
UVLO
4
Voltage
Reference
Ref
Soft Start
SS
PWM
±
+
+
HS
tON
One-Shot
XCON
VREG5
TSD
OCL
Threshold
LS
±
OCL
+
+
ZC
±
7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS563201 and TPS563208 is adaptive on-time pulse width modulation (PWM)
controller that supports a proprietary D-CAP2 mode control. The D-CAP2 mode control combines adaptive ontime control with an internal compensation circuit for pseudo-fixed frequency and low external component count
configuration with both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the
output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely
proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence
it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again
when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2 mode control.
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Feature Description (continued)
7.3.2 Pulse Skip Control (TPS563201)
The TPS563201 is designed with advanced Eco-mode to maintain high light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when the zero inductor current is detected. As the load
current further decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the
same as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. This makes the switching frequency lower,
proportional to the load current, and keeps the light load efficiency high. The transition point to the light load
operation IOUT(LL) current can be calculated in Equation 1.
(V
VOUT ) u VOUT
1
u IN
IOUT(LL)
2 u L u fSW
VIN
(1)
7.3.3 Soft Start and Pre-Biased Soft Start
The TPS563201 and TPS563208 have an internal 1-ms soft-start. When the EN pin becomes high, the internal
soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the devices initiate switching and start ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.4 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device will shut down after the UVP delay time
(typically 24 µs) and re-start after the hiccup time (typically 15 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.5 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.6 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
10
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7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS563201 and TPS563208 can operate in their normal switching modes. Normal continuous conduction mode
(CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS563201 and TPS563208 operate
at a quasi-fixed frequency of 580 kHz.
7.4.2 Eco-mode Operation
When the TPS563201 and TPS563208 are in the normal CCM operating mode and the switch current falls to 0
A, the TPS563201 and TPS563208 begin operating in pulse skipping Eco-mode. Each switching cycle is
followed by a period of energy saving sleep time. The sleep time ends when the VFB voltage falls below the Ecomode threshold voltage. As the output current decreases, the perceived time between switching pulses
increases.
7.4.3 Standby Operation
When the TPS563201 and TPS563208 are operating in either normal CCM or Eco-mode, they may be placed in
standby by asserting the EN pin low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The devices are typical step-down DC-DC converters. It typically uses to convert a higher dc voltage to a lower
dc voltage with a maximum available output current of 3 A. The following design procedure can be used to select
component values for the TPS563201 and TPS563208. Alternately, the WEBENCH® software may be used to
generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a
comprehensive database of components when generating a design. This section presents a simplified discussion
of the design process.
8.2 Typical Application
The application schematic in Figure 19 was developed to meet the previous requirements. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 19 shows the TPS563201 and TPS563208 4.5-V to 17-V input, 1.05-V output converter schematics.
C7 0.1 F
1
L1
VOUT = 1.05 V/3A
2
VOUT
GND
VBST
SW
EN
VIN
VFB
6
R3 10 k
5
EN
2.2 H
C9
22 F
C8
22 F
3
4
VOUT
R1 3.09 k
R2
10 k
1
C1
10 F
C2
10 F
C3
0.1 F
Not Installed
C4
1
VIN
VIN = 4.5 V to 17 V
1
Figure 19. TPS563201 and TPS563208 1.05-V/3-A Reference Design
12
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
EXAMPLE VALUE
Input voltage range
4.5 to 17 V
Output voltage
1.05 V
ΔVout = ±5%
Transient response, 1.5-A load step
Input ripple voltage
400 mV
Output ripple voltage
30 mV
Output current rating
3A
Operating frequency
580 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1 ·
§
VOUT
0.768 u ¨ 1
R2 ¸¹
©
(2)
8.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
2S LOUT u COUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 3 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
1
3.09
1.05
1.2
L1 (µH)
C8 + C9 (µF)
MIN
TYP
MAX
10.0
1.5
2.2
4.7
20 to 68
3.74
10.0
1.5
2.2
4.7
20 to 68
5.76
10.0
1.5
2.2
4.7
20 to 68
1.5
9.53
10.0
1.5
2.2
4.7
20 to 68
1.8
13.7
10.0
1.5
2.2
4.7
20 to 68
2.5
22.6
10.0
2.2
2.2
4.7
20 to 68
3.3
33.2
10.0
2.2
2.2
4.7
20 to 68
5
54.9
10.0
3.3
3.3
4.7
20 to 68
6.5
75
10.0
3.3
3.3
4.7
20 to 68
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The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5, and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
VIN(MAX) VOUT
VOUT
IlP P
u
VIN(MAX)
LO u fSW
(4)
IlPEAK
IlP P
2
IO
IO2
ILO(RMS)
(5)
1
IlP
12
2
P
(6)
For this design example, the calculated peak current is 3.5 A and the calculated RMS current is 3.01 A. The
inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS563201 and TPS563208
are intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68
µF. Use Equation 7 to determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(7)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.
8.2.2.3 Input Capacitor Selection
The TPS563201 and TPS563208 require an input decoupling capacitor and a bulk capacitor is needed
depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An
additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The
capacitor voltage rating needs to be greater than the maximum input voltage.
8.2.2.4 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
8.2.3 Application Curves
3%
3%
TPS563201
TPS563208
1%
0
-1%
-2%
1%
0
-1%
-2%
-3%
-3%
0
0.5
1
1.5
2
Output Current (A)
2.5
3
0
0.5
D019
Figure 20. TPS563201 and TPS563208 Load Regulation,
VIN = 5 V
14
TPS563201
TPS563208
2%
Output Voltage (V)
Output Voltage (V)
2%
1
1.5
2
Output Current (A)
2.5
3
D020
Figure 21. TPS563201 and TPS563208 Load Regulation,
VIN = 12 V
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100%
1.055
TPS563201
TPS563208
1.054
90%
80%
70%
1.052
Efficiency
Output Voltage (V)
1.053
1.051
1.05
60%
50%
40%
1.049
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
30%
1.048
20%
1.047
4
6
8
10
12
Input Voltage (V)
14
16
18
10%
0.001
0.005
D021
0.02 0.05 0.1 0.2
Output Current (A)
0.5
1
2 3
D022
IOUT of TPS563201: 1 A
IOUT of TPS563208: 10 mA
Figure 22. TPS563201 and TPS563208 Line Regulation
Figure 23. TPS563201 Efficiency
VOUT = 100 mV/div
VIN = 100 mV/div
LX = 5 V/div
LX = 5 V/div
IOUT = 2 A/div
IL = 500 mA/div
800 ns/div
20 µs/div
Figure 24. TPS563201 Input Voltage Ripple
Figure 25. TPS563201 Output Voltage Ripple, 10 mA
VOUT = 20 mV/div
VOUT = 20 mV/div
LX = 5 V/div
LX = 5 V/div
IL = 2 A/div
IL = 500 mA/div
1 µs/div
1 µs/div
Figure 26. TPS563201 Output Voltage Ripple, Iout = 0.25 A
Figure 27. TPS563201 Output Voltage Ripple, Iout = 2 A
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VOUT = 10 mV/div
VOUT = 50 mV/div
SW = 5 V/div
IOUT = 1 A/div
800 ns/div
100 µs/div
Figure 28. TPS563208 Output Voltage Ripple, IOUT = 0 A
VOUT = 20 mV/div
Figure 29. TPS563201 Transient Response, 0.1 to 1.5 A
VOUT = 20 mV/div
IOUT = 1 A/div
IOUT = 1 A/div
100 µs/div
100 µs/div
Figure 30. TPS563201 Transient Response, 0.75 to 2.25 A
Figure 31. TPS563208 Transient Response 0.1 to 2 A
VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
VOUT = 500 mV/div
2 ms/div
400 µs/div
Figure 32. TPS563201 Start Up Relative to VI
16
Figure 33. TPS563201 Start-Up Relative to EN
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VIN = 5 V/div
VIN = 5 V/div
VEN = 5 V/div
VEN = 5 V/div
VOUT = 500 mV/div
VOUT = 500 mV/div
10 ms/div
100 µs/div
Figure 34. TPS563201 Shutdown Relative to VI
Figure 35. TPS563201 Shutdown Relative to EN
9 Power Supply Recommendations
TPS563201 and TPS563208 are designed to operate from input supply voltage in the range of 4.5 V to 17 V.
Buck converters require the input voltage to be higher than the output voltage for proper operation. The
maximum recommended operating duty cycle is 75%. Using that criteria, the minimum recommended input
voltage is VO / 0.75.
10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
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10.2 Layout Example
VOUT
GND
Vias to the
Internal SW
Node Copper
Additional
Vias to the
GND Plane
Output
Capacitor
BOOST
CAPACITOR
Output
Inductor
GND
SW
Vias to the
Internal SW
Node Copper
Input Bypass
Capacitor
VIN
VIN
VBST
EN
To Enable
Control
Feedback
Resistors
VFB
SW Node Copper
Pour Area on
Internal
or Bottom Layer
Figure 36. TPS563201 and TPS563208 Layout
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS563201
Click here
Click here
Click here
Click here
Click here
TPS563208
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
D-CAP2, Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS563201DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
3201
TPS563201DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
3201
TPS563208DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
3208
TPS563208DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
3208
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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