TPS563219EVM-663

User's Guide SLVUAB5 – October 2014 TPS563219EVM-663 3-A, Regulator Evaluation Module This user's guide contains information for the TPS563219 as well as support documentation for the TPS563219EVM-663 evaluation module. Included are the performance specifications, schematic, and the bill of materials of the TPS563219EVM-663. 1 2 3 4 5 6 Contents Introduction ................................................................................................................... 2 Performance Specification Summary ..................................................................................... 2 Modifications.................................................................................................................. 3 3.1 Output Voltage Setpoint............................................................................................ 3 Test Setup and Results ..................................................................................................... 4 4.1 Input/Output Connections .......................................................................................... 4 4.2 Start-Up Procedure ................................................................................................. 4 4.3 Efficiency ............................................................................................................. 5 4.4 Load Regulation..................................................................................................... 6 4.5 Line Regulation ..................................................................................................... 7 4.6 Load Transient Response ......................................................................................... 7 4.7 Output Voltage Ripple .............................................................................................. 8 4.8 Input Voltage Ripple ................................................................................................ 8 4.9 Start-Up .............................................................................................................. 9 4.10 Shut-Down ......................................................................................................... 10 Board Layout ................................................................................................................ 11 5.1 Layout ............................................................................................................... 11 Schematic, Bill of Materials, and Reference ............................................................................ 12 6.1 Schematic .......................................................................................................... 12 6.2 Bill of Materials .................................................................................................... 13 6.3 Reference .......................................................................................................... 14 List of Figures ........................................................................................... 1 TPS563219EVM-663 Efficiency 2 TPS563219EVM-663 Light Load Efficiency .............................................................................. 5 3 TPS563219EVM-663 Load Regulation, 5 V Input ....................................................................... 6 4 TPS563219EVM-663 Load Regulation, 12 V Input ..................................................................... 6 5 TPS563219EVM-663 Line Regulation .................................................................................... 7 6 TPS563219EVM-663 Load Transient Response, 25% to 75% Load Step........................................... 7 7 TPS563219EVM-663 Output Voltage Ripple, IOUT = 3 A ................................................................ 8 8 TPS563219EVM-663 Input Voltage Ripple, IOUT = 3 A .................................................................. 8 9 TPS563219EVM-663 Start-Up Relative to VIN ........................................................................... 9 10 TPS563219EVM-663 Start-Up Relative to EN ........................................................................... 9 11 TPS563219EVM-663 Shut-Down Relative to VIN 12 TPS563219EVM-663 Shut-Down Relative to EN ...................................................................... 10 13 Top Assembly ............................................................................................................... 11 14 Top Layer.................................................................................................................... 11 15 Bottom Layer ................................................................................................................ 12 ...................................................................... 5 10 D-CAP2 is a trademark of Texas Instruments. SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 1 Introduction 16 www.ti.com TPS563219EVM-663 Schematic Diagram .............................................................................. 12 List of Tables 1 1 Input Voltage and Output Current Summary ............................................................................. 2 2 TPS563219EVM-663Performance Specifications Summary........................................................... 2 3 Output Voltages .............................................................................................................. 3 4 Connection and Test Points ................................................................................................ 4 5 Bill of Materials ............................................................................................................. 13 Introduction The TPS563219 is a single, adaptive on-time, D-CAP2™ mode, synchronous buck converter requiring a very low external component count. The D-CAP2 control circuit is optimized for low-ESR output capacitors such as POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. The slow start time is externally programmable and there is a dedicated Power Good (PG) pin to aid in voltage monitoring and sequencing. The switching frequency is internally set at a nominal 650 kHz. The high-side and low-side switching MOSFETs are incorporated inside the TPS563219 package along with the gate-drive circuitry. The low drain-to-source on resistance of the MOSFETs allows the TPS563219 to achieve high efficiencies and helps keep the junction temperature low at high output currents. The TPS563219 dc/dc synchronous converter is designed to provide up to a 3-A output from an input voltage source of 4.5 V to 17 V. The output voltage range is from 0.8 V to 6.5 V. Rated input voltage and output current ranges for the evaluation module are given in Table 1. The TPS563219EVM-663 evaluation module (EVM) is a single, synchronous buck converter providing 1.05 V at 3 A from 4.5-V to 17-V input. This user’s guide describes the TPS563219EVM-663 performance. Table 1. Input Voltage and Output Current Summary 2 EVM Input Voltage Range Output Current Range TPS563219EVM-663 VIN = 4.5 V to 17 V 0 A to 3 A Performance Specification Summary A summary of the TPS563219EVM-663 performance specifications is provided in Table 2. Specifications are given for an input voltage of VIN = 12 V and an output voltage of 1.05 V, unless otherwise noted. The ambient temperature is 25°C for all measurement, unless otherwise noted. Table 2. TPS563219EVM-663Performance Specifications Summary Specifications Test Conditions Input voltage range (VIN) Min Typ Max 4.5 12 17 Output voltage Operating frequency CH1 2 VIN = 12 V, IO = 3 A Output current range VIN = 12 V, LO = 1.5 µH Output ripple voltage VIN = 12 V, IO = 3 A TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated V 1.05 V 650 kHz 0 Over current limit Unit 3 A A 20 mVPP SLVUAB5 – October 2014 Submit Documentation Feedback Modifications www.ti.com 3 Modifications These evaluation modules are designed to provide access to the features of the TPS563219. Some modifications can be made to this module. 3.1 Output Voltage Setpoint To change the output voltage of the EVMs, it is necessary to change the value of resistor R1. Changing the value of R1 can change the output voltage above 0.765 V. The value of R1 for a specific output voltage can be calculated using Equation 1. R2 ´ (VOUT - 0.765 V ) R1 = 0.765 V (1) Table 3 lists the R1 values for some common output voltages. Note that the values given in Table 3 are standard values and not the exact value calculated using Table 3. Table 3. Output Voltages L1 (µH) Output Voltage (V) R1 (kΩ) R2 (kΩ) Min Typ Max 1.0 3.09 10.0 1.5 2.2 4.7 20 - 68 1.05 3.74 10.0 1.5 2.2 4.7 20 - 68 1.2 5.76 10.0 1.5 2.2 4.7 20 - 68 1.5 9.53 10.0 1.5 2.2 4.7 20 - 68 1.8 13.7 10.0 1.5 2.2 4.7 20 - 68 2.5 22.6 10.0 2.2 3.3 4.7 20 - 68 3.3 33.2 10.0 2.2 3.3 4.7 20 - 68 5.0 54.9 10.0 3.3 4.7 4.7 20 - 68 6.5 75.0 10.0 3.3 4.7 4.7 20 - 68 SLVUAB5 – October 2014 Submit Documentation Feedback C5 + C6 +C7 (µF) TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 3 Test Setup and Results 4 www.ti.com Test Setup and Results This section describes how to properly connect, set up, and use the TPS563219EVM-663. The section also includes test results typical for the evaluation modules and efficiency, output load regulation, output line regulation, load transient response, output voltage ripple, input voltage ripple, start-up, and switching frequency. 4.1 Input/Output Connections The TPS563219EVM-663 is provided with input/output connectors and test points as shown in Table 4. A power supply capable of supplying 3 A must be connected to J1 through a pair of 20-AWG wires. The load must be connected to J2 through a pair of 20-AWG wires. The maximum load current capability is 3 A. Wire lengths must be minimized to reduce losses in the wires. Test point TP1 provides a place to monitor the VIN input voltages with TP2 providing a convenient ground reference. TP7 is used to monitor the output voltage with TP8 as the ground reference. Table 4. Connection and Test Points 4.2 Reference Designator Function J1 VIN (see Table 1 for VIN range) J2 VOUT, 1.05 V at 3-A maximum JP1 EN control. Shunt EN to GND to disable, shunt EN to VIN to enable. TP1 VIN positive monitor point TP2 GND monitor test point TP3 EN test point TP4 Switch node test point TP5 Test point for loop response measurements TP6 VOUT positive monitor point TP7 GND monitor test point Start-Up Procedure 1. Ensure that the jumper at JP1 (Enable control) pins 1 and 2 are covered to shunt EN to GND, disabling the output. 2. Apply appropriate VIN voltage to VIN (J1-2) and GND (J1-1). See Table 1 for VIN voltage range. 3. Move the jumper at JP1 (Enable control) from pins 1 and 2 (EN and GND), to pins 2 and 3 (EN and VIN) enabling the output. 4 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback Test Setup and Results www.ti.com 4.3 Efficiency Figure 1 shows the efficiency for the TPS563219EVM-663 at an ambient temperature of 25°C. 100 90 80 Efficiency (%) 70 60 50 40 30 20 10 VIN = 5V VIN = 12V 0 0 0.5 1 1.5 Output Current (A) 2 2.5 3 D001 Figure 1. TPS563219EVM-663 Efficiency Figure 2 shows the efficiency at light loads for the TPS563219EVM-663 at an ambient temperature of 25°C. 100 90 80 Efficiency (%) 70 60 50 40 30 20 10 0 0.001 VIN = 5V VIN = 12V 0.002 0.003 0.005 0.01 0.02 0.03 0.05 0.07 0.1 Output Current (A) 0.2 0.3 0.4 0.5 0.7 1 2 3 4 5 D002 Figure 2. TPS563219EVM-663 Light Load Efficiency SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 5 Test Setup and Results 4.4 www.ti.com Load Regulation The load regulation for the TPS563219EVM-663 is shown in Figure 3 and Figure 4. 1 0.8 0.6 Load Regulation (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 0.5 1 1.5 Output Current (A) 2 2.5 3 D003 Figure 3. TPS563219EVM-663 Load Regulation, 5 V Input 1 0.8 0.6 Load Regulation (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 0.5 1 1.5 Output Current (A) 2 2.5 3 D004 Figure 4. TPS563219EVM-663 Load Regulation, 12 V Input 6 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback Test Setup and Results www.ti.com 4.5 Line Regulation The line regulation for the TPS563219EVM-663 is shown in Figure 5. 0.5 0.4 0.3 Line Regulation (%) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 4 6 8 10 12 Input Voltage (V) 14 16 18 D005 Figure 5. TPS563219EVM-663 Line Regulation 4.6 Load Transient Response The TPS563219EVM-663 response to load transient is shown in Figure 6. The current steps and slew rates are indicated in the figures. Total peak-to-peak voltage variation is as shown. VO = 50 mV / div (ac coupled) IO = 1 A / div Load step = 0.75 A - 2.25 A, slew rate = 500 mA / µsec Time = 200 µsec / div Figure 6. TPS563219EVM-663 Load Transient Response, 25% to 75% Load Step SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 7 Test Setup and Results 4.7 www.ti.com Output Voltage Ripple The TPS563219EVM-663 output voltage ripple is shown in Figure 7. The output currents are as indicated. VO = 20 mV / div (ac coupled) SW = 5 V / div Time = 1 µsec / div Figure 7. TPS563219EVM-663 Output Voltage Ripple, IOUT = 3 A 4.8 Input Voltage Ripple The TPS563219EVM-663 input voltage ripple is shown in Figure 8. The output current is as indicated. VI = 50 mV / div (ac coupled) SW = 5 V / div Time = 1 µsec / div Figure 8. TPS563219EVM-663 Input Voltage Ripple, IOUT = 3 A 8 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback Test Setup and Results www.ti.com 4.9 Start-Up The TPS563219EVM-663 start-up waveform relative to VIN is shown in Figure 9. Load = 1 Ω resistive. VI = 10 V / div SS = 5 V / div VO = 500 mV / div PG = 1 V / div Time = 1 msec / div Figure 9. TPS563219EVM-663 Start-Up Relative to VIN The TPS563219EVM-663 start-up waveform relative to enable (EN) is shown in Figure 10. Load = 1 Ω resistive. EN = 10 V / div SS = 5 V / div VO = 500 mV / div PG = 1 V / div Time = 1 msec / div Figure 10. TPS563219EVM-663 Start-Up Relative to EN SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 9 Test Setup and Results www.ti.com 4.10 Shut-Down The TPS563219EVM-663 shut-down waveform relative to VIN is shown in Figure 11. Load = 1 Ω resistive. VI = 10 V / div SS = 5 V / div VO = 500 mV / div PG = 1 V / div Time = 5 msec / div Figure 11. TPS563219EVM-663 Shut-Down Relative to VIN The TPS563219EVM-663 shut-down waveform relative to EN is shown in Figure 12. Load = 1 Ω resistive. EN = 10 V / div SS = 5 V / div VO = 500 mV / div PG = 1 V / div Time = 5 msec / div Figure 12. TPS563219EVM-663 Shut-Down Relative to EN 10 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback Board Layout www.ti.com 5 Board Layout This section provides a description of the TPS563219EVM-663, board layout, and layer illustrations. 5.1 Layout The board layout for the TPS563219EVM-663 is shown in Figure 13, Figure 14 and Figure 15. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS563219 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network. Figure 13. Top Assembly Figure 14. Top Layer SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 11 Schematic, Bill of Materials, and Reference www.ti.com Figure 15. Bottom Layer 6 Schematic, Bill of Materials, and Reference 6.1 Schematic Figure 16 is the schematic for the TPS563219EVM-663. U1 TPS563219DDF TP1 J1 TP4 VIN = 4.5 - 17 V L1 1.5uH VIN VBST EN SW TP7 VOUT = 1.05 V C5 3 J2 8 0.1µF C1 0.1µF TP2 GND C2 10µF R4 10.0k C3 10µF 7 PG SH-JP1 JP1 TP3 5 3 2 1 SS VFB GND TP5 2 JP2 C6 22µF SH-JP2 R5 4 100k 6 C7 22µF C8 22µF TP6 R3 TP8 0 R1 3.74k GND GND 1 C4 8200pF R2 10.0k GND GND GND GND Figure 16. TPS563219EVM-663 Schematic Diagram 12 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback Schematic, Bill of Materials, and Reference www.ti.com 6.2 Bill of Materials Table 5. Bill of Materials Designator Quantity Value !PCB1 1 C1, C5 2 0.1uF C2, C3 2 C4 Part Number Manufacturer Printed Circuit Board PWR663 Any CAP, CERM, 0.1uF, 25V, +/-10%, X5R, 0603 0603 GRM188R61E104KA01D MuRata 10uF CAP, CERM, 10uF, 25V, +/-10%, X5R, 1210 1210 GRM32DR61E106KA12L MuRata 1 8200pF CAP, CERM, 8200pF, 25V, +/-10%, X7R, 0603 0603 GRM188R71E822KA01D MuRata C6, C7, C8 3 22uF CAP, CERM, 22uF, 10V, +/-10%, X7R, 1206 1206 GRM31CR71A226KE15L MuRata J1, J2 2 Terminal Block, 6A, 3.5mm Pitch, 2Pos, TH 7.0x8.2x6.5mm ED555/2DS On-Shore Technology JP1 1 Header, 100mil, 3x1, Tin, TH Header, 3 PIN, 100mil, Tin PEC03SAAN Sullins Connector Solutions JP2 1 Header, 100mil, 2x1, Tin, TH Header, 2 PIN, 100mil, Tin PEC02SAAN Sullins Connector Solutions L1 1 Inductor, Shielded Drum Core, Superflux, 1.5uH, 11A, 0.0078 ohm, SMD WE-HC4 744311150 Wurth Elektronik eiSos LBL1 1 Thermal Transfer Printable Labels, 1.250" W x 0.250" H - 10,000 per roll PCB Label 1.25"H x 0.250"W THT-13-457-10 Brady R1 1 3.74k RES, 3.74k ohm, 1%, 0.1W, 0603 0603 CRCW06033K74FKEA Vishay-Dale R2, R4 2 10.0k RES, 10.0k ohm, 1%, 0.1W, 0603 0603 CRCW060310K0FKEA Vishay-Dale R3 1 0 RES, 0 ohm, 5%, 0.1W, 0603 0603 ERJ-3GEY0R00V Panasonic R5 1 100k RES, 100k ohm, 1%, 0.1W, 0603 0603 CRCW0603100KFKEA Vishay-Dale SH-JP1, SH-JP2 2 1x2 Shunt, 100mil, Gold plated, Black Shunt 969102-0000-DA 3M TP1, TP7 2 Red Test Point, Miniature, Red, TH Red Miniature Testpoint 5000 Keystone TP2, TP8 2 Black Test Point, Miniature, Black, TH Black Miniature Testpoint 5001 Keystone TP3, TP5, TP6 3 White Test Point, Miniature, White, TH White Miniature Testpoint 5002 Keystone TP4 1 Yellow Test Point, Miniature, Yellow, TH Yellow Miniature Testpoint 5004 Keystone U1 1 TPS56X21X 4.5V to 17 V Input, Synchronous Step-Down Voltage Regulator DDF0008A DDF0008A TPS563219DDF Texas Instruments 1.5uH Description Package Reference SLVUAB5 – October 2014 Submit Documentation Feedback TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated 13 Schematic, Bill of Materials, and Reference 6.3 www.ti.com Reference 1. TPS56x219 4.5 V to 17 V Input, 2-A/3-A Synchronous Step-Down Voltage Regulator in SOT-23 data sheet (SLVSCM7) 14 TPS563219EVM-663 3-A, Regulator Evaluation Module Copyright © 2014, Texas Instruments Incorporated SLVUAB5 – October 2014 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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