TPS56339DDCT

Order Now Product Folder Support & Community Tools & Software Technical Documents TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 TPS56339 4.5-V to 24-V Input, 3-A Output Synchronous Buck Converter 1 Features 3 Description • • • • • • • • • • • The TPS56339 is a 4.5-V to 24-V input voltage range, 3-A synchronous buck converter. The device includes two integrated switching MOSFETs, internal loop compensation and 5-ms internal soft-start to reduce component count. By employing the SOT-23 (6) package, the device achieves the high power density and offers small footprint on PCB. 1 • • • Input voltage range: 4.5 V to 24 V Output voltage range: 0.8 V to 16 V 3-A maximum continuous output current Fixed 500-kHz switching frequency Support up to 97% duty cycle Integrated 70-mΩ and 35-mΩ MOSFETs Typical 3-μA shutdown current Typical 98-μA quiescent current Internal 5-ms soft-start Internal loop compensation for ease use Cycle-by-cycle current limit for both high-side and low-side MOSFETs Non-latched UVP, UVLO and TSD protections SOT-23 (6) package Create a custom design using TPS56339 with the WEBENCH® Power Designer 2 Applications • • • 12-V, 19-V distributed power-bus supply Industrial applications – Video surveillance and security systems – Appliance Consumer application – Digital TV and LCD monitors – Wireless and intelligent speakers The TPS56339 employs Advanced Emulated Current Mode (AECM) control that can get fast transient response with fixed frequency. The internal adaptive loop adjustment eliminates the need for external compensation over a wide voltage output range. Cycle-by-cycle current limit on the high-side protects the device in current overload conditions and is enhanced by a low-side sourcing current limit which prevents current runaway. Hiccup protection will be triggered under undervoltage and thermal shutdown protections. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS56339 SOT-23 (6) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS56339 Efficiency Simplified Schematic 100 TPS56339 6 Rboot 3 VIN VIN 95 BOOT Cin Cboot 90 Lo 2 GND Rfb1 5 EN 4 EN 85 VOUT SW FB Co Rfb2 Efficiency (%) 1 80 75 70 65 60 Vin=12V, Vout=5V Vin=19V, Vout=5V Vin=12V, Vout=3.3V Vin=19V, Vout=3.3V 55 50 45 0.001 0.01 0.1 Load Current (A) 1 5 Eff- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview ................................................................... 9 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 14 7.5 Light-Load Operation .............................................. 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 22 10.1 Layout Guidelines ................................................. 22 10.2 Layout Example .................................................... 22 11 Device and Documentation Support ................. 24 11.1 11.2 11.3 11.4 11.5 11.6 Receiving Notification of Documentation Updates Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 24 24 24 24 24 24 12 Mechanical, Packaging, and Orderable Information ........................................................... 24 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (November 2018) to Revision A • 2 Page Changed marketing status from Advance Information to initial release. ................................................................................ 1 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 TPS56339 www.ti.com SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 5 Pin Configuration and Functions DDC Package 6-Pin SOT Top View GND 1 6 BOOT SW 2 5 EN VIN 3 4 FB Pin Functions PIN I/O (1) DESCRIPTION NAME NO. BOOT 6 O A 30-Ω boot resistor and a 0.1-μF bootstrap cap are required between BOOT and SW. The voltage on this cap carries the gate drive voltage for the high-side MOSFET. EN 5 I Enable pin. Float to enable. Adjust the input undervoltage lockout with two resistors. FB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider. GND 1 G Ground pin. Source terminal of low-side MOSFET as well as the ground terminal for controller circuit. Connect sensitive FB to this GND at a single point. SW 2 O Switch node connection between high-side MOSFET and low-side MOSFET. VIN 3 I Input voltage supply pin. The drain terminal of high-side MOSFET. (1) I = Input, O = Output, G = GND Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 3 TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted) (1) Input voltages Output voltages MIN MAX VIN –0.3 26 EN –0.3 6 BOOT –0.3 SW+6 FB –0.3 6 BOOT-SW –0.3 6 SW –0.3 26 –3 26 SW ( 5V. The COUT_E is the effective value after derating, the value of L1·COUT_E should be within in the range. The capacitor value and ESR determines the amount of output voltage ripple. TheTPS56339 is intended for use with ceramic or other low ESR capacitors. Use Equation 15 to determine the required RMS current rating for the output capacitor. ICORMS VOUT ˜ (VIN_MAX VOUT ) 12 ˜ VIN_MAX ˜ L1 ˜ fSW (15) For this design two Murata GRM21BR61C226ME44 22-uF, 0805, 16-V output capacitors are used. From the data sheet the estimated DC derating of 51.8% at room temperature with AC voltage of 0.2V. The total output effective capacitance is approximately 22.8 μF. The value of L1·COUT_E is 127.7 μH×μF, which is within the recommended range. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 17 TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com 8.2.2.5 Input Capacitor Selection The TPS56339 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor (C3) from VIN pin to ground is recommended to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS56339. The input ripple current can be calculated using Equation 16. ICIRMS IOUT ˜ VOUT VIN_MIN VOUT ˜ VIN_MIN VIN_MIN (16) The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 35-V voltage rating is required to support the maximum input voltage. For this example, two Murata GRM21BR6YA106KE43L (10-μF, 35-V, 0805, X5R) capacitors have been selected. The effective capacitance under input voltage of 12 V for each one is 0.269 × 10 = 2.69 μF. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 17. Using the design example values, IOUT_MAX = 3 A, CIN_E = 2 × 2.69 = 5.38 μF, fSW = 500 kHz, yields an input voltage ripple of 279 mV and a RMS input ripple current of 1.48 A. 'VIN IOUT _ MAX ˜ 0.25 CIN ˜ fSW (IOUT _ MAX ˜ RESR _ MAX ) where • RESR_MAX is the maximum series resistance of the input capacitor (17) 8.2.2.6 Bootstrap Capacitor Selection A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. TI recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10-V or higher voltage rating. In addition, TI recommends in series one boot resistor to make the device more robust, so a 30-Ω of R3 are required to be used between BOOT to bootstrap capacitor, C4. 8.2.3 Undervoltage Lockout Set Point The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is connected between VIN and the EN pin of the TPS56339 and R2 is connected between EN and GND . The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. For the example design, the supply should turn on and start switching when the input voltage increases above 6.6 V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 5.7 V (UVLO stop or disable). Equation 1 and Equation 2 can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified the nearest standard resistor value for R1 is 174 kΩ and for R2 is 36.5 kΩ. 18 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 TPS56339 www.ti.com SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 8.2.4 Application Curves VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted) 100 5.3 95 5.2 Output Voltage (V) Efficiency (%) 90 85 80 75 70 65 Vin = 6.5 V Vin = 12 V Vin = 19 V 60 55 0.001 0.01 0.1 Load Current (A) 1 5.1 5 4.9 Vin = 6.5 V Vin = 12 V Vin = 19 V 4.8 4.7 0.001 5 0.01 Eff- Figure 18. Efficiency 0.1 Load Current (A) 1 5 Load Figure 19. Load Regulation 5.15 5.2 5 4.8 Output Voltage (V) Output Voltage (V) 5.1 5.05 5 4.6 4.4 4.2 4 3.8 4.95 Iout = 0.03 A Iout = 3 A Iout = 0.5 A Iout = 1.5 A Iout = 3 A 3.6 4.9 3.4 6 8 10 12 14 16 18 Input Voltage (V) 20 22 24 4 4.25 Line Figure 20. Line Regulation 4.5 4.75 5 5.25 5.5 5.75 Input Voltage (V) 6 6.25 6.5 Drop Figure 21. Dropout Curve 70 65 Case Temperature (qC) Vin(AC) = 200 mV/div 60 55 Vout(AC) = 50 mV/div 50 45 SW = 10 V/div 40 IL = 1 A/div 35 Vin = 12 V Vin = 19 V 30 0.5 0.75 1 1.25 1.5 1.75 2 2.25 Load Current (A) 2.5 2.75 Time = 4 ms/div 3 Case Figure 23. Steady State Waveforms, IOUT = 0 A Figure 22. Case Temperature Rise vs Load Current Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 19 TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted) Vin(AC) = 200 mV/div Vout(AC) = 20 mV/div Vin(AC) = 200 mV/div Vout(AC) = 20 mV/div IL = 2 A/div IL = 1 A/div SW = 10 V/div SW = 10 V/div Time = 1 µs/div Time = 2 µs/div Figure 24. Steady State Waveforms, IOUT = 0.3 A Figure 25. Steady State Waveforms, IOUT = 3 A Vout(AC) = 100 mV/div Vout(AC) = 100 mV/div Iout = 2 A/div Iout = 2 A/div Time = 100 s/div Time = 100 s/div Figure 26. Transient Response 1.5 to 3 A Figure 27. Transient Response 0.3 to 2.7 A Vin = 10 V/div Vin = 10 V/div Vout = 5 V/div Vout = 5 V/div IL = 2 A/div IL = 2 A/div SW = 5 V/div Time = 2 ms/div Figure 28. Startup Relative to VIN 20 SW = 5 V/div Time = 800 µs/div Submit Documentation Feedback Figure 29. Shutdown Relative to VIN Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 TPS56339 www.ti.com SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 VIN = 12 V, L1= 5.6 µH, COUT = 44 µF, TA = 25 °C. (unless otherwise noted) Ven = 5 V/div Ven = 5 V/div Vout = 5 V/div Vout = 5 V/div IL = 2 A/div IL = 2 A/div SW = 10 V/div Time = 2 ms/div SW = 10 V/div Time = 200 µs/div Figure 30. Enable Relative to EN Figure 31. Disable Relative to EN Vin = 10 V/div Vin = 10 V/div Vout = 5 V/div Vout = 5 V/div IL = 5 A/div IL = 5 A/div SW = 10 V/div SW = 10 V/div Time = 20 ms/div Time = 20 ms/div Figure 33. Short Recovery Figure 32. Short Protection 9 Power Supply Recommendations The devices are designed to operate from an input voltage supply range between 4.5 V and 24 V. This input supply must be well regulated. If the input supply is located more than a few inches from the device or converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitor. An electrolytic capacitor with a value of 47 μF is a typical choice. The 0.1-µF ceramic bypass capacitor should be as close as possible to VIN and GND pins. Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 21 TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com 10 Layout 10.1 Layout Guidelines 1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation. 2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize trace impedance. 3. The 0.1-µF ceramic bypass capacitor should be as close as possible to VIN and GND pins. 4. Provide sufficient vias for the input capacitor and output capacitor. 5. Keep the SW trace as physically short and wide as practical to minimize radiated emissions. 6. Do not allow switching current to flow under the device. 7. A separate VOUT path should be connected to the upper feedback resistor. 8. Make a Kelvin connection to the GND pin for the feedback path. 9. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has ground shield. 10. The trace of the VFB node should be as small as possible to avoid noise coupling. 11. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its trace impedance. 10.2 Layout Example Figure 34. TPS56339 Top Layout Example 22 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 TPS56339 www.ti.com SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 Layout Example (continued) Figure 35. TPS56339 Bottom Layout Example Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 23 TPS56339 SLVSEI2A – NOVEMBER 2018 – REVISED MAY 2019 www.ti.com 11 Device and Documentation Support 11.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 24 Submit Documentation Feedback Copyright © 2018–2019, Texas Instruments Incorporated Product Folder Links: TPS56339 PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS56339DDCR ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T6339 TPS56339DDCT ACTIVE SOT-23-THIN DDC 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 T6339 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of