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TPS565208
SLVSE72B – SEPTEMBER 2017 – REVISED JUNE 2018
TPS565208 4.5-V to 17-V Input, 5-A Synchronous Step-Down Voltage Regulator in SOT-23
1 Features
3 Description
•
•
•
The TPS565208 is a simple, easy-to-use, 5-A
synchronous step-down converter in SOT-23
package.
1
•
•
•
•
•
•
•
•
•
•
•
•
5-A Maximum Output Current
Integrated 31-mΩ and 16-mΩ FETs
D-CAP2™ Mode Control with Fast Transient
Response
Input Voltage Range: 4.5 V to 17 V
Output Voltage Range: 0.76 V to 7 V
Continuous Current Mode
500-kHz Switching Frequency
Low Shutdown Current of Less than 1 µA
1% Feedback Voltage Accuracy
Startup from Pre-biased Output Voltage
Cycle-by-Cycle Current Limit
Hiccup-mode Overcurrent Protection
Non-Latch UVP and TSD Protections
Fixed Soft Start: 1.0 ms
Create a Custom Design Using the TPS565208
With the WEBENCH® Power Designer
The device is optimized to operate with minimum
external component count and also optimized to
achieve low standby current.
This switch mode power supply (SMPS) device
employs D-CAP2™ mode control, which provides fast
transient response and requires no external
compensation components. D-CAP2™ also allows
the use of low-equivalent series resistance (ESR)
specialty polymer capacitors and ceramic capacitors.
The TPS565208 is available in a 6-pin 1.6-mm × 2.9mm SOT (DDC) package, and operates over a –40°C
to 125°C junction temperature range.
Device Information(1)
PART NUMBER
TPS565208
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
DDC (6)
space
Digital TV Power Supply
High Definition Blu-ray™ Disc Players
Networking Home Terminal
Digital Set Top Box (STB)
Surveillance
Simplified Schematic
space
TPS565208 Load Regulation
CBST
TPS565208
1
LO
6
GND
VBST
5
2
VOUT
SW
CO
EN
3
VIN
EN
4
VIN
VOUT
VFB
RFB2 RFB1
CIN
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS565208
SLVSE72B – SEPTEMBER 2017 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 11
8
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Development Support ...........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2017) to Revision B
•
Added Tape and Reel information with improved yield. ....................................................................................................... 20
Changes from Original (September 2017) to Revision A
•
2
Page
Page
Initial public release. .............................................................................................................................................................. 1
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SLVSE72B – SEPTEMBER 2017 – REVISED JUNE 2018
5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
GND
1
6
VBST
SW
2
5
EN
VIN
3
4
VFB
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
1
—
Ground pin. Source terminal of low-side power NFET as well as the ground terminal for
controller circuit. Connect sensitive VFB to this GND at a single point.
SW
2
O
Switch node connection between high-side NFET and low-side NFET.
VIN
3
I
Input voltage supply pin. The drain terminal of high-side power NFET.
VFB
4
I
Converter feedback input. Connect to output voltage with feedback resistor divider.
EN
5
I
Enable input control. Active high and must be pulled up to enable the device.
VBST
6
O
Supply input for the high-side NFET gate drive circuit. Connect 0.1 µF capacitor between
VBST and SW pins.
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SLVSE72B – SEPTEMBER 2017 – REVISED JUNE 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN, EN
–0.3
19
V
VBST
–0.3
25
V
VBST (10 ns transient)
–0.3
27
V
VBST (vs SW)
–0.3
6.5
V
VFB
–0.3
6.5
V
SW
–2
19
V
–3.5
21
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Input voltage
SW (10 ns transient)
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Supply input voltage range
VI
Input voltage range
TJ
NOM
MAX
4.5
17
VBST
–0.1
23
VBST (10 ns transient)
–0.1
26
VBST (vs SW)
–0.1
6.0
EN
–0.1
17
VFB
–0.1
5.5
SW
–1.8
17
SW (10 ns transient)
–3.5
20
–40
125
Operating junction temperature
UNIT
V
V
°C
6.4 Thermal Information
TPS565208
THERMAL METRIC (1)
DDC (SOT)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
95.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.6
°C/W
RθJB
Junction-to-board thermal resistance
16.4
°C/W
ψJT
Junction-to-top characterization parameter
1.4
°C/W
ψJB
Junction-to-board characterization parameter
16.4
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IVIN
Operating – non-switching
supply current
VIN current, EN = 5 V, VFB = 1 V
590
780
µA
IVINSDN
Shutdown supply current
VIN current, EN = 0 V
0.8
5
µA
LOGIC THRESHOLD
VENH
EN high-level input voltage
VENL
EN low-level input voltage
REN
EN pin resistance to GND
1.6
VEN = 12 V
V
0.8
V
400
kΩ
120
245
753
760
767
mV
0
±0.1
µA
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFBTH
VFB threshold voltage
IVFB
VFB input current
TA = 25°C, VFB = 0.8 V
RDS(on)h
High-side switch resistance
TA = 25°C, VBST – VSW= 5.5 V
31
mΩ
RDS(on)l
Low-side switch resistance
TA = 25°C
16
mΩ
MOSFET
CURRENT LIMIT
IOCL
Current limit
5.3
6.7
8
A
THERMAL SHUTDOWN
TSDN
Thermal shutdown
threshold (1)
Shutdown temperature
172
Hysteresis
°C
38
ON-TIME TIMER CONTROL
tOFF(MIN)
Minimum off time
VFB = 0.61 V
236
280
ns
Soft-start time
Internal soft-start time
1.0
ms
Switching frequency
VIN = 12 V, VOUT = 5 V, CCM mode
500
kHz
65
%
1.8
ms
14.9
ms
SOFT START
tSS
FREQUENCY
FSW
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VUVP
Output UVP threshold
THICCUP_WAIT
Hiccup on time
THICCUP_RE
Hiccup time before restart
Hiccup detect (H > L)
UVLO
Wake up VIN voltage
UVLO
UVLO threshold
Shutdown VIN voltage
Hysteresis VIN voltage (1)
(1)
4.0
3.3
4.3
3.6
V
0.4
Not production tested.
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
0.8
0.763
0.762
0.7
FB Voltage (V)
Buck Quiescent Current (mA)
0.75
0.65
0.6
0.55
0.761
0.76
0.5
0.759
0.45
0.4
-50
-20
10
40
70
Junction Temperature (qC)
100
0.758
-50
130
-20
D001
Figure 1. TPS565208 Supply Current vs Junction
Temperature
10
40
70
Junction Temperature (qC)
100
130
D002
Figure 2. VFB Voltage vs Junction Temperature
1.45
1.23
EN Pin UVLO - Low (V)
EN Pin UVLO - High (V)
1.2
1.42
1.39
1.36
1.17
1.14
1.11
1.08
1.33
1.05
1.3
-50
-20
10
40
70
Junction Temperature (qC)
100
1.02
-50
130
-20
D003
Figure 3. EN Pin UVLO Low Voltage vs Junction
Temperature
10
40
70
Junction Temperature (qC)
100
130
D004
Figure 4. TPS565208 EN Pin UVLO High Voltage vs Junction
Temperature
60
28
50
Low Side RDS_ON (m:)
High Side RDS_ON (m:)
55
45
40
35
30
24
20
16
25
20
-50
-30
-10
10
30
50
70
Junction Temperature (qC)
90
110
130
-30
D005
Figure 5. High-Side Rds-On vs Junction Temperature
6
12
-50
-10
10
30
50
70
Junction Temperature (qC)
90
110
130
D006
Figure 6. Low-Side Rds-On vs Junction Temperature
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
580
Vout = 1.8V
Vout = 3.3V
Vout = 5V
580
Switching Frequency (KHz)
Switching Frequency (KHz)
600
560
540
520
500
480
4
6
8
10
12
Input Voltage (V)
14
16
Vout = 1.05V
Vout = 3.3V
Vout - 5V
560
540
520
500
480
460
0.001
18
IOUT = 1 A
90%
90%
80%
80%
70%
70%
Efficiency (%)
Efficiency (%)
100%
60%
50%
40%
30%
5
D052
60%
50%
40%
30%
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
0.01
0.1
Output Current (A)
1
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
0
0.001
5
0.01
D009
Figure 9. TPS565208 VOUT = 1.05 V Efficiency, L = 2.2 µH
100%
90%
90%
80%
80%
70%
70%
60%
50%
40%
30%
0.1
Output Current (A)
1
5
D010
Figure 10. TPS565208 VOUT = 1.5 V Efficiency, L = 2.2 µH
100%
Efficiency (%)
Efficiency
1
Figure 8. TPS565208 Switching Frequency vs Output
Current
100%
60%
50%
40%
30%
Vin=5V
Vin=9V
Vin=12V
Vin=15V
20%
10%
0
0.001
0.1
Output Current (A)
VIN = 12 V
Figure 7. TPS565208 Switching Frequency vs Input Voltage
0
0.001
0.01
D054
0.01
0.1
Output Current (A)
1
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
10%
5
0
0.001
D53
Figure 11. TPS565208 VOUT = 1.8 V Efficiency, L = 2.2 µH
0.01
0.1
Output Current (A)
1
5
D012
Figure 12. TPS565208 VOUT = 3.3 V Efficiency, L = 2.2 µH
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Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
90%
80%
Efficiency (%)
70%
60%
50%
40%
30%
20%
VIN = 9 V
VIN = 12 V
VIN = 15 V
10%
0
0.001
0.01
0.1
Output Current (A)
1
5
D013
Figure 13. TPS565208 VOUT = 5 V Efficiency, L = 3.3 µH
8
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7 Detailed Description
7.1 Overview
The TPS564208 is a 5-A synchronous step-down converter. The proprietary D-CAP2™ mode control supports
low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic capacitors without
complex external compensation circuits. The fast transient response of D-CAP2™ mode control can reduce the
output capacitance required to meet a specific level of performance.
7.2 Functional Block Diagram
EN 5
VUVP
VOVP
VFB 4
Voltage
Reference
Soft Start
+
UVP
Hiccup
+
OVP
VIN
6
VBST
2
SW
1
GND
VREG5
Regulator
UVLO
+
+
+
Control Logic
3
PWM
SS
HS
+
Internal Ramp
One-Shot
XCON
VREG5
Ripple Injection
TSD
OCL
threshold
LS
OCL
+
+
ZC
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7.3 Feature Description
7.3.1 Adaptive On-Time Control and PWM Operation
The main control loop of the TPS565208 is adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive on-time control
with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration
with low-ESR ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one shot duration is set inversely proportional to the converter input voltage, VIN,
and proportional to the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range,
hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on
again when the feedback voltage falls below the reference voltage. An ripple is added to reference voltage to
simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2TM mode control.
7.3.2 Soft Start and Pre-Biased Soft Start
The TPS565208 has an internal 1.0-ms soft-start. When the EN pin becomes high, the internal soft-start function
begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converter ramps up smoothly into regulation point.
7.3.3 Current Protection
The output over-current limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The
inductor current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, and the output inductor value. During the on time of the low-side FET switch, this current decreases
linearly. The average value of the switch current is the load current IOUT. If the monitored current is above the
OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage
feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles,
the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current is higher than
the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being
limited, the output voltage tends to fall as the demanded load current may be higher than the current available
from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP
threshold voltage, the UVP comparator detects it. And then, the device shuts down after the UVP delay time
(typically 24 µs) and re-starts after the hiccup time (typically 14.9 ms).
When the over current condition is removed, the output voltage returns to the regulated value.
7.3.4 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.5 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value (typically 172°C),
the device is shut off. This is a non-latch protection.
10
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7.4 Device Functional Modes
7.4.1 Normal Operation
When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the
TPS565208 operates in the normal switching mode. Normal continuous conduction mode (CCM) occurs when
the minimum switch current is above 0 A. In CCM, the TPS565208 operates at a quasi-fixed frequency of 550
kHz.
7.4.2 Standby Operation
When the TPS565208 is operating in normal CCM, it may be placed in standby by asserting the EN pin low.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with
a maximum available output current of 5 A. The following design procedure can be used to select component
values for the TPS565208. Alternately, the WEBENCH® software may be used to generate a complete design.
The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of
components when generating a design. This section presents a simplified discussion of the design process.
8.2 Typical Application
The application schematic in Figure 14 shows the TPS565208 4.5-V to 17-V input, 1.05-V output converter
design meeting the requirements for 5-A output. This circuit is available as the evaluation module (EVM). The
sections provide the design procedure.
C7 0.1 F
TPS565208
1
L1
VOUT = 1.05 V / 5 A
2
VOUT
GND
VBST
SW
EN
VIN
VFB
6
R3 10 k
5
EN
2.2 H
C9
22 F
C8
22 F
3
4
VOUT
R1 3.74 k
R2
10 k
1
C1
10 F
C2
10 F
C3
0.1 F
Not Installed
C4
1
VIN
VIN = 4.5 V to 17 V
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Figure 14. TPS565208 1.05-V, 5-A Reference Design
12
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Typical Application (continued)
8.2.1 Design Requirements
Table 1 shows the design parameters for this application.
Table 1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
4.5 to 17 V
Output voltage
1.05 V
Transient response, 1A/us slew rate
ΔVout = ±5%
Input ripple voltage
400 mV
Output ripple voltage
20 mV
Output current rating
5A
Operating frequency
550 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS565208 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using to calculate VOUT.
To improve efficiency at very light loads consider using larger value resistors. However, using too high of
resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will
be more noticeable.
R1 ö
æ
VOUT = 0.760 ´ ç 1 +
R2 ÷ø
è
(1)
8.2.2.3 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
fP
2S LOUT u COUT
(2)
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At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40
dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain
roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor
and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the
high frequency zero but close enough that the phase boost provided be the high frequency zero provides
adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.
Table 2. Recommended Component Values
OUTPUT
VOLTAGE (V)
R1 (kΩ)
R2 (kΩ)
L1 (µH)
MIN
TYP
MAX
C8 + C9 (µF)
1
3.09
10.0
1
2.2
4.7
20 to 68
1.05
3.74
10.0
1
2.2
4.7
20 to 68
1.2
5.76
10.0
1
2.2
4.7
20 to 68
1.5
9.53
10.0
1.5
2.2
4.7
20 to 68
1.8
13.7
10.0
1.5
2.2
4.7
20 to 68
2.5
22.6
10.0
2.2
2.2
4.7
20 to 68
3.3
33.2
10.0
2.2
2.2
4.7
20 to 68
5
54.9
10.0
3.3
3.3
4.7
20 to 68
6.5
75
10.0
3.3
3.3
4.7
20 to 68
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3,
Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
Use 550 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS
current of Equation 6.
VIN(MAX) - VOUT
VOUT
IP-P =
u
VIN(MAX)
LO u fSW
(3)
IPEAK = IO +
IP -P
2
ILO(RMS) =
IO2 +
(4)
1
lP - P2
12
(5)
For this design example, the calculated peak current is 5.4 A and the calculated RMS current is 5 A. The
inductor used is a WE 744311220 with a peak current rating of 13 A and an RMS current rating of 9 A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS565208 is intended for
use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 6
to determine the required RMS current rating for the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(6)
For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.229 A.
8.2.2.4 Input Capacitor Selection
The TPS565208 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.
14
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8.2.2.5 Bootstrap Capacitor Selection
A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI
recommends to use a ceramic capacitor.
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8.2.3 Application Curves
3%
3%
TPS565208
2%
Output Voltage (%)
Output Voltage (%)
2%
1%
0
-1%
1%
0
-1%
-2%
-2%
-3%
-3%
TPS565208
0
1
2
3
Output Current (A)
VIN = 5 V
4
5
0
1
2
3
Output Current (A)
VIN = 12 V
VOUT1 = 1.05 V
D015
VOUT1 = 1.05 V
Figure 15. TPS565208 Load Regulation, VIN = 5 V
4
5
D016
Figure 16. TPS565208 Load Regulation, VIN = 12 V
1.046
100%
90%
1.044
70%
Efficiency (%)
Output Voltage (V)
80%
1.042
1.04
1.038
60%
50%
40%
30%
1.036
VIN = 5 V
VIN = 9 V
VIN = 12 V
VIN = 15 V
20%
1.034
10%
TPS565208
1.032
4
6
8
10
12
Input Voltage (V)
14
16
18
0
0.001
D017
0.01
0.1
Output Current (A)
1
5
D009
IOUT = 1 A
Figure 17. TPS565208 Line Regulation
Figure 18. TPS565208 Efficiency, Vout = 1.05 V
1 µs/div
1 µs/div
Figure 19. TPS565208 Input Voltage Ripple
16
Figure 20. TPS565208 Output Voltage Ripple, No Load
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1 µs/div
1 µs/div
Figure 21. TPS565208 Output Voltage Ripple, IOUT 2.5 A
Figure 22. TPS565208 Output Voltage Ripple, IOUT 5 A
100 µs/div
100 µs/div
Figure 23. TPS565208 Transient Response 0.1 to 2.5 A
Figure 24. TPS565208 Transient Response, 1.25 to 3.75 A
2 ms/div
100 µs/div
Figure 25. TPS565208 Transient Response, 2.5 to 5 A
Figure 26. TPS565208 Startup Relative to VIN
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20 ms/div
400 µs/div
Figure 28. TPS565208 Shutdown Relative to VIN
Figure 27. TPS565208 Startup Relative to EN
400 µs/div
Figure 29. TPS565208 Shutdown Relative to EN
9 Power Supply Recommendations
The TPS565208 is designed to operate from input supply voltage in the range of 4.5 V to 17 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation. The maximum recommended
operating duty cycle is 83%. Using that criteria, the minimum recommended input voltage is VO / 0.83.
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10 Layout
10.1 Layout Guidelines
1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
3. Provide sufficient vias for the input capacitor and output capacitor.
4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
5. Do not allow switching current to flow under the device.
6. A separate VOUT path should be connected to the upper feedback resistor.
7. Make a Kelvin connection to the GND pin for the feedback path.
8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
9. The trace of the VFB node should be as small as possible to avoid noise coupling.
10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
10.2 Layout Example
Trace on the
bottom layer
GND
VOUT
OUTPUT
CAPACITOR
Additional
Vias to the
GND plane
BOOST
CAPACITOR
GND
VBST
SW
EN
OUTPUT
INDUCTOR
VIN
VIN
TO ENABLE
CONTROL
FEEDBACK
RESISTORS
VFB
GND trace under IC
On top layer
INPUT BYPASS
CAPACITOR
GND
Figure 30. TPS565208 Layout Example
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11 Device and Documentation Support
11.1 Development Support
11.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS565208 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
D-CAP2, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
Blu-ray is a trademark of Blu-ray Disc Association.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS565208DDCR
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
5208
TPS565208DDCT
ACTIVE
SOT-23-THIN
DDC
6
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
5208
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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