TPS565242, TPS565247
SLUSEN1A – FEBRUARY 2022 – REVISED APRIL 2022
TPS56524x 3-V to 16-V Input Voltage, 5-A Synchronous Buck Converter in a SOT-563
Package
1 Features
3 Description
•
The TPS56524x is simple, easy-to-use, high power
density, high efficiency synchronous buck converter.
The device supports input voltage ranging from 3 V to
16 V and up to 5-A continuous current with a SOT-563
package.
•
•
•
Configured for a wide range of applications
– 3-V to 16-V input voltage range
– 0.6-V to 7-V output voltage range
– 0.6-V reference voltage
– ±1% reference accuracy at 25°C
– ±1.5% reference accuracy at –40°C to 125°C
– Integrated 28.2-mΩ and 15.1-mΩ RDSON FET
– 120-μA low quiescent current
– 600-kHz switching frequency
– Supports maximum 98% duty cycle operation
– Precision EN threshold voltage
– 1.39-ms fixed typical soft-start time
Ease of use and small solution size
– Eco-mode (TPS565242) and FCCM mode at
light loading (TPS565247)
– Part of a full P2P family including solutions for 4
A, 5 A, and 6 A and FCCM/ECO operation
– D-CAP3™ control topology
– Support start-up with prebiased output
– Non-latch for OV/OT/UVLO protection
– Hiccup mode for UV protection
– Cycle-by-cycle OC and NOC limit
– 6-pin SOT-563 package
Create a custom design using the TPS565242 with
the WEBENCH® Power Designer
Create a custom design using the TPS565247 with
the WEBENCH® Power Designer
The TPS56524x uses D-CAP3 topology to provide
a fast transient response and support low-ESR
output capacitors with no requirement for external
compensation. It has two grounds, GND and AGND,
which should be connected together for optimal
thermal performance. AGND also provides a good
load and line regulation. The device can support up
to 98% duty operation.
The TPS565242 operates in Eco-mode, which
maintains high efficiency during light loading. The
TPS565247 operates in FCCM mode, which keeps
the same frequency and lower output ripple during
all load conditions. It integrates complete protection
through OVP, OCP, UVLO, OTP, and UVP with
hiccup. The device is available in 1.6-mm × 1.6mm SOT-563 package and has an optimized pinout
for easy PCB layout. The junction temperature is
specified from –40°C to 125°C.
Device Information
PART NUMBER
TPS565242
2 Applications
•
•
•
TPS565247
LCD TV, STB and DVR, streaming media player
IP network camera, video doorbell, building
security gateway
WLAN/Wi-Fi access point, small business router,
rack server
1
VIN
VIN
SW
2
(1)
(1)
BODY SIZE (NOM)
SOT-563 (6)
1.60 mm × 1.60 mm
PACKAGE
For all available packages, see the orderable addendum at
the end of the data sheet.
100%
L
VOUT
90%
80%
5
4
EN
AGND
Cin
GND
3
GND
FB
RFBT
6
Cout
Efficiency
EN
70%
60%
50%
RFBB
Vout = 1.05V
Vout = 3.3V
Vout = 5V
40%
Simplified Schematic
30%
0.001
0.01
0.1
Iout (A)
1
5
TPS565242, Efficiency at VIN = 12 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS565242, TPS565247
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 14
8.1 Application Information............................................. 14
8.2 Typical Application.................................................... 14
9 Power Supply Recommendations................................20
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Receiving Notification of Documentation Updates.. 22
11.3 Support Resources................................................. 22
11.4 Trademarks............................................................. 22
11.5 Electrostatic Discharge Caution.............................. 22
11.6 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
Changes from Revision * (February 2022) to Revision A (April 2022)
Page
• Changed marketing status from Advance Information to initial release. ............................................................1
2
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5 Pin Configuration and Functions
VIN
1
6
FB
SW
2
5
EN
GND
3
4
AGND
Figure 5-1. 6-Pin SOT-563 DRL Package (Top View)
Table 5-1. Pin Functions
Pin
(1)
Type(1)
Description
Name
No.
VIN
1
I
Input voltage supply pin
SW
2
O
Switch node connection between the high-side NFET and low-side NFET
GND
3
—
Ground pin source terminal of the low-side power NFET as well as the ground terminal for controller
circuit
AGND
4
—
Ground of internal analog circuitry. Connect AGND to the GND plane.
EN
5
I
Enable input to converter. Driving EN high enables the converter.
FB
6
I
Converter feedback input. Connect to the output voltage with a feedback resistor divider.
I = Input, O = Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VIN
–0.3
18
FB, EN
–0.3
6
AGND, PGND
–0.3
0.3
–2
18
–6.5
20
Operating junction temperature range, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Input voltage
SW
Output voltage
(1)
SW (< 20 ns)
UNIT
V
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
UNIT
±2000
V
±500
JEDEC document JEP157 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
Output voltage
NOM
MAX
3
16
FB, EN
–0.1
5.5
AGND, PGND
–0.1
0.1
SW
–1
16
SW (< 20 ns)
–6
18
UNIT
V
V
Output current
IO
0
6
A
TJ
Operating junction temperature
–40
125
°C
Tstg
Storage temperature
–40
150
°C
6.4 Thermal Information
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
RθJA_effective
Junction-to-ambient thermal resistance on EVM board
6 PINS
UNIT
131.1
°C/W
58
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.6
°C/W
RθJB
Junction-to-board thermal resistance
16.4
°C/W
ΨJT
Junction-to-top characterization parameter
0.8
°C/W
YJB
Junction-to-board characterization parameter
16.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
(2)
DRL (SOT-563)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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(2)
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This RθJA_effective is tested on TPS565242EVM board (2 layer, copper thickness of top and bottom layer are 2 oz) at VIN = 12 V, VOUT =
5 V, IOUT = 5A , TA = 25oC.
6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input voltage range
IVIN
VIN
VIN supply current
IINSDN
3
16
V
No load, VEN = 5 V, VFB = 0.65 V, nonswitching, ECO version
120
µA
No load, VEN = 5 V, VFB = 0.65 V, nonswitching, FCCM version
400
µA
2
µA
VIN shutdown current
No load, VEN = 0 V
UVLO
VIN undervoltage lockout
Wake-up VIN voltage
2.75
2.92
3
UVLO
VIN undervoltage lockout
Shutdown VIN voltage
2.6
2.72
2.9
UVLO
VIN undervoltage lockout
Hysteresis VIN voltage
UVLO
200
V
V
mV
FEEDBACK VOLTAGE
VREF
FB voltage
TJ = 25°C
594
600
606
mV
VREF
FB voltage
TJ = –40°C to 125°C
591
600
609
mV
High-side MOSFET RDS(ON)
TJ = 25°C, VVIN ≥ 5 V
28.2
mΩ
High-side MOSFET RDS(ON)
TJ = 25°C, VVIN = 3 V
30.1
mΩ
RDS (ON)LO
Low-side MOSFET RDS(ON)
TJ = 25°C, VVIN ≥ 5 V
15.1
mΩ
RDS (ON)LO
Low-side MOSFET RDS(ON)
TJ = 25°C, VVIN = 3 V
16.1
mΩ
IOCL_LS
Overcurrent threshold
Valley current setpoint
INOCL
Negative overcurrent threshold
MOSFET
RDS (ON)HI (1)
5.3
6.9
8.5
A
2
3.4
4.2
A
DUTY CYCLE and FREQUENCY CONTROL
FSW
TON(MIN)
(1)
TOFF(MIN) (1)
Switching frequency
TJ = 25°C, VVOUT = 3.3 V
Minimum on time
TJ = 25°C
Minimum off time
VFB = 0.5 V
600
kHz
50
ns
100
ns
LOGIC THRESHOLD
VEN(ON)
EN threshold high level
1.07
VEN(OFF)
EN threshold low level
0.95
VENHYS
EN hystersis
REN1
EN pulldown resistor
1.18
1.33
1
1.2
V
V
180
mV
2
MΩ
1.39
ms
SOFT START
tSS
Internal soft-start time
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP trip threshold
115%
120%
tOVPDLY
OVP prop deglitch
VUVP
UVP trip threshold
55%
60%
tUVPDLY
UVP prop deglitch
256
μs
tUVPDEL
Output hiccup delay relative to SS time UVP detect
256
μs
tUVPEN
Output hiccup enable delay relative to
SS time
13
ms
155
°C
TJ = 25°C
UVP detect
125%
24
μs
65%
THERMAL PROTECTION
TOTP (2)
OTP trip threshold
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6.5 Electrical Characteristics (continued)
TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TOTPHSY (2)
(1)
(2)
6
TEST CONDITIONS
OTP hysteresis
MIN
TYP
20
MAX
UNIT
°C
Specified by design
Not production tested
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6.6 Typical Characteristics
VIN = 12 V (unless otherwise noted)
130
455
128
440
425
IVIN (uA)
IVIN (uA)
126
124
410
122
395
120
118
-40
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
380
-40
140
Figure 6-1. TPS565242 Quiescent Current
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
140
Figure 6-2. TPS565247 Quiescent Current
1.044
1.2
1.042
1.199
1.04
1.038
VEN(OFF) (V)
VEN(ON) (V)
1.198
1.197
1.196
1.195
1.036
1.034
1.032
1.03
1.194
1.028
1.193
1.192
-40
1.026
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
140
1.024
-40
Figure 6-3. Enable On Threshold Voltage
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
140
Figure 6-4. Enable Off Threshold Voltage
21
39
20
36
RDS(ON)HI (mohm)
RDS(ON)LO (mohm)
19
18
17
16
15
33
30
27
14
24
13
12
-40
-20
0
20
40
60
80
100
Junction Temperature ( oC)
Figure 6-5. Low-Side RDS(ON)
120
140
21
-40
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
140
Figure 6-6. High-Side RDS(ON)
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6.6 Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
0.602
700
0.6015
650
600
Frequency (kHz)
0.601
Vref (V0
0.6005
0.6
0.5995
550
500
450
0.599
350
0.5985
300
0.598
-40
250
-20
0
20
40
60
80
100
Junction Temperature ( oC)
120
2
140
4
6
900
12
14
16
750
640
700
650
600
550
560
480
400
320
240
500
160
450
80
400
0
1
2
3
4
Vout = 0.6V
Vout = 1.05V
Vout = 3.3V
Vout = 5V
Vout = 7V
720
Frequency(kHz)
800
0
0.001
5
0.01
Iout (A)
Figure 6-9. TPS565247 Frequency vs Loading
100%
100%
90%
90%
80%
80%
70%
70%
60%
60%
50%
40%
30%
10%
0
0.001
0.01
0.1
Iout (A)
1
Figure 6-11. TPS565242 Efficiency at 0.6 VOUT with a 0.82-μH
Inductor
1
5
50%
40%
30%
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
20%
0.1
Iout (A)
Figure 6-10. TPS565242 Frequency vs Loading
Efficiency
Efficiency
10
Vin (V)
800
Vout = 0.6V
Vout = 1.05V
Vout = 3.3V
Vout = 5V
Vout = 7V
850
8
8
Figure 6-8. Frequency vs Input Voltage at 5-A Loading
Figure 6-7. VREF Voltage
Frequency (kHz)
Vout= 0.6V
Vout= 1.05V
Vout= 3.3V
Vout= 5V
Vout= 7V
400
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
20%
10%
5
0
0.001
0.01
0.1
Iout (A)
1
5
Figure 6-12. TPS565247 Efficiency at 0.6 VOUT with a 0.82-μH
Inductor
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6.6 Typical Characteristics (continued)
VIN = 12 V (unless otherwise noted)
100%
100%
90%
90%
80%
80%
70%
Efficiency
Efficiency
70%
60%
50%
30%
20%
0.001
0.01
0.1
Iout (A)
1
50%
40%
30%
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
40%
60%
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
20%
10%
0
0.001
5
Figure 6-13. TPS565242 Efficiency at 1.05 VOUT with a 1-μH
Inductor
0.01
0.1
Iout (A)
1
5
Figure 6-14. TPS565247 Efficiency at 1.05 VOUT with a 1-μH
Inductor
100%
100%
90%
90%
80%
70%
Efficiency
Efficiency
80%
70%
60%
50%
40%
30%
VIN = 6V
VIN = 12V
VIN = 16V
50%
40%
0.001
60%
0.01
0.1
Iout (A)
1
VIN = 6V
VIN = 12V
VIN = 16V
20%
10%
0
0.001
5
Figure 6-15. TPS565242 Efficiency at 3.3 VOUT with a 2.2-μH
Inductor
0.01
0.1
Iout(A)
1
5
Figure 6-16. TPS565247 Efficiency at 3.3 VOUT with a 2.2-μH
Inductor
1
100%
90%
0.9
80%
0.8
Efficiency
Efficiency
70%
0.7
60%
50%
40%
30%
VIN = 6V
VIN = 12V
VIN = 16V
0.6
0.5
0.001
0.01
0.1
Iout (A)
1
Figure 6-17. TPS565242 Efficiency at 5 VOUT with a 2.2-μH
Inductor
VIN = 6V
VIN = 12V
VIN = 16V
20%
10%
5
0
0.001
0.01
0.1
Iout (A)
1
5
Figure 6-18. TPS565247 Efficiency at 5 VOUT with a 2.2-μH
Inductor
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7 Detailed Description
7.1 Overview
The TPS56524x is a 5-A integrated FET and BST pin synchronous step-down buck converter that operates from
3-V to 16-V input voltage (VIN) and 0.6-V to 7-V output voltage. This device also integrates the BST pin in an
internal IC and adds one AGND pin. The device employs D-CAP3 topology that provides fast transient response
with no external compensation components and an accurate feedback voltage. The proprietary D-CAP3 mode
enables low external component count, ease of design, and optimization of the power design for cost, size, and
efficiency. The topology provides a seamless transition between CCM operating mode at higher load condition
and DCM operation at lighter load condition.
The Eco-mode version allows the TPS565242 to maintain high efficiency at light load. The FCCM version allows
the TPS565247 to maintain a fixed switching frequency and lower output voltage ripple. The TPS56524x is able
to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and
ultra-low ESR ceramic capacitors.
7.2 Functional Block Diagram
UV threshold
+
UV
+
OV
VIN
OV threshold
FB
+
VREF
+
VREGOK
LDO
2.8 V /
2.5 V
Internal
VCC
+
+PWM
+
Control Logic
SS
Internal
BST
VIN
Internal
Compensaon
Internal SS
Internal VCC
On/Off time
Minimum On/Off
Light load
OCP/OVP/UVP/NOC/
TSD
Soft-Start
SW
XCON
Clock
GND
EN
+
EN Threshold
+
OCL
AGND
+
THOK
155°C /20°C
+
ZC
AGND
+
NOCL
10
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports
a proprietary DCAP3 mode control. The DCAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both
low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56524x
also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an
internal one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and
is inversely proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the
input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side
MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ripple
generation circuit is added to the reference voltage to emulate the output ripple, enabling the use of very
low-ESR output capacitors such as multilayered ceramic capacitors (MLCC). No external current sense network
or loop compensation is required for DCAP3 control topology.
7.3.2 Eco-Mode Control
The TPS56524x is designed with advanced Eco-mode to maintain high light load efficiency. As the output
current decreases from heavy load condition, the inductor current is also reduced and eventually comes
to a point that its rippled valley touches zero level, which is the boundary between continuous conduction
and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on
time is kept almost the same as it was in continuous conduction mode so that it takes longer time to discharge
the output capacitor with smaller load current to the level of the reference voltage. This makes the switching
frequency lower, proportional to the load current and keeps the light load efficiency high. The transition point to
the light load operation, IOUT(LL) current, can be calculated in Equation 1.
IOUT(LL)
(V
1
u IN
2 u L u fSW
VOUT ) u VOUT
VIN
(1)
7.3.3 Soft Start and Prebiased Soft Start
The TPS56524x has an internal fixed soft start. The EN default status is low. When the EN pin becomes high,
the internal soft-start function begins ramping up the reference voltage to the PWM comparator.
If the output capacitor is prebiased at start-up, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage, VFB. This scheme makes sure that the
converter ramps up smoothly into the regulation point.
7.3.4 Overvoltage Protection
The TPS56524x has the overvoltage protection feature. When the output voltage becomes higher than the OVP
threshold, OVP is triggered with a 24-μs deglitch time. Both the high-side MOSFET driver and the low-side
MOSFET driver are turned off. When the overvoltage condition is removed, the device returns to switching.
7.3.5 Large Duty Operation
The TPS56524x can support large duty operations up to 98% by smoothly dropping down the switching
frequency. When VIN / VOUT < 1.6 and VFB is lower than internal VREF, the switching frequency is allowed to
smoothly drop to make TON extended to implement the large duty operation and improve the performance of
the load transient performance. Please refer frequency test waveform in Figure 6-18. The minimum switching
frequency is limited to about 200 kHz.
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7.3.6 Current Protection and Undervoltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain-to-source voltage. This voltage is
proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by the
following:
•
•
•
•
VIN
VOUT
On time
Output inductor value
During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch
current is the load current, IOUT. If the monitored valley current is above the OCL level, the converter maintains a
low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until
the current level becomes OCL level or lower. In subsequent switching cycles, the on time is set to a fixed value
and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. The load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current
is being limited, the output voltage tends to fall as the demanded load current can be higher than the current
available from the converter, which can cause the output voltage to fall. When the FB voltage falls below the
UVP threshold voltage, the UVP comparator detects it and the device shuts down after the UVP delay time
(typically 256 µs) and restarts after the hiccup wait time (typically 13 ms).
When the overcurrent condition is removed, the output voltage returns to the regulated value.
The TPS565247 is a FCCM mode part. In this mode, the device has negative inductor current at light loading.
The device has NOC (negative overcurrent) protection to avoid too large negative current. NOC protection
detects the valley of inductor current. When the valley value of inductor current exceeds the NOC threshold, the
IC turns off the low side then turns on the high side. When the NOC condition is removed, the device returns to
normal switching.
Because the TPS565247 is a FCCM mode port, if the inductance is so small that the device trigger NOC, it will
cause output voltage to be higher than target value. The minimum inductance is identified as Equation 2.
(2)
7.3.7 Undervoltage Lockout (UVLO) Protection
UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,
the device is shut off. This protection is non-latching.
7.3.8 Thermal Shutdown
The device monitors the temperature of itself. If the temperature exceeds the threshold value, the device is shut
off. This is a non-latch protection.
7.4 Device Functional Modes
7.4.1 Eco-Mode Operation
The TPS565242 operates in Eco-mode, which maintains high efficiency at light loading. As the output current
decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point
where the rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on
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time is kept almost the same as it was in continuous conduction mode so that it takes longer time to discharge
the output capacitor with smaller load current to the level of the reference voltage. This makes the switching
frequency lower, proportional to the load current, and keeps the light load efficiency high.
7.4.2 FCCM Mode Control
The TPS565247 operates in forced CCM (FCCM) mode, which keeps the converter operating in continuous
current mode during light load conditions and allows the inductor current to become negative. During FCCM
mode, the switching frequency (FSW) is maintained at an almost constant level over the entire load range, which
is suitable for applications requiring tight control of the switching frequency and output voltage ripple at the cost
of lower efficiency under light load.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The device is typical buck DC/DC converters. It is typically used to convert a higher DC voltage to a lower
DC voltage with a maximum available output current of 5 A. The following design procedure can be used to
select component values for the TPS56524x. Alternately, the WEBENCH® software can be used to generate a
complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive
database of components when generating a design. This section presents a simplified discussion of the design
process.
8.2 Typical Application
The application schematic in Figure 8-1 was developed to meet the requirements in Table 8-1. This circuit is
available as the evaluation module (EVM). The sections provide the design procedure.
Figure 8-1 shows the TPS56524x 12-V input, 1.05-V output converter schematic.
VIN = 3 V to 16 V
1
VIN
C1
10 F
C2
10 F
6
VIN
C3
0.1 F
R1 7.5 k
2
5
SW
1 C4
4
GND
VOUT = 1.05 V
R2
10 k
EN
3
VOUT
VOUT
FB
AGND
R3 20 k
L1
1.0 H
C5
22
F
C6
22 F
C7
22 F
1
Not Installed
VIN
R4 30 k
Figure 8-1. Schematic
14
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8.2.1 Design Requirements
Table 8-1 shows the design parameters for this application.
Table 8-1. Design Parameters
Parameter
Example Value
Input voltage range
3 to 16 V
Output voltage
1.05 V
Transient response, 2.5-A load step
ΔVout = ±5%
Output ripple voltage
20 mV
Output current rating
5A
Operating frequency
600 kHz
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS565242 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS565247 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT.
To improve efficiency at very light loads, consider using larger value resistors because too high of resistance will
be more susceptible to noise and voltage errors from the FB input current will be more noticeable. It is suggested
to use a 10-kΩ resistor for R2 to start the design.
(3)
8.2.2.3 Output Filter Selection
The LC filter used as the output filter has a double pole at Equation 4. In this equation, COUT should use its
effective value after derating, not its nominal value.
fP
1
2S LOUT u COUT
(4)
For any control topology that is compensated internally, there is a range of the output filter it can support. At low
frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the
device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per
decade rate and the phase drops has a 180 degree drop. The internal ripple generation network introduces a
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high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and leads the 90 degree
phase boost. The internal ripple injection high-frequency zero is about 66 kHz. The inductor and capacitor
selected for the output filter is recommended that the double pole is located about 20 kHz, so that the phase
boost provided by this high-frequency zero provides adequate phase margin for the stability requirement. The
crossover frequency of the overall system should usually be targeted to be less than one-third of the switching
frequency (FSW).
Table 8-2. Recommended Component Values
Output
Voltage (V)
R1 (kΩ)
R2 (kΩ)
Minimum
L1 (μH)
Typical L1
(μH)
Maximum
L1 (μH)
Minimum
COUT (μF)
Typical
COUT (μF)
Maximum
COUT (μF)
CFF (pF)
0.6
0
10.0
0.42
0.82
2.2
44
88
220
—
1.05
7.5
10.0
0.68
1/1.5
2.2
44
66
220
—
1.8
20.0
10.0
1
1.5
2.2
44
66
220
10–470
2.5
95.0
30.0
1.2
2.2
4.7
44
66
220
10–470
3.3
135.0
30.0
1.5
2.2
4.7
44
66
220
10–470
5
220.0
30.0
2.2
2.2/3.3
6.8
44
66
220
10–470
7
320.0
30.0
2.2
3.3
6.8
44
66
220
10–470
The inductor peak-to-peak ripple current, peak current, and RMS current are calculated using Equation 5,
Equation 6, and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current.
IlP
P
IlPEAK
ILO(RMS)
VIN(MAX) VOUT
VOUT
u
VIN(MAX)
LO u fSW
IO
IlP P
2
IO2
(5)
(6)
1
IlP
12
2
P
(7)
For this design example, the calculated peak current is 5.8 A and the calculated RMS current is 5.02 A. The
inductor used is WE744311100 with 8-A saturation current and 15-A rated current.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS56524x are intended for
use with ceramic or other low-ESR capacitors. Use Equation 8 to determine the required RMS current rating for
the output capacitor.
ICO(RMS)
VOUT u VIN
VOUT
12 u VIN u LO u fSW
(8)
For this design, four MuRata GRM21BR61A226ME44L 22-µF output capacitors are used. The typical ESR is 2
mΩ each. The calculated RMS current is 0.47 A and each output capacitor is rated for 4 A.
8.2.2.4 Input Capacitor Selection
The TPS56524x requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF
capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor
voltage rating needs to be greater than the maximum input voltage.
16
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8.2.3 Application Curves
800
700
750
600
700
Frequency (kHz)
800
500
400
300
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
200
100
600
550
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
450
400
0
0.001
0.01
0.1
Iout (A)
1
0
5
1
2
3
4
5
Iout (A)
Figure 8-2. TPS565242 Frequency vs Loading
Figure 8-3. TPS565247 Frequency vs Loading
0.25%
0.25%
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
0.15%
Output voltage regulation
650
500
Output voltage regulatioin
Frequency (kHz)
The following data is tested with VIN = 12 V, VOUT = 1.05 V, TA = 25°C, unless otherwise specified.
0.05%
-0.05%
-0.15%
-0.25%
-0.35%
VIN = 3V
VIN = 6V
VIN = 12V
VIN = 16V
0.15%
0.05%
-0.05%
-0.15%
-0.25%
0
1
2
3
4
5
0
1
2
3
Iout (A)
4
5
Iout (A)
0.03%
0.03%
0.02%
0.02%
Output voltage regulation
Output voltage regulation
Figure 8-4. TPS565242 Load Regulation vs Loading Figure 8-5. TPS565247 Load Regulation vs Loading
0.01%
0
-0.01%
-0.02%
-0.03%
-0.04%
0.01%
0
-0.01%
-0.02%
-0.03%
-0.04%
-0.05%
-0.05%
2
4
6
8
10
Vin (V)
12
14
16
Figure 8-6. TPS565242 Line Regulation vs VIN with
5-A Loading
2
4
6
8
10
Vin (V)
12
14
16
Figure 8-7. TPS565247 Line Regulation vs Loading
with 5-A Loading
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Vout=20mV/div(AC coupled)
Vout=20mV/div(AC coupled)
SW=5V/div
SW=5V/div
80us/div
2us/div
Figure 8-8. TPS565242 Output Voltage Ripple with
0.01-A Loading
Figure 8-9. TPS565247 Output Voltage Ripple with
0.01-A Loading
Vout=20mV/div(AC coupled)
SW=5V/div
Vout=50mV/div(AC coupled)
74
Iout=5A/div
2us/div
200us/div
Figure 8-10. Output Voltage Ripple with 5-A
Loading
Figure 8-11. TPS565242 Transient Response with
0.5 A to 4.5 A by 2.5-A/μs Load Step
Vout=50mV/div(AC coupled)
Vout=50mV/div(AC coupled)
Iout=5A/div
Iout=5A/div
200us/div
200us/div
Figure 8-12. TPS565242 Transient Response with
0.1 A to 5 A by 2.5-A/μs Load Step
18
Figure 8-13. TPS565247 Transient Response with
0.5 A to 4.5 A by 2.5-A/μs Load Step
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Vin=5V/div
Vout=50mV/div(AC coupled)
EN=2V/div
Vout=500mV/div
Iout=5A/div
200us/div
1ms/div
Figure 8-14. TPS565247 Transient Response with
0.1 A to 5 A by 2.5-A/μs Load Step
Figure 8-15. Start-Up Through EN, IOUT = 5 A
Vin=5V/div
Vin=5V/div
EN=2V/div
EN=2V/div
52
Vout=500mV/div
Vout=500mV/div
2ms/div
4ms/div
Figure 8-16. Shutdown Through EN, IOUT = 5 A
Figure 8-17. Start-Up with VIN Rising, IOUT = 5 A
Vout=500mV/div
Vin=5V/div
EN=2V/div
SW=10V/div
Vout=500mV/div
IL=10A/div
4ms/div
80us/div
Figure 8-18. Start-Up with VIN Falling, IOUT = 5 A
Figure 8-19. TPS565242 Normal Operation to
Output Hard Short
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Vout=200mV/div
Vout=500mV/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
80us/div
4ms/div
Figure 8-20. TPS565247 Normal Operation to
Output Hard Short
Figure 8-21. Output Hard Short Hiccup
9 Power Supply Recommendations
The TPS56524x are designed to operate from input supply voltages in the range of 3 V to 16 V. Buck converters
require the input voltage to be higher than the output voltage for proper operation.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
•
•
•
20
VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also an
advantage from the view point of heat dissipation.
The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
Provide sufficient vias for the input capacitor and output capacitor.
Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
Do not allow switching current to flow under the device.
A separate VOUT path should be connected to the upper feedback resistor.
Make a Kelvin connection to the GND pin for the feedback path.
Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
The trace of the FB node should be as small as possible to avoid noise coupling.
The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.
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10.2 Layout Example
VIN
GND
CIN
SW
RFBB
VIN
FB
SW
EN
GND
RFBT
EN
Control
AGND
L
VOUT
GND
COUT
VIA (Connected to GND plane at bottom layer)
Figure 10-1. Suggested Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS565242 device with the WEBENCH® Power Designer.
Click here to create a custom design using the TPS565247 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
D-CAP3™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
22
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS565242DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
5242
Samples
TPS565247DRLR
ACTIVE
SOT-5X3
DRL
6
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
5247
Samples
XTPS565242DRLR
ACTIVE
SOT-5X3
DRL
6
4000
TBD
Call TI
Call TI
-40 to 125
Samples
XTPS565247DRLR
ACTIVE
SOT-5X3
DRL
6
4000
TBD
Call TI
Call TI
-40 to 125
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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