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TPS566235
SLVSEW1B – APRIL 2019 – REVISED APRIL 2019
TPS566235 4.5-V to 18-V Input, 6-A Synchronous Step-Down Converter
1 Features
3 Description
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The TPS566235 is a cost effective, high-voltage
input, high efficiency synchronous Buck converter
with integrated FETs. It enables system designers to
complete the suite of various end-equipment power
bus regulators with a cost effective, low component
count, low standby current solution.
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Input voltage range: 4.5 V to 18 V
Output voltage range: 0.6 V to 7 V
±1% reference voltage at room temperature
Supports 6-A continuous output current
D-CAP3™ architecture control for fast transient
response
Integrated 25-mΩ and 12-mΩ RDS(on) power FETs
108-µA low quiescent current
Selectable Eco-Mode™, Out-Of-Audio™ and
FCCM by MODE pin
Out-Of-Audio™ light-load operation with switching
frequency over 25 kHz
Supports pre-biased start up function
600-kHz switching frequency
Internal 1-ms soft start
Supports ceramic output capacitors
Power good indicator
Cycle-by-cycle valley over current protection
Non-latched for OC, OV, UV, OT and UVLO
protections
3.0-mm × 2.0-mm HotRod™ VQFN package
Create a Custom Design Using the TPS566235
With the WEBENCH® Power Designer
2 Applications
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The TPS566235 employs the D-CAP3™ mode
control that provides a fast transient response and
good line/load regulation with no external
compensation components. It also has a proprietary
circuit that enables the device to support low
equivalent series resistance (ESR) output capacitors
such as specialty polymer and ultra-low ESR ceramic
capacitors. The control topology supports seamless
transition between CCM mode at heavy load
conditions and DCM operation at light load
conditions. There are three operation modes can be
configured by MODE pin at light load: Eco-Mode™,
Out-Of-Audio™ (OOA) and Forced Continuous
Conduction Mode (FCCM). The OOA mode is a
unique control feature that keeps the switching
frequency above audible frequency with minimum
reduction in efficiency.
The TPS566235 supports pre-biased start up and
power good indicator. It provides complete protection
including OVP, UVP, OCP, OTP and UVLO. The
device is available in 3.0-mm x 2.0-mm HotRod™
package and the junction temperature is specified
from –40°C to 125°C.
Device Information(1)
DTV and STB
Switcher and router
Server and enterprise SSD
Surveillance and single board computer
Distributed power systems
PART NUMBER
TPS566235
PACKAGE
VQFN (13)
BODY SIZE (NOM)
3.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
Efficiency vs Output Current Eco-mode
100
Vout
L
Vin
SW
VIN
Cout
BST
EN
TPS566235
FB
PG
VCC
90
Efficiency (%)
Cin
80
70
60
MODE
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
50
AGND
PGND
40
0.001
0.01
0.1
I-Load (A)
1
10
D013
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS566235
SLVSEW1B – APRIL 2019 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
Absolute Maximum Ratings..................................
ESD Ratings ...........................................................
Recommended Operating Conditions .................
Thermal Information..............................................
Electrical Characteristics .....................................
1
1
1
2
3
4
4
4
4
5
5
11.1 Typical Characteristics ............................................ 7
12 Detailed Description ........................................... 10
12.1
12.2
12.3
12.4
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
10
10
11
12
13 Application and Implementation........................ 15
13.1 Application Information.......................................... 15
13.2 Typical Application ............................................... 15
14 Power Supply Recommendations ..................... 19
15 Layout................................................................... 20
15.1 Layout Guidelines ................................................. 20
15.2 Layout Example .................................................... 20
16 Device and Documentation Support ................. 21
16.1
16.2
16.3
16.4
16.5
16.6
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
17 Mechanical, Packaging, and Orderable
Information ........................................................... 22
17.1 Package Option Addendum .................................. 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2019) to Revision B
•
2
Page
Changed marketing status from Advance Information to initial release. ............................................................................... 1
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5 Pin Configuration and Functions
RJN Package
13-Pin VQFN
Top View
AGND
13
12
11
VCC
3
FB
4
PG
2
4
PGND
1
9
BST
8
SW
7
MODE
3
VIN
10
3
4
5
6
PGND
PGND
EN
PGND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
2,3,4,6
G
Power GND terminal for the controller circuit and the internal circuitry.
EN
5
I
Enable pin of Buck converter. EN pin is a digital input pin, decides turn on/off Buck converter. Internal pull
down current to disable converter if leave this pin open.
MODE
7
I
Eco-Mode™/OOA/FCCM Mode selection pin with external 1% resistor or connecting to VCC.
SW
8
O
Switching node connection to the output inductor and bootstrap capacitor.
BST
9
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW, 0.1 uF is recommended.
VCC
10
P
Internal LDO output for control and driver. Decouple with a minimum 1 μF ceramic capacitor as close to VCC
as possible.
AGND
11
G
Ground of internal analog circuitry. Connect AGND to GND plane with a short trace.
FB
12
I
Feedback sensing pin for Buck output voltage. Connect this pin to the resistor divider between output voltage
and AGND.
PG
13
O
Open drain power good indicator. It is asserted low if output voltage is out of PG threshold, over voltage or if
the device is under thermal shutdown, EN shutdown or during soft start.
VIN
PGND
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6 Specifications
7 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
Output voltage
(1)
MIN
MAX
UNIT
VIN
–0.3
20
V
BST – SW
–0.3
6
V
BST
–0.3
25
V
FB, EN, MODE
–0.3
6
V
PGND, AGND
–0.3
0.3
V
SW
–0.3
20
V
SW (10-ns transient)
–3.0
22
V
PG
–0.3
6
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
9 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage
Output voltage
IOUT
Output current (1)
TJ
Operating junction temperature
Tstg
Storage temperature
(1)
4
MAX
UNIT
VIN
4.5
18
V
BST – SW
–0.3
5.5
V
BST
–0.3
23
V
FB, EN, MODE
–0.3
5.5
V
PGND, AGND
–0.3
0.3
V
SW
–0.3
18
V
SW(10 ns transient)
–3.0
20
V
PG, VCC
–0.3
5.5
V
6
A
–40
125
°C
–40
150
°C
In order to be consistent with the TI reliability requirement of 100k Power-On-Hours at 105°C junction temperature, the output current
should not exceed 6A continuously under 100% duty operation as to prevent electromigration failure in the solder. Higher junction
temperature or longer power-on hours are achievable at lower than 6A continuous output current.
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10 Thermal Information
TPS566235
THERMAL METRIC (1)
RJN (VQFN)
UNIT
13 PINS
RθJA
Junction-to-ambient thermal resistance
70
°C/W
RθJA_effective
Junction-to-ambient thermal resistance with TI EVM
34.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.4
°C/W
RθJB
Junction-to-board thermal resistance
22.1
°C/W
ψJT
Junction-to-top characterization parameter
1.4
°C/W
ψJB
Junction-to-board characterization parameter
22.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
11 Electrical Characteristics
Tj = -40°C to 125°C, VIN = 12 V, typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
Input Voltage Range
IVIN
VIN Supply Current
VEN = 3.3V,Non Switching
4.5
IVINSDN
VIN Shutdown Current
VEN = 0V
18
V
108
µA
3
µA
VCC OUTPUT
VCC
VCC Output Voltage
IVCC
VCC Current Limit
VIN > 5.0V
4.75
4.83
VIN = 4.5, no Load
4.3
4.5
4.92
V
V
20
mA
FEEDBACK VOLTAGE
VFB
VFB Voltage
TJ = 25°C
594
600
606
mV
TJ = -40 to 125°C
591
600
609
mV
4.2
4.4
V
UVLO
Wake up VIN voltage
UVLO
VIN Under-Voltage Lockout
Shut down VIN voltage
3.6
Hysteresis VIN voltage
3.7
V
500
mV
LOGIC THRESHOLD
VEN(ON)
EN Threshold High-level
1.22
1.32
1.42
VEN(OFF)
EN Threshold Low-level
1.04
1.12
1.20
IEN
EN Pull Down Current
IMODE
MODE Sourcing Current
VEN = 0.8V
V
V
2
µA
5
µA
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Electrical Characteristics (continued)
Tj = -40°C to 125°C, VIN = 12 V, typical values are at Tj = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFET
RDS(ON)H
High Side MOSFET Rds(on)
25
mΩ
RDS(ON)L
Low Side MOSFET Rds(on)
12
mΩ
kHz
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching Frequency
600
TMIN_ON
Minimum On-time
50
TMIN_OFF
Minimum Off-time
ns
200
ns
OOA Function
TOOA
Mode Operation Period
32
µs
Soft Start Time
1
ms
SOFT START
TSS
POWER GOOD
TPGDLYLH
PG Low to High Delay
PG from low to high
160
µs
TPGDLYHL
PG High to Low Delay
PG from high to low
32
µs
VFB falling (fault)
85
%
VFB rising (good)
90
%
VFB rising (fault)
115
%
VPGTH
PG Threshold
VFB falling (good)
110
%
IPGSK
PG Sink Current
VPG = 0.5V
52
mA
IPGLK
PG Leak Current
VPG = 5.5V
1
µA
8.6
A
CURRENT LIMIT
IOCL
Over Current Threshold
INOCL
Negative Over Current Threshold
Valley current set point
6.6
7.6
3.4
A
VFB rising (fault)
125
%
VFB falling (good)
120
%
32
µs
VFB falling (fault)
60
%
VFB rising (good)
65
%
256
µs
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP Trip Threshold
tOVPDLY
OVP Prop Deglitch
VUVP
UVP Trip Threshold
tUVPDLY
UVP Prop Deglitch
THERMAL PROTECTION
TOTP
OTP Trip Threshold (1)
150
°C
TOTPHYS
OTP Hysteresis (1)
20
°C
(1)
6
Not production tested
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11.1 Typical Characteristics
140
5
130
4.5
Shutdown Current (PA)
Supply Current (PA)
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
120
110
100
90
4
3.5
3
2.5
80
-50
-20
10
40
70
Junction Temperature (qC)
100
2
-50
130
VEN = 5 V
100
130
D003
Figure 2. Shutdown Current vs Temperature
615
1.44
610
1.4
EN On Voltage (V)
VFB Feedbacvk Voltage (mV)
10
40
70
Junction Temperature (qC)
VEN = 0 V
Figure 1. Supply Current vs Junction Temperature
605
600
595
590
1.36
1.32
1.28
1.24
585
-50
-20
10
40
70
Junction Temperature (qC)
100
1.2
-50
130
1.2
35
High-side RDS(on) (m:)
40
1.15
1.1
1.05
1
10
40
70
Junction Temperature (qC)
100
130
D005
Figure 4. Enable On Voltage vs Junction Temperature
1.25
0.95
-50
-20
D004
Figure 3. Feedback Voltage vs Junction Temperature
EN Off Voltage (V)
-20
D002
30
25
20
15
-20
10
40
70
Junction Temperature (qC)
100
130
10
-50
D006
Figure 5. Enable Off Voltage vs Junction Temperature
-20
10
40
70
Junction Temperature (qC)
100
130
D007
Figure 6. High-Side RDS(on) vs Junction Temperature
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Typical Characteristics (continued)
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
130
18
128
OVP Threshold (%)
Low-side RDS(on) (m:)
16
14
12
10
126
124
122
8
6
-50
-20
10
40
70
Junction Temperature (qC)
100
120
-50
130
Figure 7. Low-Side RDS(on) vs Junction Temperature
8.2
61
8
60
59
58
10
40
70
Junction Temperature (qC)
100
130
D009
Figure 8. OVP Threshold vs Junction Temperature
62
Valley Current Limit (A)
UVP Threshold (%)
-20
D008
7.8
7.6
7.4
7.2
57
56
-50
-20
10
40
70
Junction Temperature (qC)
100
130
7
-50
-20
D010
Figure 9. UVP Threshold vs Junction Temperature
10
40
70
Junction Temperature (qC)
100
130
D011
Figure 10. Valley Current Limit vs Junction Temperature
1.15
Soft-start Time (ms)
1.1
1.05
1
0.95
0.9
0.85
-50
-20
10
40
70
Junction Temperature (qC)
100
130
D012
Figure 11. Soft-Start Time vs Junction Temperature
8
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Typical Characteristics (continued)
TJ=-40oC to 125oC, VIN=12V(unless otherwise noted)
100
100
90
80
70
80
Efficiency (%)
Efficiency (%)
90
70
60
50
40
30
20
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
50
40
0.001
60
0.01
0.1
I-Load (A)
1
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
10
0
0.001
10
0.01
D013
Figure 12. Efficiency, Eco-mode
600
Switching Frequency (kHz)
80
Efficiency (%)
70
60
50
40
30
20
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
10
0.01
0.1
I-Load (A)
1
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
500
400
300
200
0
0.001
10
0.01
D014
Figure 14. Efficiency, FCCM
0.1
I-Load (A)
1
10
D023
Figure 15. Switching Frequency vs Output Load, Eco-mode
800
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
Switching Frequency (kHz)
Switching Frequency (kHz)
D015
100
700
500
400
300
200
700
600
500
VIN=12V, VOUT=1.05V
VIN=12V, VOUT=3.3V
VIN=12V, VOUT=5V
100
0
0.001
10
Figure 13. Efficiency, OOA-mode
90
600
1
700
100
0
0.001
0.1
I-Load (A)
0.01
0.1
I-Load (A)
1
10
400
0.001
D017
Figure 16. Switching Frequency vs Output Load, OOA-mode
0.01
0.1
I-Load (A)
1
10
D018
Figure 17. Switching Frequency vs Output Load, FCCM
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12 Detailed Description
12.1 Overview
The TPS566235 is high density synchronous Buck converter which operates from 4.5 V to 18 V input voltage
(VIN), and the output range is from 0.6 V to 7 V. It has 25-mΩ and 12-mΩ integrated MOSFETs that enable high
efficiency up to 6 A. The proprietary D-CAP3™ mode enables low external component count, ease of design,
optimization of the power design for cost, size and efficiency. The TPS566235 has ultra-low quiescent current
(ULQ™) mode. This feature is beneficial for long battery life in system standby mode. The device employs DCAP3™ mode control that provides fast transient response with no external compensation components. The
control topology supports seamless transition between CCM mode at heavy load conditions and DCM operation
at light load conditions. There are three operation modes can be configured by MODE pin at light load: EcoMode™, OOA and FCCM. Eco-Mode™ allows the TPS566235 to maintain high efficiency at light load. OOA
mode makes switching frequency above audible frequency (25kHz), even there is no loading at output side.
FCCM mode has the constant switching frequency at both light and heavy load. TPS566235 are able to adapt to
both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
12.2 Functional Block Diagram
PG high
threshold
UV threshold
+
PG
+
UV
Delay
+
+
PG low
threshold
OV
OV threshold
VIN
+
0.6 V
LDO
4.2V /
3.7V
Internal SS
VCC
+
+
+
FB
Control Logic
PWM
BST
SS
VIN
+
Internal Ramp
x
x
x
x
x
x
Ripple injection
SW
On/Off time
Minimum On/Off
OVP/UVP/TSD
Eco-Mode/OOA/FCCM
Soft-Start
PGOOD
SW
XCON
One Shot
PGND
+
EN
+
OCL
EN Threshold
+
ZC
MODE
Eco-Mode/OOA/FCCM
+
NOCL
150°C /20°C
+
THOK
AGND
10
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12.3 Feature Description
12.3.1 PWM Operation and D-CAP3™ Control
The main control loop of the Buck is adaptive on-time pulse width modulation (PWM) controller that supports a
proprietary D-CAP3™ mode control. The D-CAP3™ mode control combines adaptive on-time control with an
internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The
TPS566235 also includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and it is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to reference voltage for emulating the output ripple, this enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3™ control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the TPS566235 is a low-pass L-C circuit. This L-C filter has a double-pole frequency
described in Equation 1.
fp
1
2 u S u LOUT u COUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS566235. The low-frequency L-C double pole has a 180 degree drop in phase. At the output filter
frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is related to the
switching frequency. The crossover frequency of the overall system should usually be targeted to be less than
one-third of the switching frequency (FSW).
12.3.2 Power Good
The Power Good (PG) pin is an open drain output. Once the FB pin voltage is between 90% and 110% of the
internal reference voltage (VREF=0.6V), the PG is de-asserted and floats after a 160 µs de-glitch time. A pull-up
resistor of 100 kΩ is recommended to pull it up to VCC. The PG pin is pulled low when the FB pin voltage is
lower than 85% or greater than 115% threshold or in an event of thermal shutdown or during the soft-start period.
PG de-glitch time (from high to low) is 32 µs.
12.3.3 Soft Start and Pre-Biased Soft Start
The TPS566235 has an internal 1.0 ms soft-start time. Soft start can prevent the overshoot of output voltage
during start up. When the EN pin becomes high, internal soft-start function begins ramping up the reference
voltage to the PWM comparator.
The TPS566235 can prevent current from being pulled from the output during startup if the output is pre-biased.
The device disables the switching of both the high-side and low-side FETs until the soft-start commands a
voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage VFB). Then, the
controller start the first high side FET gate driver pulses. This scheme prevents the initial sinking of the pre-bias
output, and ensure that the output voltage starts and ramps up into regulation and the control loop is given time
to transition from pre-biased start-up to normal mode operation.
12.3.4 Over current Protection and Undervoltage Protection
The TPS566235 has the over current protection and undervoltage protection. The output over current limit (OCL)
is implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state
by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
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Feature Description (continued)
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over current protection. When the load current is higher
than the over current threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited, the output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it, the device will shut off after a wait time of 256 µs and then re-start after the hiccup time (typically
7xTss). When the over current condition is removed, the output will be recovered.
12.3.5 Over Voltage Protection
TPS566235 has the over voltage protection function by monitoring the feedback voltage (VFB). When the
feedback voltage becomes higher than 125% of VREF, the OVP comparator output goes high and turns off both
high-side and low-side MOSFETs after a wait time of 32 µs. This protection is a non-latching operation. The
device re-starts switching when the feedback voltage falls below 120% of VREF.
12.3.6 UVLO Protection
The undervoltage lockout (UVLO) protection monitors the VCC pin voltage to protect the internal circuitry from
low input voltages. When the voltage is lower than UVLO threshold voltage, the under-voltage lockout circuit
prevents mis-operation of the device by turning off both high-side and low-side MOSFETs. The converter begins
operation again when the input voltage exceeds the threshold by a hysteresis of 500 mV (typical).This is a nonlatch protection.
12.3.7 Thermal Shutdown
The device monitors the internal die temperature. If it exceeds the thermal shutdown threshold value (typically
150°C), the device shuts off. This is a non-latch protection.
12.4 Device Functional Modes
12.4.1 Light Load Operation
TPS566235 has a MODE pin which can setup three different modes of operation for light load running. The light
load operation mode includes Eco-Mode™, Out-Of-Audio™ mode and FCCM mode.
12.4.2 MODE Pin Configuration
TPS566235 detect the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in Table 1. TPS566235 internally has a comparator to compare this voltage with reference voltage and
decide which mode to choose. The voltage on the MODE pin can be set by connecting to VCC pin or connecting
a resistor RM between this pin and AGND. There is a source current of 5 µA at the mode pin and generate
voltage for mode selection to avoid noise and spurious trigger. The VMODE voltage range and recommended
resistor value is shown in Table 1. The MODE pin setting can be reset only by VIN power cycling or EN toggle.
Table 1. Mode Pin Settings
VMODE
12
0-0.3 V
0.3 V-1.2 V
>1.2 V
Recommended Resistor
0Ω
100 kΩ-150 kΩ
To VCC (recommend) or
RM>400kΩ
Operating Mode
Eco-Mode™
OOA
FCCM
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Figure 18 shows the typical start-up sequence of the device once the enable signal crosses the EN turn on
threshold (VIN is higher then UVLO threshold). After the voltage on VCC crosses the rising UVLO threshold, it
takes about 60 µs to read the mode setting .The output voltage starts ramping after 10 µs from the mode reading
is done.
EN
EN threshold
VCC UVLO
VCC
MODE3
MODE2
MODE1
MODE
VOUT
PGOOD
60…s
60…s
10…s
Tss
500…s
Figure 18. Start-Up Sequence
12.4.3 Advanced Eco-Mode™ Control
The advanced Eco-Mode™ control scheme to maintain high efficiency at light loads. As the output current
decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point
where the rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction modes. The low-side MOSFET is turned off when a zero inductor current is detected.
As the load current further decreases, the converter runs into discontinuous conduction mode. The on-time is
kept almost the same as it is in continuous conduction mode so that it takes more time to discharge the output to
the level of reference voltage with a smaller load current. The light load current where the transition to EcoMode™ operation happens ( IOUT(LL) ) can be calculated from Equation 2.
(V -V
) × VOUT
1
IOUT(LL) =
× IN OUT
2 × LOUT × FSW
VIN
(2)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application).
12.4.4 Out-Of-Audio™ Mode
Out-Of-Audio™ (OOA) light-load mode is a unique control feature that keeps the switching frequency above
audible frequency with minimum reduction in efficiency. It prevents audio noise generation from the output
capacitors and inductor. During Out-of-Audio operation, the OOA control circuit monitors the states of both highside and low-side MOSFETs and forces them switching if both MOSFETs are off for more than 32 μs. When both
high-side and low-side MOSFETs are off for more than 32 μs during a light-load condition, the low side FET will
discharge until reverse OC happens or output voltage drops to trigger the high-side FET on.
If the MODE pin is selected to operate in OOA mode, when the device works at light load, the minimum
switching frequency is above 25 kHz which avoids the audible noise in the system.
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12.4.5 Force CCM Mode
Force CCM (FCCM) mode keeps the converter to operate in continuous conduction mode during light-load
conditions and allows the inductor current to become negative. During FCCM mode, the switching frequency
(FSW) is maintained at an almost constant level over the entire load range, which is suitable for applications
requiring tight control of the switching frequency and output voltage ripple at the cost of lower efficiency under
light load.
12.4.6
Standby Operation
The TPS566235 can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 3 µA when in standby condition. EN pin is pulled low internally when it is floating and the device is
disabled by default.
14
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13 Application and Implementation
NOTE
Information in the following application sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
13.1 Application Information
The schematic of Figure 19 shows a typical application for TPS566235. This design converts an input voltage
range of 4.5 V to 18 V down to 1.05 V with a maximum output current of 6 A.
13.2 Typical Application
Figure 19. Application Schematic
13.2.1 Design Requirements
Table 2. Design Parameters
PARAMETER
VOUT
Output voltage
IOUT
Output current
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
FSW
Switching frequency
CONDITIONS
MIN
TYP
IOUT: 10%-90%, 2.5A/µs
UNIT
V
6
A
±5% x VOUT
4.5
12
18
V
2% x VOUT
600
Light load operation mode
TA
MAX
1.05
kHz
Eco-Mode™
Ambient temperature
25
°C
13.2.2 Detailed Design Procedure
13.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS566235 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
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•
•
•
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Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.2.2.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 3 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 3 and Equation 4. It is
important that the inductor is rated to handle these currents.
2ö
æ
1 æ VOUT × (VIN(max) - VOUT )ö ÷
ç
2
÷
IL(rms)= ç I OUT + × ç
12 ç VIN(max) × LOUT × FSW ÷ ÷÷
ç
è
ø
è
ø
IOUT(ripple)
IL(peak) = IOUT +
2
(3)
(4)
During transient/short circuit conditions the inductor current can increase up to the current limit of the device so it
is safe to choose an inductor with a saturation current higher than the peak current under current limit condition.
13.2.2.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In D-CAP3™, the regulator reacts within
one cycle to the change in the duty cycle so the good transient performance can be achieved without needing
large amounts of output capacitance. The recommended output capacitance range is given in Table 3
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple)
Table 3. Recommended Component Values
LOUT (µH)
COUT (µF)
CFF (pF)
VOUT (V)
RLOWER
(kΩ)
RUPPER
(kΩ)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1
20
13.3
0.68
1
4.7
44
110
-
-
1.05
20
15
0.68
1
4.7
44
110
-
-
1.2
20
20
1
1.2
4.7
44
110
-
-
1.5
20
30
1
1.2
4.7
44
110
-
-
1.8
20
40
1.2
1.5
4.7
44
110
-
-
2.5
20
63.3
1.5
2.2
4.7
44
110
-
-
3.3
20
90
1.5
2.2
4.7
44
110
10
220
5
20
146.6
1.5
2.2
4.7
44
110
10
220
13.2.2.4 Input Capacitor Selection
The minimum input capacitance required is given in Equation 5.
IOUT ×VOUT
CIN(min) =
VINripple ×VIN ×FSW
(5)
TI recommends using a high quality X5R or X7R input decoupling capacitors of 44 µF on the input voltage pin.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by Equation 6 below:
ICIN(rms) = IOUT ×
16
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
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13.2.3 Application Curves
Figure 20 through Figure 35 applies to the circuit of Figure 19. VIN = 12 V, TJ = 25°C (unless otherwise specified)
1
90
0.8
80
0.6
Load Regulation (%)
100
Efficiency (%)
70
60
50
40
30
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
20
10
0
0.001
0.01
0.1
I-Load (A)
1
0.4
0.2
0
-0.2
-0.4
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
-0.6
-0.8
-1
0.001
10
0.01
D001
1
10
D019
Figure 21. Load Regulation
800
700
700
600
Switching Frequency (kHz)
Swtiching Frequency (kHz)
Figure 20. Efficiency Curve
0.1
I-Load (A)
600
500
400
300
VIN=5V, VOUT=1.05V
VIN=8.4V, VOUT=1.05V
VIN=12V, VOUT=1.05V
VIN=18V, VOUT=1.05V
500
400
300
200
100
200
4
6
8
10
12
VIN (V)
14
16
0
0.001
18
0.01
D022
0.1
I-Load (A)
1
10
D016
IOUT = 6 A
Figure 23. Switching Frequency vs Output Load
1
1
0.8
0.8
0.6
0.6
Line Regulation (%)
Line Regulation (%)
Figure 22. Switching Frequency vs Input Voltage
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
4
6
8
10
12
VIN (V)
14
16
18
4
D020
Figure 24. Line Regulation, IOUT = 0.1 A
6
8
10
12
VIN (V)
14
16
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D021
Figure 25. Line Regulation, IOUT = 6 A
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EN=5V/div
EN=5V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
400…s/div
2ms/div
Figure 26. Start-Up Through EN, IOUT = 3 A
Figure 27. Shut-down Through EN, IOUT = 3 A
Vin=10V/div
Vin=10V/div
Vout=1V/div
Vout=1V/div
IL=5A/div
IL=5A/div
400…s/div
4ms/div
Figure 28. Start Up Relative to VIN Rising, IOUT = 3 A
Figure 29. Start Up Relative to VIN Falling, IOUT = 3 A
Vout=50mV/div (AC coupled)
Vout=20mV/div (AC coupled)
SW=10V/div
SW=10V/div
2…s/div
100…s/div
Figure 30. Output Voltage Ripple, IOUT = 0.01 A
18
Figure 31. Output Voltage Ripple, IOUT = 6 A
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Vout=100mV/div (AC coupled)
Vout=100mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200…s/div
200…s/div
Slew Rate=2.5A/µs
Slew Rate=2.5A/µs
Figure 32. Transient Response, 0.6 A to 5.4 A
Figure 33. Transient Response, 0 A to 6 A
Vout=1V/div
Vout=1V/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
4ms/div
80…s/div
Figure 34. Normal Operation to Output Hard Short
Figure 35. Output Hard Short Hiccup
14 Power Supply Recommendations
The TPS566235 is intended to be powered by a well regulated dc voltage. The input voltage range is 4.5 V to 18
V. TPS566235 is Buck converter, the input supply voltage must be bigger than the desired output voltage for
proper operation. Input supply current must be appropriate for the desired output current. If the input voltage
supply is located far from the TPS566235 circuit, some additional input bulk capacitance is recommended.
Typical values are 100 µF to 470 µF.
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15 Layout
15.1 Layout Guidelines
When laying out the printed circuit board, the following guideline should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the layout diagram of Figure 36
• Recommend a four-layer PCB for good thermal performance and with maximum ground plane. 3" x 3", fourlayer PCB with 2-oz. copper used as example.
• Place the decoupling capacitors right across VIN as close as possible.
• Place output inductors and capacitors with IC at the same layer, SW routing should be as short as possible to
minimize EMI, and should be a wide plane to carry big current, enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible.
• Place BST resistor and capacitor with IC at the same layer, close to BST and SW plane, >15 mil width trace
is recommended to reduce line parasitic inductance.
• FB could be wide and must be routed away from the switching node, BST node or other high efficiency
signal.
• VIN trace must be wide to reduce the trace impedance and provide enough current capability.
• Place multiple vias near GND and near input capacitors to reduce parasitic inductance and improve thermal
performance.
15.2 Layout Example
R
Trace on internal or
bottom layer
R
R
4
VIN
VCC
AGND
FB
PG
VIN
3
C
R
BST
C
SW
C
C
Mode setting
PGND
MODE
L
3
4
400kb
100kb
0b
PGND
EN
PGND
PGND
Additional Vias to
the GND plane
PSM OOA FCCM
Additional Vias to
the GND plane
To Enable
Control
GND
GND
C
VOUT
Figure 36. PCB Layout Recommendation Diagram
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16 Device and Documentation Support
16.1 Device Support
16.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
16.1.2 Development Support
16.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS566235 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
16.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
16.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
16.4 Trademarks
D-CAP3, Eco-Mode, Out-Of-Audio, HotRod, Advanced Eco-Mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
16.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
16.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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17 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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14-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS566235RJNR
ACTIVE
VQFN-HR
RJN
13
3000
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
566235
TPS566235RJNT
ACTIVE
VQFN-HR
RJN
13
250
RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
-40 to 125
566235
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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