TPS566231, TPS566238
TPS566231,
TPS566238
SLUSDQ7A – MAY 2020
– REVISED JANUARY
2021
SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
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TPS56623x 3-V to 18-V Input, 6-A Synchronous Step-Down Voltage Regulator
1 Features
3 Description
•
The TPS56623x are simple, easy to use, highefficiency, 6-A synchronous buck converters in a QFN
9-pin 1.5-mm x 2.0-mm package.
•
•
Configured for rugged applications
– Input voltage range: 3 V to 18 V
– Output voltage range: 0.6 V to 7 V
– 6-A continuous output current
– 0.6-V ±1% reference voltage (25°C)
– 98% maximum duty cycle
– 600-kHz switching frequency
– Non-latched for OC, OV, UV, and OT
protections
– Built-in output discharge function
Numerous pin-compatible options
– TPS566231 and TPS566238 with SS pin for
adjustable soft-start time
– TPS566231P and TPS566238P with PG pin for
power good indicator
– TPS566231 and TPS566231P for auto-skip
mode
– TPS566238 and TPS566238P for continuous
current mode
Small solution size and ease of use
– Integrated power MOSFET with RDS(on) 20.8
mΩ and 10.6 mΩ
– D-CAP3™ architecture control for fast transient
response and internal compensation
– 1.5-mm × 2.0-mm HotRod™ QFN package
– Create a custom design with the WEBENCH®
Power Designer
The devices operate with wider supply input voltage
ranging from 3 V to 18 V. The D-CAP3™ control mode
was adopted to provide a fast transient response,
good line and load regulation, no requirement for
external compensation, and to support low-ESR
output capacitors.
The TPS566231 and TPS566231P operate in EcoMode™ for high efficiency during light load operation,
and are designed with ULQ™ (Ultra Low Quiescent)
feature, achieving 50-uA quiescent current to enable
long battery life in low-power applications. The
TPS566238 and TPS566238P operate in continuous
current mode, which maintains lower output ripple
during all load conditions.
The TPS566231 and TPS566238 soft-start time can
be adjusted through the SS pin. The TPS566231P
and TPS566238P indicate power good through the
PG pin.
The TPS56623x can support up to 98% duty cycle
operation, and integrate complete protection through
OVP, OCP, UVLO, OTP, and UVP with hiccup. They
are each available in a 9-pin 1.5-mm x 2.0-mm
HotRod™ package and the junction temperature is
specified from -40°C to 125°C.
Device Information
2 Applications
•
•
•
Digital TV, set-top box, gaming consoles
Server, storage and networking point-of-load
Industrial PC, IP camera, and factory automation
applications
VIN
TPS566231/8
TPS566231P/8P SW
BODY SIZE (NOM)
TPS566231
TPS566238
VQFN (9)
TPS566231P
1.50 mm × 2.00 mm
TPS566238P
(1)
VIN
PACKAGE(1)
PART NUMBER
For all available packages, see the orderable addendum at
the end of the data sheet.
100
L
VOUT
95
90
CBST
COUT
R1
BST
EN
FB
R2
VCC
SS/PG
Efficiency (%)
CIN
85
80
75
70
65
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
60
C1
PGND
55
0.001
Typical Application
0.01
0.1
I-Load (A)
1
10
12VI
TPS566231 Efficiency Versus Output Current
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................14
8 Application and Implementation.................................. 15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................23
11.1 Receiving Notification of Documentation Updates.. 23
11.2 Support Resources................................................. 23
11.3 Trademarks............................................................. 23
11.4 Electrostatic Discharge Caution.............................. 23
11.5 Glossary.................................................................. 23
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (May 2020) to Revision A (January 2021)
Page
• Changed device status from Advance Information to Production Data.............................................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
2
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
5 Pin Configuration and Functions
BST
VIN
VIN
BST
VIN
VIN
7
6
5
7
6
5
8
SW
SS
8
SW
9
PGND
4
1
2
3
VCC
FB
EN
Figure 5-1. TPS566231/TPS566238 Package (Top
View)
PG
9
PGND
4
1
2
3
VCC
FB
EN
Figure 5-2. TPS566231P/TPS566238P Package (Top
View)
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VCC
1
O
5.0-V internal VCC LDO output. This pin supplies voltage to the internal circuitry and gate driver. Bypass
this pin with a 1-μF capacitor. If VVIN is lower than 5 V, VCC will follow the VIN voltage.
FB
2
I
Converter feedback input. Connect to the center tap of the resistor divider between output voltage and
ground.
EN
3
I
Enable pin of buck converter. The EN pin is a digital input pin, so it decides to turn on or turn off the buck
converter. If the EN pin is open, the internal pullup current occurs to enable converter.
PGND
4
G
Ground pin. Power ground return for the switching circuit. Connect sensitive SS and FB returns to PGND at
a single point.
VIN
5, 6
P
Input voltage supply pin. Connect the input decoupling capacitors between VIN and PGND.
BST
7
O
Supply input for the gate drive voltage of the high-side MOSFET. Connect the bootstrap capacitor between
BST and SW. 0.1 μF is recommended.
SW
8
O
Switch node terminal. Connect the output inductor to this pin.
O
TPS566231 and TPS566238 soft-start control pin. Connecting an external capacitor sets the soft-start time.
O
TPS566231P and TPS566238P open-drain power good indicator. It is asserted low if output voltage is out
of PG threshold, over voltage, or if the device is under thermal shutdown, EN shutdown, or during soft start.
SS/PG
9
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Input voltage
MIN
MAX
VIN
–0.3
20
V
BST
–0.3
26
V
BST (10-ns transient)
-0.3
28
V
BST-SW
–0.3
7
V
VIN-SW
VIN-SW (10-ns transient)
22
V
25.5
V
SS, FB, EN, PG
–0.3
6
V
PGND
–0.3
0.3
V
SW
Output voltage
UNIT
–2
20
V
SW (10-ns transient)
–5.5
22
V
VCC
–0.3
6
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input voltage
Output voltage
4
MAX
UNIT
VIN
3
18
V
BST
–0.1
23.5
V
BST-SW
–0.1
5.5
V
SS, FB, EN, PG
–0.1
5.5
V
PGND
–0.1
0.1
V
–1
18
V
–0.1
5.5
V
0
6
A
–40
125
°C
SW
VCC
IOUT
Output current
TJ
Operating junction temperature
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
6.4 Thermal Information
TPS56623x
THERMAL
METRIC(1)
RQF (VQFN)
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance
RθJA_effective
Junction-to-ambient thermal resistance with TI EVM
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ΨJT
ΨJB
RθJC(bot)
(1)
89.6
°C/W
44
°C/W
72.2
°C/W
25
°C/W
Junction-to-top characterization parameter
2.2
°C/W
Junction-to-board characterization parameter
24.8
°C/W
Junction-to-case (bottom) thermal resistance
NA
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY VOLTAGE
VIN
IVIN
IINSDN
Input voltage range
VIN
VIN Supply Current
VIN Shutdown Current
3
18
V
No load, VEN = 5 V, non-switching
(TPS566231/TPS566231P)
25
50
75
µA
No load, VEN = 5 V, non-switching
(TPS566238/TPS566238P)
275
375
475
µA
3.2
5
µA
No load, VEN = 0 V
UVLO
VUVLOVIN
VIN UVLO threshold
Wake up VIN voltage
2.62
2.74
2.86
V
Shut down VIN voltage
2.44
2.54
2.64
V
Hysteresis VIN voltage
200
mV
VCC OUTPUT
VCC
VCC Output Voltage
ICC
VCC Current Limit
VIN = 12 V
4.7
VIN = 3 V
5
5.2
3
V
V
VIN = 12 V
20
mA
VIN = 3 V
5
mA
FEEDBACK VOLTAGE
VFB
FB voltage
TJ = 25°C
594
600
606
mV
TJ = -40°C to 125°C
591
600
609
mV
MOSFET
RDS (ON)HI
High-side MOSFET Rds(on)
RDS (ON)LO
Low-side MOSFET Rds(on)
IOCL
Over Current threshold
INOCL
Negative Over Current threshold
TJ = 25°C, VIN ≥ 5 V
20.8
mΩ
TJ = 25°C, VIN = 3 V
25.8
mΩ
TJ = 25°C, VIN ≥ 5 V
10.6
mΩ
TJ = 25°C, VIN = 3 V
13
Valley current set point
mΩ
6.1
7.4
8.9
A
2
3.4
5.3
A
DUTY CYCLE and FREQUENCY CONTROL
FSW
Switching Frequency
TJ = 25°C, VVOUT = 1.0 V
TON(MIN)
Minimum On-time(1)
TJ = 25°C
TOFF(MIN)
Minimum
Off-time(1)
VFB = 0.5 V
600
50
100
kHz
90
ns
ns
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD
VEN(ON)
EN Threshold High-level
1.13
1.19
1.25
V
VEN(OFF)
EN Threshold Low-level
1.01
1.08
1.16
V
VENHYS
EN Hysteresis
IEN
EN Pull up Current
VEN = 1.0 V
110
mV
2
uA
OUTPUT DISCHARGE and SOFT START
RDIS
Discharge resistance
TJ = 25°C, VVOUT = 0.5 V, VEN = 0 V
ISS
Soft-start Charge Current
TPS566231/TPS566238
TSS
Internal Soft-start Time
TPS566231P/TPS566238P
114
Ω
5
6.5
8.5
uA
0.93
1.9
2.9
ms
POWER GOOD (TPS566231P/TPS566238P)
TPGDLY
VPGTH
PG Start-up Delay
PG Threshold
PG from low-to-high
1
ms
PG from high-to-low
32
us
VFB falling (fault)
80
85
90
%
VFB rising (good)
85
90
95
%
VFB rising (fault)
110
115
120
%
VFB falling (good)
105
110
115
%
VPG_L
PG Sink Current Capability
IOL = 4 mA
IPGLK
PG Leak Current
VPGOOD = 5.5 V
0.4
V
1
uA
120
%
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
OVP Trip Threshold
tOVPDLY
OVP Prop deglitch
VUVP
UVP Trip Threshold
110
115
55
60
TJ = 25°C
tUVPDLY
UVP Prop deglitch
tUVPDEL
Output Hiccup delay relative to SS time
UVP detect
tUVPEN
Output Hiccup enable delay relative to
SS time
UVP detect (TPS566231/TPS566238)
tUVPEN
Output Hiccup enable delay relative to
SS time
UVP detect (TPS566231P/
TPS566238P)
32
us
65
%
256
us
256
us
7
cycles
19
ms
OTP Trip Threshold(1)
160
°C
Hysteresis(1)
25
°C
THERMAL PROTECTION
TOTP
TOTPHSY
(1)
6
OTP
No production test, specified by design.
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SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
6.6 Typical Characteristics
60
415
55
400
Supply Current (uA)
Supply Current (uA)
TJ = -40°C to 125°C, VIN = 12 V (unless otherwise noted)
50
45
-20
10
40
70
Junction Temperature(OC)
VEN = 5 V
100
340
-50
130
VEN = 5 V
TPS566231
10
40
70
Junction Temperature(OC)
100
130
D002
TPS566238
Figure 6-2. Supply Current vs Junction
Temperature
4.5
VFB Feedback Voltage (mV)
615
4
Supply Current (uA)
-20
D001
Figure 6-1. Supply Current vs Junction
Temperature
3.5
3
2.5
2
-50
370
355
40
35
-50
385
-20
10
40
70
Junction Temperature(OC)
100
610
605
600
595
590
-50
130
-20
D002
10
40
70
Junction Temperature(OC)
100
130
D003
VEN = 0 V
Figure 6-4. Feedback Voltage vs Junction
Temperature
1.22
1.12
1.21
1.11
EN Off Voltage (V)
EN On Voltage (V)
Figure 6-3. Shutdown Current vs Temperature
1.2
1.19
1.18
1.17
-50
1.1
1.09
1.08
-20
10
40
70
Junction Temperature(OC)
100
130
1.07
-50
-20
D004
Figure 6-5. Enable On Voltage vs Junction
Temperature
10
40
70
Junction Temperature(OC)
100
130
D005
Figure 6-6. Enable Off Voltage vs Junction
Temperature
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30
16
27
14
Low-Side RDS(on) (m:)
High-Side RDS(on) (m:)
SLUSDQ7A – MAY 2020 – REVISED JANUARY 2021
24
21
18
15
-50
12
10
8
-20
10
40
70
Junction Temperature(OC)
100
6
-50
130
-20
D006
VIN = 12 V
20
32
18
Low-Side RDS(on) (m:)
High-Side RDS(on) (m:)
35
29
D007
26
16
14
12
-20
10
40
70
Junction Temperature(OC)
100
10
-50
130
-20
D006
VIN = 3 V
10
40
70
Junction Temperature(OC)
100
130
D007
VIN = 3 V
Figure 6-9. High-Side RDS(on) vs Junction
Temperature
Figure 6-10. Low-Side RDS(on) vs Junction
Temperature
120
65
118
63
UVP Threshold (%)
OVP Threshold (%)
130
Figure 6-8. Low-Side RDS(on) vs Junction
Temperature
23
116
114
112
110
-50
61
59
57
-20
10
40
70
Junction Temperature(OC)
100
Figure 6-11. OVP Threshold vs Junction
Temperature
8
100
VIN = 12 V
Figure 6-7. High-Side RDS(on) vs Junction
Temperature
20
-50
10
40
70
Junction Temperature(OC)
130
55
-50
-20
D009
10
40
70
Junction Temperature(OC)
100
130
D010
Figure 6-12. UVP Threshold vs Junction
Temperature
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170
8
150
7.8
Valley Current Limit (A)
Discharge Resistor (:)
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130
110
90
7.4
7.2
70
-50
-20
10
40
70
Junction Temperature(OC)
100
7
-50
130
10
40
70
Junction Temperature(OC)
2.5
6.6
2.3
Soft-Start Time (ms)
7
6.2
5.8
100
130
D011
Figure 6-14. Valley Current Limit vs Junction
Temperature
5.4
2.1
1.9
1.7
5
-50
-20
10
40
70
Junction Temperature(OC)
100
1.5
-50
130
-20
10
40
70
Junction Temperature(OC)
D012
TPS566231 and TPS566238
100
130
D013
TPS566231P and TPS566238P
Figure 6-15. Soft-Start Charge Current Iss vs
Junction Temperature
Figure 6-16. Soft-Start Time vs Junction
Temperature
115
100
110
90
105
80
70
100
Efficiency (%)
Ambient Temperature (OC)
-20
D008
Figure 6-13. Discharge Resistor vs Junction
Temperature
Soft-Start ISS (uA)
7.6
95
90
85
60
50
40
30
Nat Conv
100 LFM
200 LFM
400 LFM
80
75
20
70
0
1
VIN = 12 V
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
10
2
3
4
Output Current (A)
5
6
7
0
0.001
0.01
SOA_
1
10
D100
VIN = 12 V
VOUT = 1.0 V
Figure 6-17. Safe Operating Area
0.1
I-Load (A)
Figure 6-18. TPS566238 and TPS566238P
Efficiency
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700
Switching Frequency (kHz)
Switching Frequency (kHz)
600
800
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
500
400
300
200
700
600
500
VVIN=12V, VOUT=1V
VVIN=12V, VOUT=3.3V
VVIN=12V, VOUT=5V
100
0
0.001
0.01
0.1
I-Load (A)
1
10
400
0.001
0.01
12VI
0.1
I-Load (A)
1
10
D102
Figure 6-19. TPS566231 and TPS566231P FSW Load Figure 6-20. TPS566238 and TPS566238P FSW Load
Regulation
Regulation
10
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7 Detailed Description
7.1 Overview
The TPS56623x is an 6-A integrated FET synchronous buck converter that operates from 3-V to 18-V input
voltage (VIN) and 0.6-V to 7-V output voltage. The proprietary D-CAP3™ mode enables low external component
count, ease of design, and optimization of the power design for cost, size, and efficiency. The key feature of the
TPS566231 and TPS566231P is ultra-low quiescent current (ULQ™) mode. This feature enables long battery life
in system standby mode and high efficiency under light load conditions. The devices employ D-CAP3 mode
control that provides fast transient response with no external compensation components and an accurate
feedback voltage. The control topology provides a seamless transition between CCM operating mode in heavier
load conditions and DCM operation in lighter load conditions.
This Eco-mode™ allows the TPS566231 and TPS566231P to maintain high efficiency at light load. The
TPS566238 and TPS566238P work in continuous current mode to maintain lower output ripple in all load
conditions. The soft-start time of the TPS566231 and TPS566238 can be adjusted through the SS pin. The
TPS566231P and TPS566238P indicate power good through the PG pin. The devices are able to adapt to both
low equivalent series resistance (ESR) output capacitors such as POS-CAP or SP-CAP, and ultra-low ESR
ceramic capacitors.
7.2 Functional Block Diagram
PG high
threshold
UV threshold
PG
+
Delay
+
UV
+
PG low
threshold
+
OV
VIN
OV threshold
FB
+
0.6 V
+
VREGOK
LDO
VCC
2.74 V /
2.54 V
+
+PWM
+
PG
SS/PG
Control Logic
BST
SS
VIN
Internal Ramp
Internal SS
Ripple injection
SW
x
x
x
x
x
x
x
On/Off time
Minimum On/Off
Light load Operation
OVP/UVP/OCP/TSD
Soft-Start
Large Duty Operation
Power Good
SW
XCON
PGND
One Shot
+
OCL
EN
+
+
EN Threshold
+
ZC
+
THOK
160°C /25°C
NOCL
Discharge control
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3 Control
The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports
a proprietary D-CAP3 mode control. D-CAP3 mode control combines adaptive on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both lowESR and ceramic output capacitors. It is stable even with virtually no ripple at the output. The TPS56623x also
includes an error amplifier that makes the output voltage very accurate.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the converter input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage
range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is
turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit
is added to the reference voltage for emulating the output ripple. This enables the use of very low-ESR output
capacitors such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation
is required for D-CAP3 control topology.
For any control topology that is compensated internally, there is a range of the output filter it can support. The
output filter used with the devices is a low-pass L-C circuit. This L-C filter has a double-pole frequency described
in Equation 1.
fp
1
2 u S u LOUT u COUT
(1)
At low frequency, the overall loop gain is set by the output set-point resistor divider network and the internal gain
of the TPS56623x. The low-frequency L-C double pole has a 180 degree drop in-phase. At the output filter
frequency, the gain rolls off at a –40-dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain rolloff from –40-dB to –20-dB per
decade and leads the 90 degree phase boost. The internal ripple injection high-frequency zero is about 45 kHz.
The inductor and capacitor selected for the output filter is recommended such that the double pole is located
close to 1/3 the high-frequency zero so that the phase boost provided by this high-frequency zero provides
adequate phase margin for the stability requirement. The crossover frequency of the overall system should
usually be targeted to be less than one-third of the switching frequency (FSW).
7.3.2 Soft Start
The TPS566231 and TPS566238 have an external SS pin is provided for setting soft-start time. When the EN
pin becomes high, the soft start function begins ramping up the reference voltage to the PWM comparator.
If the application needs a longer soft start time than 0.5 ms, it can be set by connecting a capacitor on the SS
pin. When the EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor
(CSS) connected between SS and ground. The devices tracks the lower of the internal soft-start voltage or the
external soft-start voltage as the reference. The estimated equation for the soft-start time (TSS) is shown in
Equation 2:
6OO (IO) =
1.4 × %OO (J() × 84'( (8)
+OO :Q#;
(2)
where
•
•
12
VREF is 0.6 V
ISS is 6.5 μA
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7.3.3 Power Good
The TPS566231P and TPS566238P have the PG pin as a power good indicator. The PG pin is an open-drain
output. Once the VFB is between 90% and 110% of the internal reference voltage (VREF), the PG is de-asserted
and floats after a 1-ms de-glitch time. A 100-kΩ pullup resistor is recommended to pull the voltage up to VCC.
The PG pin is pulled low when:
•
•
•
the FB pin voltage is lower than 85% or greater than 115% of the target output voltage,
the device an OVP, UVP, or thermal shutdown event,
or during the soft-start period.
7.3.4 Large Duty Operation
The TPS56623x can support large duty operations by smoothly dropping down the switching frequency. When
VIN / VOUT < 1.6 and the VFB is lower than internal VREF, the switching frequency is allowed to smoothly drop to
make TON extended to implement the large duty operation and also improve the performance of the load
transient performance. The minimum switching frequency is limited with about 165 kHz with typical minimum offtime of 100 ns. The TPS56623x can support up to 98% duty cycle operation.
7.3.5 Overcurrent Protection and Undervoltage Protection
The TPS56623x has overcurrent protection and undervoltage protection. The output overcurrent limit (OCL) is
implemented using a cycle-by-cycle valley detect circuit. The switch current is monitored during the OFF state by
measuring the low-side FET drain-to-source voltage. This voltage is proportional to the switch current. To
improve accuracy, the voltage sensing is temperature compensated.
During the on-time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time, and the output inductor value. During the on-time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is
above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even
the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent
switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner.
There are some important considerations for this type of overcurrent protection. When the load current is higher
than the overcurrent threshold by one half of the peak-to-peak inductor ripple current, the OCL is triggered and
the current is being limited. The output voltage tends to drop because the load demand is higher than what the
converter can support. When the output voltage falls below 60% of the target voltage, the UVP comparator
detects it and the device will shut off after a wait time of 256 μs and then restart after the hiccup time (typically 7
× Tss). When the overcurrent condition is removed, the output will be recovered.
7.3.6 Overvoltage Protection
The TPS56623x has the overvoltage protection feature. When the output voltage becomes higher than 115% of
the target voltage, the OVP is triggered. The output will be discharged after a wait time of 32 µs, and both the
high-side MOSFET driver and the low-side MOSFET driver turnoff. When the overvoltage condition is removed,
the output voltage will be recovered.
7.3.7 UVLO Protection
Undervoltage lockout protection (UVLO) monitors the VIN power input. When the voltage is lower than UVLO
threshold voltage, the device is shut off and output is discharged. This is a non-latch protection.
7.3.8 Output Voltage Discharge
The TPS56623x has the discharge function by using internal MOSFET of about 114-Ω RDS(on), which discharges
the output VOUT through the SW node during any event like output overvoltage protection, output undervoltage
protection, TSD, if VCC voltage below the UVLO, and when the EN pin voltage (VEN) is below the turnon
threshold. The discharge is slow due to the lower current capability of the MOSFET.
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7.3.9 Thermal Shutdown
The TPS56623x monitors the internal die temperature. If the temperature exceeds the threshold value (typically
160°C), the device is shut off and the output will be discharged. This is a non-latched protection, the device
restarts switching when the temperature goes below the thermal shutdown threshold.
7.4 Device Functional Modes
7.4.1 Advanced Eco-mode Control
The TPS566231 and TPS566231P operate in advanced Eco-mode mode, which maintains high light load
efficiency. As the output current decreases from heavy load conditions, the inductor current is also reduced and
eventually comes to a point where the rippled valley touches zero level, which is the boundary between
continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when the zero
inductor current is detected. As the load current further decreases, the converter runs into discontinuous
conduction mode. The on-time is kept almost the same as it was in continuous conduction mode so that it takes
longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. This
makes the switching frequency lower, proportional to the load current, and keeps the light load efficiency high.
The light load current where the transition to Eco-mode operation happens (IOUT(LL)) can be calculated from
Equation 3.
IOUT(LL) =
(V -V
) × VOUT
1
× IN OUT
2 × LOUT × FSW
VIN
(3)
After identifying the application requirements, design the output inductance (LOUT) so that the inductor peak-topeak ripple current is approximately between 20% and 30% of the IOUT(max) (peak current in the application). It is
also important to size the inductor properly so that the valley current does not hit the negative low-side current
limit.
7.4.2 Force CCM Mode
The TPS566238 and TPS566238P operate in Force CCM (FCCM) mode, which keeps the converter operating in
continuous current mode during light-load conditions and allows the inductor current to become negative. During
FCCM mode, the switching frequency (FSW) is maintained at an almost constant level over the entire load range,
which is suitable for applications requiring tight control of the switching frequency and output voltage ripple at the
cost of lower efficiency under light load.
7.4.3 Standby Operation
The TPS56623x can be placed in standby mode by pulling the EN pin low. The device operates with a shutdown
current of 3.2 µA when in standby condition. The EN pin is pulled high internally. When floating, the part is
enabled by default.
14
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 8-1 shows a typical application for TPS566231 with 1-V output. This design converts an
input voltage range of 3 V to 18 V down to 1 V with a maximum output current of 6 A.
8.2 Typical Application
Figure 8-1. 1-V, 6-A Reference Design
8.2.1 Design Requirements
Table 8-1 lists the design parameters for this example.
Table 8-1. Design Parameters
PARAMETER
VOUT
Output voltage
IOUT
Output current
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
FSW
TA
CONDITIONS
MIN
TYP
MAX
1
V
6
0.1 A - 6 A load step, 2.5 A/μs
A
±50
3
CCM condition
12
UNIT
mV
18
V
14
mV(P-P)
Switching frequency
600
kHz
Ambient temperature
25
°C
8.2.2 Detailed Design Procedure
8.2.2.1 External Component Selection
8.2.2.1.1 Output Voltage Set Point
To change the output voltage of the application, it is necessary to change the value of the upper feedback
resistor. By changing this resistor, you can change the output voltage above 0.6 V. See Equation 4.
VOUT
0 . 6 u (1
R UPPER
)
R LOWER
(4)
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8.2.2.1.2 Inductor Selection
The inductor ripple current is filtered by the output capacitor. A higher inductor ripple current means the output
capacitor should have a ripple current rating higher than the inductor ripple current. See Table 8-2 for
recommended inductor values.
The RMS and peak currents through the inductor can be calculated using Equation 5 and Equation 6. It is
important that the inductor is rated to handle these currents.
§
¨2
¨ I OUT
¨
©
IL RMS
IL(peak)
IOUT
1 §¨ VOUT u ( VIN (max) VOUT ) ·¸
u
12 ¨© VIN (max) u L OUT u FSW ¸¹
2·
¸
¸
¸
¹
(5)
IL(ripple)
2
(6)
During transient and short-circuit conditions, the inductor current can increase up to the current limit of the
device so it is safe to choose an inductor with a saturation current higher than the peak current under current
limit condition.
8.2.2.1.3 Output Capacitor Selection
After selecting the inductor the output capacitor needs to be optimized. In D-CAP3, the regulator reacts within
one cycle to the change in duty cycle so the good transient performance can be achieved without needing large
amounts of output capacitance. The recommended output capacitance range is given in Table 8-2. It is not
recommended to choose the combination of minimum inductance and minimum capacitance or maximum
inductance and maximum capacitance.
Ceramic capacitors have very low ESR, otherwise the maximum ESR of the capacitor should be less than
VOUT(ripple)/IOUT(ripple).
Table 8-2. Recommended Component Values
LOUT (µH)
COUT (µF)
VOUT (V)
RLOWER (kΩ)
RUPPER
(kΩ)
MIN
TYP
MAX
MIN
MAX
0.6
10
0
0.68
1
4.7
44
220
-
16
CFF (PF)
1
30
20
0.68
1
4.7
44
220
-
1.2
20
20
1
1.2
4.7
44
220
-
1.8
20
40
1
1.5
4.7
44
220
0-50
3.3
20
90
1.5
2.2
4.7
44
220
10-100
5.0
30
220
1.5
2.2
4.7
44
220
10-100
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8.2.2.1.4 Input Capacitor Selection
The devices require input decoupling capacitors on power supply input VIN and the bulk capacitors are needed
depending on the application. The minimum input capacitance required is given in Equation 7.
CIN(min) =
IOUT ×VOUT
VINripple ×VIN ×FSW
(7)
TI recommends using high-quality X5R or X7R input decoupling capacitors of 30 µF on the input voltage pin VIN.
The voltage rating on the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of the application. The input ripple
current is calculated by Equation 8:
ICIN(rms) = IOUT ×
(VIN(min)-VOUT )
VOUT
×
VIN(min)
VIN(min)
(8)
A 1-µF ceramic capacitor is needed for the decoupling capacitor on VCC pin.
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8.2.3 Application Curves
Figure 8-2 through Figure 8-25 apply to the circuit of Figure 8-1. VIN = 12-V. TA = 25°C unless otherwise
specified.
95
100
90
90
80
70
Efficiency (%)
Efficiency (%)
85
80
75
70
60
50
40
30
65
55
0.001
0.01
0.1
I-Load (A)
1
0
0.001
10
0.01
1Vou
0.1
I-Load (A)
1
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
Load Regulation (%)
0.6
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
0.01
0.1
I-Load (A)
1
-1
0.001
10
0.01
1Vlo
Figure 8-4. TPS566231 Load Regulation
0.1
I-Load (A)
10
D106
800
Switching Frequency (kHz)
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
500
400
300
200
700
600
500
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
100
0
0.001
1
Figure 8-5. TPS566238 Load Regulation
700
600
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V,VOUT=1V
0.8
0.4
10
D101
1
-1
0.001
0.01
0.1
I-Load (A)
1
10
400
0.001
0.01
1VFs
Figure 8-6. TPS566231 FSW vs Output Load
18
1
Figure 8-3. TPS566238 Efficiency Curve
0.6
Switching Frequency (kHz)
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
10
Figure 8-2. TPS566231 Efficiency Curve
0.8
Load Regulation (%)
20
VVIN=3V, VOUT=1V
VVIN=5V, VOUT=1V
VVIN=12V, VOUT=1V
60
0.1
I-Load (A)
1
10
D103
Figure 8-7. TPS566238 FSW vs Output Load
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800
1
0.8
0.6
Line Regulation (%)
Switching Frequency (%)
700
600
500
400
0.4
0.2
0
-0.2
-0.4
-0.6
300
-0.8
-1
200
3
4
5
6
7
8
3
9 10 11 12 13 14 15 16 17 18
VIN (V)
1V6A
4
5
6
7
IOUT = 6 A
9 10 11 12 13 14 15 16 17 18
VIN (V)
1V_l
IOUT = 0.1 A
Figure 8-8. Switching Frequency vs Input Voltage
Figure 8-9. TPS566231 Line Regulation
1
1
0.8
0.8
0.6
0.6
Line Regulation (%)
Line Regulation (%)
8
0.4
0.2
0
-0.2
-0.4
0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
VIN (V)
D104
3
4
5
6
IOUT = 0.1 A
7
8
9 10 11 12 13 14 15 16 17 18
VIN (V)
1V_l
IOUT = 6 A
Figure 8-10. TPS566238 Line Regulation
Figure 8-11. Line Regulation
Vout=20mV/div (AC coupled)
Vout=10mV/div (AC coupled)
SW=5V/div
SW=5V/div
2us/div
10us/div
IOUT = 0.01 A
IOUT = 0.01 A
Figure 8-12. TPS566231 Output Voltage Ripple
Figure 8-13. TPS566238 Output Voltage Ripple
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VIN=5V/div
Vout=20mV/div (AC coupled)
EN=2V/div
SW=5V/div
Vout=500mV/div
2us/div
1ms/div
Figure 8-14. Output Voltage Ripple, IOUT = 6 A
Figure 8-15. Start-Up Through EN, IOUT = 3 A
VIN=5V/div
VIN=5V/div
EN=2V/div
EN=2V/div
Vout=500mV/div
Vout=500mV/div
200us/div
4ms/div
Figure 8-16. Shut-down Through EN, IOUT = 3 A
Figure 8-17. Start-up with VIN Rising, IOUT = 3 A
VIN=5V/div
Vout=50mV/div (AC coupled)
EN=2V/div
Vout=500mV/div
Iout=5A/div
4ms/div
200us/div
0.6 A to 5.4 A
Figure 8-18. Start-up with VIN Falling, IOUT = 3 A
20
Slew Rate = 2.5 A/μs
Figure 8-19. TPS566231 Transient Response
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Vout=50mV/div (AC coupled)
Vout=50mV/div (AC coupled)
Iout=5A/div
Iout=5A/div
200us/div
200us/div
0.1 A to 6 A
Slew Rate = 2.5 A/μs
Figure 8-20. TPS566231 Transient Response
0.6 A to 5.4 A
Slew Rate = 2.5 A/μs
Figure 8-21. TPS566238 Transient Response
Vout=1V/div
Vout=50mV/div (AC coupled)
SW=10V/div
Iout=5A/div
IL=10A/div
80us/div
200us/div
0.1 A to 6 A
Slew Rate = 2.5 A/μs
Figure 8-22. TPS566238 Transient Response
Vout=1V/div
Figure 8-23. TPS566231 Normal Operation to
Output Hard Short
Vout=200mV/div
SW=10V/div
SW=10V/div
IL=10A/div
IL=10A/div
80us/div
10ms/div
Figure 8-24. TPS566238 Normal Operation to
Output Hard Short
Figure 8-25. Output Hard Short Hiccup
9 Power Supply Recommendations
The TPS56623x is intended to be powered by a well-regulated dc voltage. The input voltage range is 3 V to 18
V. The input supply voltage must be greater than the desired output voltage for proper operation. Input supply
current must be appropriate for the desired output current. If the input voltage supply is located far from the
TPS56623x circuit, additional input bulk capacitance is recommended. Typical values are 100 μF to 470 μF.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
•
•
•
A four-layer PCB for good thermal performance and with maximum ground plane is recommended. 55-mm ×
60-mm, four-layer PCB with 2-1-1-2 oz copper is used as example.
Place the decoupling capacitors right across VIN and VCC as close as possible.
Place an output inductor and capacitors with IC at the same layer. SW routing should be as short as possible
to minimize EMI, and should be a width plane to carry big current. Enough vias should be added to the PGND
connection of output capacitor and also as close to the output pin as possible.
Place a BST resistor and capacitor with IC at the same layer, close to BST and SW plane. 15-mil width trace
is recommended to reduce line parasitic inductance.
Feedback must be routed away from the switching node, BST node, or other high frequency signal.
VIN trace must be wide to reduce the trace impedance and provide enough current capability.
Place multiple vias under the device near VIN and PGND and near input capacitors to reduce parasitic
inductance and improve thermal performance.
10.2 Layout Example
Figure 10-1 shows the recommended top-side layout. Component reference designators are the same as the
circuit shown in Figure 8-1. Resistor divider for EN is not used in the circuit of Figure 8-1, but are shown in the
layout for reference.
GND
C
C
C
R
Additional Vias to
the GND plane
GND
VCC
FB
EN
4
Additional Vias to
the GND plane
To Enable
Control
R
To Other
GND Layer
PGND
C
C
SS
SW
C
C
BST
VIN
VIN
L
C
VOUT
C
VIN
R
Figure 10-1. Top-Layer Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
D-CAP3™, HotRod™, Eco-Mode™, ULQ™, Eco-mode™, and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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5-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS566231PRQFR
ACTIVE
VQFN-HR
RQF
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1ID
TPS566231RQFR
ACTIVE
VQFN-HR
RQF
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1H4
TPS566238PRQFR
ACTIVE
VQFN-HR
RQF
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1IE
TPS566238RQFR
ACTIVE
VQFN-HR
RQF
9
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1H5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
