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TPS568215OA
SLVSDU7 – JANUARY 2017
TPS568215OA 4.5-V to 17-V Input , 8-A Synchronous Step-Down SWIFT™ Converter
1 Features
3 Description
•
•
•
The TPS568215OA is TI's smallest monolithic 8-A
synchronous buck converter with an adaptive on-time
D-CAP3™ control mode. The device integrates low
RDS(on) power MOSFETs that enable high efficiency
and it offers ease-of-use with minimal external
component count for space-conscious power
systems. Key features include a very accurate
reference voltage, fast load transient response, Outof-Audio mode, adjustable current limit and no
requirement for external compensation. A forced
continuous conduction mode helps meet tight voltage
regulation accuracy requirements for performance
DSPs and FPGAs. The TPS568215OA is available in
a thermally enhanced 18-pin HotRod™ QFN package
and is designed to operate from –40°C to 150°C
junction temperature. TPS568215OA is pin to pin
compatible with TPS568215 and TPS56C215 which
gives the user flexibility to pick solutions from 6A to
12A in the same footprint.
Integrated 19-mΩ and 9.4-mΩ MOSFETs
Selectable FSW of 400 kHz, 800 kHz or 1.2 MHz
Out-of-Audio Feature to Keep Switching
Frequency Out of Audio Frequency Range
Adjustable Current Limit Settings with Hiccup Restart
0.6 V ±1% Reference Voltage Across Full
Temperature Range
Optional External 5-V Bias Support for Enhanced
Efficiency
D-CAP3™ Control Mode for Fast Transient
Response
0.6 V to 5.5 V Output Voltage Range
Supports all Ceramic Capacitors
Monotonic Startup into Pre-biased Outputs
Adjustable Soft Start with a Default 1-ms Soft
Start Time
–40°C to 150°C Operating Junction Temperature
Small 3.5-mm x 3.5-mm HotRod™ QFN Package
1
•
•
•
•
•
•
•
•
•
•
PART NUMBER
TPS568215OA
PACKAGE
BODY SIZE (NOM)
VQFN (18)
3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Device Information(1)
Server and Storage
Set top Box, High-End DTV
Laptop and Gaming Systems
spacer
spacer
Typical Application Schematic
Efficiency vs Output Current
100
TPS568215OA
VREG5
VIN
CIN
MODE
90
RM_H
VREG5
RM_L
PWRGD
PGOOD
BOOT
LOUT
VOUT
OUT
SW
EN
COUT
SS
CSS
RUPPER
80
75
70
65
60
FB
AGND PGND
85
Efficiency (%)
VIN
95
V IN =4.5V, VOUT= 1.2V, FSW = 400kHz
V IN =12V, VOUT=1.2V, FSW = 400kHz
V IN =17V, VOUT=1.2V, FSW = 400kHz
55
RLOWER
50
0
Copyright © 2016, Texas Instruments Incorporated
1
2
3
4
5
Output Current (A)
6
7
8
C011
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS568215OA
SLVSDU7 – JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 19
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
Device Support ....................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
2
DATE
REVISION
NOTES
January 2017
*
Initial release.
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5 Pin Configuration and Functions
RNN Package
18-Pin VQFN
AGND 12
1 BOOT
VIN 11
2 VIN
13 FB
14 SS
15 EN
16 PGOOD
17 VREG5
18 MODE
18 MODE
TOP VIEW
17 VREG5
16 PGOOD
15 EN
14 SS
13 FB
BOTTOM VIEW
BOOT 1
12 AGND
VIN 2
11 VIN
PGND 10
3 PGND
PGND 3
10 PGND
PGND 9
4 PGND
PGND 4
9 PGND
PGND 8
5 PGND
PGND 5
8 PGND
7
6
6
SW
SW
7
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
BOOT
I
Supply input for the gate drive voltage of the high-side MOSFET. Connect a 0.1-µF bootstrap capacitor
between BOOT and SW.
VIN
P
Input voltage supply pin for the control circuitry. Connect the input decoupling capacitors between VIN and
PGND.
PGND
G
Power GND terminal for the controller circuit and the internal circuitry.
2,11
3, 4, 5,
8, 9, 10
6, 7
SW
O
Switch node terminal. Connect the output inductor to this pin.
12
AGND
G
Ground of internal analog circuitry. Connect AGND to PGND plane.
13
FB
I
Converter feedback input. Connect to the resistor divider between output voltage and AGND.
14
SS
O
Soft-Start time selection pin. Connecting an external capacitor sets the soft-start time and if no external
capacitor is connected, the soft-start time in 1ms.
15
EN
I
Enable input control, leaving this pin floating enables the converter. It can also be used to adjust the input
UVLO by connecting to the resistor divider between VIN and EN.
16
PGOOD
O
Open Drain Power Good Indicator, it is asserted low if output voltage is out of PGOOD threshold,
Overvoltage or if the device is under thermal shutdown, EN shutdown or during soft start.
17
VREG5
I/O
4.7-V internal LDO output which can also be driven externally with a 5V input. This pin supplies voltage to
the internal circuitry and gate driver. Bypass this pin with a 4.7-μF capacitor.
18
MODE
I
Switching Frequency, Current Limit selection and Light load operation mode selection pin. Connect this pin
to a resistor divider from VREG5 and AGND for different MODE options shown in table 4.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input Voltage
Output Voltage
(1)
MIN
MAX
VIN
–0.3
20
SW
–2
19
SW(10 ns transient)
–3
20
EN
–0.3
6.5
BOOT –SW
–0.3
6.5
BOOT
–0.3
25.5
SS, MODE, FB
–0.3
6.5
VREG5
–0.3
6
PGOOD
–0.3
6.5
Output Current, IOUT (2)
UNIT
V
V
10
A
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
In order to be consistent with the TI reliability requirement of 100k continuos Power-On-Hours with 105°C junction temperature at the
max output current of 10A, the converter's duty cycle should be limited to 60% operation as to prevent electromigration failure in the
solder. If higher duty cycle is required at 10A load the total power on hours or the junction temperature have to be reduced.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Input Voltage
TJ
4
NOM
MAX
VIN
4.5
SW
–1.8
17
BOOT
–0.1
23.5
VREG5
–0.1
5.2
-40
150
Operating junction temperature
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UNIT
17
V
°C
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6.4 Thermal Information
TPS568215OA
THERMAL METRIC (1)
RNN (VQFN)
UNIT
18 PINS
RθJA
Junction-to-ambient thermal resistance
42.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23.9
°C/W
RθJB
Junction-to-board thermal resistance
10.0
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
10.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = –40°C to 150°C, VIN=12V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IIN
VIN supply current
TJ = 25°C, VEN=5 V, non switching
IVINSDN
VIN shutdown current
TJ = 25°C, VEN=0 V
850
µA
7
µA
LOGIC THRESHOLD
VENH
EN H-level threshold voltage
1.175
1.225
1.3
V
VENL
EN L-level threshold voltage
1.025
1.104
1.15
V
VENHYS
0.121
IENp1
EN pull-up current
IENp2
V
VEN = 1.0 V
0.35
1.91
2.95
µA
VEN = 1.3 V
3
4.197
5.5
µA
FEEDBACK VOLTAGE
TJ = 25°C
VFB
598
600
602
mV
597.5
600
602.5
mV
TJ = –40°C to 85°C
594
600
602.5
mV
TJ = –40°C to 150°C
594
600
606
mV
TJ = 0°C to 85°C
FB voltage
LDO VOLTAGE
VREG5
LDO Output voltage
TJ = –40°C to 150°C
4.58
4.7
4.83
V
ILIM5
LDO Output Current limit
TJ = –40°C to 150°C
100
150
200
mA
RDS(on)H
High side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
19
mΩ
RDS(on)L
Low side switch resistance
TJ = 25°C, VVREG5 = 4.7 V
9.4
mΩ
Soft start charge current
TJ = -40°C to 150°C
MOSFET
SOFT START
Iss
4.9
6
7.1
µA
6
7.1
8.15
A
8
9.4
10.8
A
10
11.8
13.5
A
CURRENT LIMIT
ILIM-1 option, Valley Current
IOCL
Current Limit (Low side sourcing)
ILIM option, Valley Current
ILIM+1 option, Valley Current
Current Limit (Low side negative)
Valley Current
3
A
POWER GOOD
VPGOODTH
PGOOD threshold
VFB falling (fault)
84%
%VREF
VFB rising (good)
93%
%VREF
VFB rising (fault)
116%
%VREF
VFB falling (good)
107%
%VREF
Hiccup detect
68% x
VFB
OUTPUT UNDERVOLTAGE PROTECTION
VUVP
Output UVP threshold
THERMAL SHUTDOWN
TSDN
TSDN
Shutdown temperature
Thermal shutdown threshold
VREG5
Hysteresis
VREG5 thermal shutdown threshold
Shutdown temperature
Hysteresis
160
°C
15
°C
171
°C
18
°C
UVLO
UVLO
UVLO threshold
VREG5 rising voltage
4.1
4.3
4.5
VREG5 falling voltage
3.34
3.57
3.8
VREG5 hysteresis
6
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730
V
V
mV
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6.6 Timing Requirements
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
310
340
380
ns
ON-TIME TIMER CONTROL
tON
SW On Time
VIN = 12 V, VOUT=3.3 V, FSW = 800 kHz
tON min
SW Minimum on time
VIN = 17 V, VOUT=0.6 V, FSW= 1200 kHz
tOFF
SW Minimum off time
25°C, VFB=0.5 V
FSWOOA
OOA Switching Frequency
TJ = -40°C to 150°C, No Load
54
20
ns
310
ns
27
KHz
SOFT START
tSS
Soft start time
Internal soft start time
1.045
ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
tUVPDEL
Output Hiccup delay relative to SS time
UVP detect
1
cycle
tUVPEN
Output Hiccup enable delay relative to
SS time
UVP detect
7
cycle
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20
1200
18
1100
Shutdown Current (uA)
Non-Switching Operating Quiescent Current(uA)
6.7 Typical Characteristics
1000
900
800
700
600
16
14
12
10
8
6
4
500
2
VIN = 12V
±50
0
50
100
C001
150
C002
30
0.602
RDS(on) - On Resistance (m )
VFB - Feedback Voltage (V)
100
Figure 2. Shutdown Current vs Temperature
0.603
0.601
0.6
0.599
0.598
VIN =12V
0.597
±50
0
50
100
25
20
15
VIN =12V
10
150
TJ - Junction Temperature (ƒC)
0
±50
50
100
150
TJ - Junction Temperature (ƒC)
C003
Figure 3. Feedback Voltage vs Temperature
C004
Figure 4. High-side Rdson vs Temperature
15
8
Soft-Start Charge Current (uA)
14
RDS(ON) - On Resistance (m )
50
TJ - Junction Temperature (ƒC)
Figure 1. Quiescent Current vs Temperature
13
12
11
10
9
8
7
6
7
6
5
VIN =12V
5
VIN =12V
4
±50
0
50
100
TJ - Junction Temperature (ƒC)
Figure 5. Low-side Rdson vs Temperature
8
0
±50
150
TJ - Junction Temperature (ƒC)
VIN =12V
0
400
150
±50
0
50
100
TJ - Junction Temperature (ƒC)
C005
150
C006
Figure 6. Soft-Start Charge Current vs Temperature
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Typical Characteristics (continued)
6
Enable Pin Pull-up Current (uA)
Enable Pull-up Current (uA)
3
2.5
2
1.5
5.5
5
4.5
4
3.5
VIN =12V
1
0
±50
50
100
TJ - Junction Temperature (ƒC)
VIN =12V
3
150
0
±50
50
100
150
TJ - Junction Temperature (ƒC)
C007
Figure 7. Enable Pull-Up Current, VEN =1.0V
C008
Figure 8. Enable Pull-Up Current, VEN =1.3V
12
120
Low Side Valley Current Limit (A)
ILIM option
PGOOD Threshold (%)
115
110
105
VFB rising
VFB falling
VFB rising
VFB falling
100
95
90
85
11
10
9
8
7
6
80
1
2
3
4
5
6
7
8
9
TJ - Junction Temperature (ƒC)
10
50
100
150
TJ - Junction Temperature (ƒC)
C010
Figure 10. Valley Current Limit vs Temperature
100
90
90
80
80
70
70
Efficiency (%)
100
60
50
40
60
50
40
30
30
20
20
V IN = 12V, VOUT =1.2V
V IN = 12V, VOUT =3.3V
VIN = 12V, VOUT =5 .5V
10
0
0.001
0
±50
C009
Figure 9. PGOOD Threshold vs Temperature
Efficiency(%)
ILIM-1 Option
0.01
0.1
Output Current(A)
VIN = 12V, VOUT= 1.2V
VIN = 12V, VOUT= 3.3V
VIN = 12V, VOUT= 5.5V
10
0
0
1
Figure 11. Efficiency, Mode = OOA, FSW = 400kHz
1
2
3
4
5
6
7
Output Current (A)
C002
8
C014
Figure 12. Efficiency, Mode = FCCM, FSW = 400kHz
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency(%)
Typical Characteristics (continued)
60
50
40
V IN =12V, VOUT = 1.2V
V IN =12V, VOUT = 3.3V
10
0
0.001
0.01
0.1
VIN = 12V, VOUT= 1.2V
VIN = 12V, VOUT= 3.3V
VIN = 12V, VOUT= 5.5V
10
0
0
1
Output Current(A)
1
2
3
4
5
6
7
Output Current (A)
C003
8
C016
Figure 14. Efficiency, Mode = FCCM, FSW = 1200kHz
Figure 13. Efficiency, Mode = OOA, FSW = 1200kHz
600
Switching Frequency (kHz)
1.198
Output Voltage (V)
40
20
20
1.197
1.196
1.195
VIN = 4.5V, VOUT= 1.2V
VIN = 12V, VOUT= 1.2V
VIN = 17V,VOUT = 1.2V
1.194
0
1
2
3
4
5
6
7
Output Current (A)
1000
500
400
300
VIN = 12V,VOUT = 1.2V
VIN = 12V,VOUT= 3.3V
VIN = 12V,VOUT= 5.5V
200
8
0
1
2
3
4
5
6
7
Output Current (A)
C017
Figure 15. Load Regulation, FSW = 400kHz
8
C018
Figure 16. FSW Load Regulation, Mode = FCCM, FSW =
400kHz
1400
VIN = 12V, VOUT= 1.2V
VIN = 12V, VOUT= 3.3V
VIN = 12V, VOUT= 5.5V
Switching Frequency (kHz)
Switching Frequency (kHz)
50
30
30
900
800
700
600
VIN = 12V, VOUT= 1.2V
VIN = 12V, VOUT= 3.3V
VIN = 12V, VOUT= 5.5V
1300
1200
1100
1000
0
1
2
3
4
5
Output Current (A)
6
7
8
0
1
2
3
4
5
Output Current (A)
C019
Figure 17. FSW Load Regulation, Mode = FCCM, FSW =
800kHz
10
60
6
7
8
C020
Figure 18. FSW Load Regulation, Mode = FCCM, FSW =
1200kHz
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Typical Characteristics (continued)
1400
Switching Frequency(KHz)
1200
1000
800
600
400
FSW = 400kHz
FSW = 800kHz
FSW = 1200kHz
200
0
0
1
2
3
4
5
6
Output Current(A)
7
8
C004
Figure 19. FSW Load Regulation, Mode = OOA, VIN = 12V, VOUT=1.2V
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7 Detailed Description
7.1 Overview
The TPS568215OA is a high density synchronous step down buck converter which can operate from 4.5-V to 17V input voltage (VIN). It has 19-mΩ and 9-mΩ integrated MOSFETs that enable high efficiency up to 10 A. The
device employs D-CAP3™ mode control that provides fast transient response with no external compensation
components and an accurate feedback voltage. The control topology provides seamless transition between
FCCM operating mode at higher load condition and OOA operation at lighter load condition. OOA feature allows
the TPS568215OA to keep switching frequency above the audible frequency range. The TPS568215OA is able
to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and
ultralow ESR ceramic capacitors.
The TPS568215OA has three selectable switching frequencies (FSW) 400kHz, 800kHz and 1200kHz which gives
the flexibility to optimize the design for higher efficiency or smaller size. There are three selectable current limits.
All these options are configured by choosing the right voltage on the MODE pin.
The TPS568215OA has a 4.7 V internal LDO that creates bias for all internal circuitry. There is a feature to
overdrive this internal LDO with an external voltage on the VREG5 pin which improves the converter’s efficiency.
The undervoltage lockout (UVLO) circuit monitors the VREG5 pin voltage to protect the internal circuitry from low
input voltages. The device has an internal pull-up current source on the EN pin which can enable the device
even with the pin floating.
Soft-start time can be selected by connecting a capacitor to the SS pin. The device is protected from output
short, undervoltage and over temperature conditions.
12
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7.2 Functional Block Diagram
PG rising threshold
TPS568215OA
+
PGOOD Logic
UV
UV threshold
PGOOD
+
+
Delay
UVP / OVP
Logic
+
VREG5
PG falling threshold
OV threshold
OV
Internal Ramp
VREF
VIN
UVLO
+
-
-
Error Amp
LDO
+
+
+
FB
Control Logic
Internal SS
One shot
SS
BOOT
BOOT
x
x
x
x
x
x
x
On Time
Min On Time/Off Time
FCCM/SKIP
Soft-Start
Power Good
Internal/External VREG5
UVP/TSD
SW
SW
XCON
VREG5
PGND
Light Load Operation/
Current Limit/
Switching Frequency
MODE
TSD 160C/171C
SW
OCL
+
Ip1
Ip2
+
EN
ZC
+
Enable Threshold
NOCL
+
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7.3 Feature Description
7.3.1 PWM Operation and D-CAP3™ Control
The TPS568215OA operates using the adaptive on-time PWM control with a proprietary D-CAP3™ control which
enables low external component count with a fast load transient response while maintaining a good output
voltage accuracy. At the beginning of each switching cycle the high side MOSFET is turned on for an on-time set
by an internal one shot timer. This on-time is set based on the converter’s input voltage, output voltage and the
pseudo-fixed frequency hence this type of control topology is called an adaptive on-time control. The one shot
timer resets and turns on again once the feedback voltage (VFB) falls below the internal reference voltage (VREF).
An internal ramp is generated which is fed to the FB pin to simulate the output voltage ripple. This enables the
use of very low-ESR output capacitors such as multi-layered ceramic caps (MLCC). No external current sense
network or loop compensation is required for DCAP3™ control topology.
The TPS568215OA includes an error amplifier that makes the output voltage very accurate. This error amplifier
is absent in other flavors of DCAP3™. For any control topology that is compensated internally, there is a range of
the output filter it can support. The output filter used with the TPS568215OA is a low pass L-C circuit. This L-C
filter has double pole that is described in
1
¦P =
2 ´ p ´ LOUT ´ COUT
(1)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS568215OA. The low frequency L-C double pole has a 180 degree in phase. At the output filter
frequency, the gain rolls off at a –40dB per decade rate and the phase drops rapidly. The internal ripple
generation network introduces a high-frequency zero that reduces the gain roll off from –40dB to –20dB per
decade and increases the phase to 90 degree one decade above the zero frequency. The internal ripple injection
high frequency zero is changed according to the switching frequency selected as shown in table below. The
inductor and capacitor selected for the output filter must be such that the double pole is located close enough to
the high-frequency zero so that the phase boost provided by this high-frequency zero provides adequate phase
margin for the stability requirement. The crossover frequency of the overall system should usually be targeted to
be less than one-fifth of the switching frequency (FSW).
Table 1. Ripple Injection Zero
SWITCHING FREQUENCY (kHz)
ZERO LOCATION (kHz)
400
7.1
800
14.3
1200
21.4
Table 2 lists the inductor values and part numbers that are used to plot the efficiency curves in the Typical
Characteristics section.
Table 2. Inductor Values
VOUT(V)
1.2
3.3
5.5
(1)
14
FSW(kHz)
LOUT(uH)
Würth PART
NUMBER (1)
400
1.2
744325120
800
0.68
744311068
1200
0.47
744314047
400
2.4
744325240
800
1.5
744314150
1200
1.1
744314110
400
3.3
744325330
800
2.4
744325240
1200
1.2
744325120
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7.3.2 Out-of-Audio Operation™
The TPS568215OA is designed with OOA feature that keeps switching frequency above the audible frequency
region at light load or no load conditions. Once the converter determines that there is no switching for longer than
40us, it turns on the LS FET which brings VFB lower than internal VREF and initiates a new Ton cycle. This
ensures that the switching frequency doesn’t go lower than 25kHz typical.
7.3.3 4.7 V LDO and External Bias
The VREG5 pin is the output of the internal 4.7-V linear regulator that creates the bias for all the internal circuitry
and MOSFET gate drivers. The VREG5 pin needs to be bypassed with a 4.7-µF capacitor. An external voltage
that is above the LDO's internal output voltage can override the internal LDO, switching it to the external rail once
a higher voltage is detected. This enhances the efficiency of the converter because the quiescent current now
runs off this external rail instead of the input power supply. The UVLO circuit monitors the VREG5 pin voltage
and disables the output when VREG5 falls below the UVLO threshold. When using an external bias on the
VREG5 rail, any power-up and power-down sequencing can be applied but it is important to understand that if
there is a discharge path on the VREG5 rail that can pull a current higher than the internal LDO's current limit
(ILIM5) from the VREG5, then the VREG5 LDO turns off thereby shutting down the output of TPS568215OA. If
such condition does not exist and if the external VREG5 rail is turned off, the VREG5 voltage switches over to
the internal LDO voltage which is 4.7 V typically in a few nanoseconds. Figure 26 below shows this transition of
the VREG5 voltage from an external bias of 5.5 V to the internal LDO output of 4.7 V when the external bias to
VREG5 is disabled while the output of TPS568215OA remains unchanged.
7.3.4 MODE Selection
TPS568215OA has a MODE pin that can offer 16 different states of operation as a combination of Current Limit,
Switching Frequency and Light Load operation. The device can operate at three different current limits ILIM1,ILIM and ILIM+1 to support an output continuous current of 6 A, 8 A and 10A respectively. the device can
provide 10A output current only at switching frequencies of 400kHz and 800kHz.The TPS568215OA is designed
to compare the valley current of the inductor against the current limit thresholds so it is important to understand
that the output current will be half the ripple current above the valley current. TPS568215OA can operate at three
different frequencies of 400 kHz, 800 kHz and 1200 kHz and also can choose between OOA and FCCM mode.
The device reads the voltage on the MODE pin during start-up and latches onto one of the MODE options listed
below in table 3. The voltage on the MODE pin can be set by connecting this pin to the center tap of a resistor
divider connected between VREG5 and AGND. A guideline for the top resistor (RM_H) and the bottom resistor
(RM_L) as 5% resistors is shown in Table 3. It is important that the voltage for the MODE pin is derived from the
VREG5 rail only since internally this voltage is referenced to detect the MODE option. The MODE pin setting can
be reset only by a VIN power cycling.
Table 3. Mode Pin Resistor Settings
RM_L (kΩ)
RM_H (kΩ)
LIGHT LOAD OPERATION
CURRENT LIMIT
FREQUENCY (kHz)
5.1
300
FCCM
ILIM-1
400
10
200
FCCM
ILIM
400
20
240
FCCM
ILIM+1
400
20
160
FCCM
ILIM-1
800
20
120
FCCM
ILIM
800
51
240
FCCM
ILIM+1
800
51
200
FCCM
ILIM-1
1200
51
180
FCCM
ILIM
1200
51
150
OOA
ILIM-1
400
51
120
OOA
ILIM
400
51
110
OOA
ILIM+1
400
51
91
OOA
ILIM-1
800
51
82
OOA
ILIM
800
51
75
OOA
ILIM+1
800
51
62
OOA
ILIM-1
1200
51
51
OOA
ILIM
1200
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Figure 20 below shows the typical start-up sequence of the device once the enable signal crosses the EN turnon threshold. After the voltage on VREG5 crosses the rising UVLO threshold it takes about 500us to read the
first mode setting and approximately 100us from there to finish the last mode setting. The output voltage starts
ramping after the mode reading is done.
EN threshold
1.2V
EN
VREG5 UVLO
4.3V
VREG5
MODE16
MODE1
MODE
500us(typ)
100us
tss(1ms)
VOUT
Figure 20. Power-Up Sequence
7.3.5 Soft Start and Pre-biased Soft Start
The TPS568215OA has an adjustable soft-start time that can be set by connecting a capacitor on SS pin. When
the EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor (CSS)
connected between SS and AGND. The devices tracks the lower of the internal soft-start voltage or the external
soft-start voltage as the reference. The equation for the soft-start time (TSS) is shown in Equation 2:
C × VREF
TSS(S) = SS
ISS
where
•
VREF is 0.6 V and ISS is 6 µA
(2)
If the output capacitor is pre-biased at startup, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme ensures that the
converters ramp up smoothly into regulation point.
7.3.6 Enable and Adjustable UVLO
The EN pin controls the turn-on and turn-off of the device. When EN pin voltage is above the turn-on threshold
which is around 1.2 V, the device starts switching and when the EN pin voltage falls below the turn-off threshold
which is around 1.1V it stops switching. If the user application requires a different turn-on (VSTART) and turn-off
thresholds (VSTOP) respectively, the EN pin can be configured as shown in Figure 21 by connecting a resistor
divider between VIN and EN. The EN pin has a pull-up current Ip1 that sets the default state of the pin when it is
floating. This current increases to Ip2 when the EN pin voltage crosses the turn-on threshold. The UVLO
thresholds can be set by using Equation 3 and Equation 4.
16
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TPS568215OA
VIN
Ip1
Ih
R1
EN
R2
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Adjustable VIN Under Voltage Lock Out
æV
ö
VSTART ç ENFALLING ÷ - VSTOP
è VENRISING ø
R1 =
æ V
ö
Ip1 ç1 - ENFALLING ÷ + Ih
V
ENRISING ø
è
(3)
R1´ VENFALLING
VSTOP - VENFALLING + R1 Ip2
R2 =
where
•
•
•
•
•
Ip2 = 4.197 μA
Ip1 = 1.91 μA
Ih = 2.287 μA
VENRISING = 1.225 V
VENFALLING = 1.104 V
(4)
7.3.7 Power Good
The Power Good (PGOOD) pin is an open drain output. Once the FB pin voltage is between 93% and 107% of
the internal reference voltage (VREF) the PGOOD is de-asserted and floats after a 200 μs de-glitch time. A pull-up
resistor of 10 kΩ is recommended to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin voltage
is lower than VUVP or greater than VOVP threshold; or, in an event of thermal shutdown or during the soft-start
period.
7.3.8 Over Current Protection and Under Voltage Protection
The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch
current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is
proportional to the switch current. During the on time of the high-side FET switch, the switch current increases at
a linear rate determined by input voltage , output voltage, the on-time and the output inductor value. During the
on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the
load current IOUT. If the measured drain to source voltage of the low-side FET is above the voltage proportional to
current limit, the low side FET stays on until the current level becomes lower than the OCL level which reduces
the output current available. When the current is limited the output voltage tends to drop because the load
demand is higher than what the converter can support. When the output voltage falls below 68% of the target
voltage, the UVP comparator detects it and shuts down the device after a wait time of 1ms, the device re-starts
after a hiccup time of 7ms. In this type of valley detect control the load current is higher than the OCL threshold
by one half of the peak to peak inductor ripple current. When the overcurrent condition is removed, the output
voltage returns to the regulated value. If an OCL condition happens during start-up then the device enters
hiccup-mode immediately without a wait time of 1ms.
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7.3.9 Out-of-Bounds Operation
The device has an out-of-bounds (OOB) overvoltage protection that protects the output load at a much lower
overvoltage threshold of 8% above the target voltage. OOB protection does not trigger an overvoltage fault, OOB
protection operates as an early no-fault overvoltage protection mechanism. During the OOB operation, the
controller operates in forced PWM mode only by turning on the low-side FET. Turning on the low-side FET
beyond the zero inductor current quickly discharges the output capacitor thus causing the output voltage to fall
quickly toward the setpoint. During the operation, the cycle-by cycle negative current limit is also activated to
ensure the safe operation of the internal FETs.
7.3.10 UVLO Protection
Under voltage lock out protection (UVLO) monitors the internal VREG5 regulator voltage. When the VREG5
voltage is lower than UVLO threshold voltage, the device is shut off. This protection is non-latching.
7.3.11 Thermal Shutdown
The device monitors the internal die temperature. If this temperature exceeds the thermal shutdown threshold
value (TSDN typically 160°C) the device shuts off. This is a non-latch protection. During start up, if the device
temperature is higher than 160°C the device does not start switching and does not load the MODE settings. If the
device temp goes higher than TSDN threshold after startup, it stops switching with SS reset to ground and an
internal discharge switch turns on to quickly discharge the output voltage. The device re-starts switching when
the temperature goes below the thermal shutdown threshold but the MODE settings are not re-loaded again.
There is a second higher thermal protection on the device TSDN VREG5 which protects it from over temperature
conditions not caused by the switching of the device itself. This threshold is at typically 170°C. Even under
nonswitching condition of the device after exceeding TSDN threshold, if it still continues to heat up the VREG5
output shuts off once temperature goes beyond TSDN VREG5, thereby shutting down the device completely.
7.3.12 Output Voltage Discharge
The device has a 500ohm discharge switch that discharges the output VOUT through SW node during any event
of fault like output overvoltage, output undervoltage , TSD , if VREG5 voltage below the UVLO and when the EN
pin voltage (VEN) is below the turn-on threshold.
7.4 Device Functional Modes
7.4.1 Light Load Operation
When the MODE pin is selected to operate in FCCM mode, the converter operates in continuous conduction
mode (FCCM) during light-load conditions. During FCCM, the switching frequency (FSW) is maintained at an
almost constant level over the entire load range which is suitable for applications requiring tight control of the
switching frequency and output voltage ripple at the cost of lower efficiency under light load. If the MODE pin is
selected to operate in OOA, the device enters pulse skip mode after the valley of the inductor ripple current
crosses zero. The OOA mode maintains higher efficiency at light load with a lower switching frequency but this
switching frequency is restricted to not go below 25kHz typical.
7.4.2
Standby Operation
The TPS568215OA can be placed in standby mode by pulling the EN pin low. The device operates with a
shutdown current of 7uA when in standby condition.
18
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The schematic of Figure 22 shows a typical application for TPS568215OA. This design converts an input voltage
range of 4.5 V to 17 V down to 1.2 V with a maximum output current of 10 A.
8.2 Typical Application
VIN = 4.5 V - 17 V
VIN
C1
0.1µF
C2
0.1µF
C3
22µF
C4
22µF
C5
22µF
U1
C6
22µF
14
EN
15
16
V5
R1 10.0k
R2
18
V5
52.3k
R3
49.9k
L1
C9
2
11
C7
0.047µF PGOOD
TPS568215RNNR
17
VIN
VIN
BOOT
SW
SW
FB
SS
EN
PGOOD
MODE
PGND
PGND
PGND
PGND
PGND
PGND
VREG5
AGND
VOUT = 1.2 V, 8 A
1
6
7
13
0.1µF
3
4
5
8
9
10
VOUT
470nH
C11
47µF
R4
C12
47µF
C13
47µF
C14
47µF
10.0k
C10 56pF
R5
10.0k
12
C8
4.7µF
Copyright © 2016, Texas Instruments Incorporated
Figure 22. Application Schematic
8.2.1 Design Requirements
Table 4. Design Parameters
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT
Output voltage
1.2
V
IOUT
Output current
10
A
ΔVOUT
Transient response
VIN
Input voltage
VOUT(ripple)
Output voltage ripple
fSW
4-A load step
12
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