User's Guide
SLUU465 – November 2010
An 8-V to 14-V Vin 2010 Atom™ E6xx
Tunnel Creek Power System
The TPS59610EVM-634 evaluation module (EVM) is a complete solution for the 2010 Atom™ E6xx
Tunnel Creek Power System from a 12-V input bus. The EVM uses the TPS59610 for Atom CPU and
GPU core, TPS51120 for 5-V and 3.3-V systems, TPS54326 for Topcliff IOH, TPS59124 for DDRII 1.8 V
and CPU VTT 1.05 V, TPS51100 for 0.9 V VTT, TPS74801 for CPU 1.5-V PLL, and CPU C6 RAM 1.05 V.
TPS59610EVM-634 also uses the 3-mm x 3-mm Texas Instruments (TI) power block MOSFET
(CSD86330Q3D) for high-power density and superior thermal performance.
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Contents
Description ................................................................................................................... 4
1.1
Typical Applications ................................................................................................ 4
1.2
Features ............................................................................................................. 4
Atom Tunnel Creek Power System Block Diagram .................................................................... 4
Electrical Performance Specifications .................................................................................... 5
Schematics ................................................................................................................... 7
Test Setup .................................................................................................................. 12
5.1
Test Equipment ................................................................................................... 12
5.2
Recommended Test Setup ...................................................................................... 12
Configuration ............................................................................................................... 13
6.1
CPU and GPU Configuration ................................................................................... 13
6.2
5-V/3.3-V System Configuration ................................................................................ 15
6.3
DDR 1.8-V/1.05-V CPU VTT Configuration ................................................................... 15
6.4
0.9-V VTT and 0.9-V VTTREF Configuration ................................................................. 16
6.5
1.5-V CPU PLL Configuration ................................................................................... 16
6.6
1.05-V CPU C6 RAM Configuration ............................................................................ 16
6.7
1.2-V IOH Configuration ......................................................................................... 17
Test Procedure ............................................................................................................ 17
7.1
Line/Load Regulation and Efficiency Measurement Procedure ............................................ 17
7.2
Onboard Transient Response Measurement ................................................................. 17
7.3
Loop Gain/Phase Measurement ................................................................................ 18
7.4
Equipment Shutdown ............................................................................................ 18
Performance Data and Typical Characteristic Curves ................................................................ 19
8.1
CPU ................................................................................................................ 19
8.2
GPU ................................................................................................................ 23
8.3
5-V/3.3-V System ................................................................................................. 26
8.4
1.8-V DDR/1.05-V CPU VTT .................................................................................... 30
8.5
1.2-V IOH .......................................................................................................... 33
EVM Assembly Drawings and PCB Layout ............................................................................ 35
Bill of Materials ............................................................................................................. 37
List of Figures
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TPS59610EVM-634 Schematic, Sheet 1 of 5 ...........................................................................
TPS59610EVM-634 Schematic, Sheet 2 of 5 ...........................................................................
8-V to 14-V Vin 2010 Atom Tunnel Creek Power System Block Diagram
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OSR is a trademark of Texas Instruments.
Atom is a trademark of Intel Corporation.
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TPS59610EVM-634 Schematic, Sheet 3 of 5 ........................................................................... 9
5
TPS59610EVM-634 Schematic, Sheet 4 of 5 ......................................................................... 10
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TPS59610EVM-634 Schematic, Sheet 5 of 5 ......................................................................... 11
7
TPS59610EVM-634 Recommended Test Setup ...................................................................... 12
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CPU Efficiency
9
CPU Load Regulation ..................................................................................................... 19
10
CPU Enable Turnon
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Enable Turnoff ............................................................................................................. 19
12
CPU Switching Node
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............................................................................................................
......................................................................................................
.....................................................................................................
CPU Vcore Ripple .........................................................................................................
CPU Output Load Release Without Overshoot Reduction ..........................................................
CPU Output Load Release With Maximum Overshoot Reduction ..................................................
CPU Transient From DCM to CCM ....................................................................................
CPU Transient From CCM to DCM .....................................................................................
CPU Bode Plot 12 Vin, 1 V/5 A ..........................................................................................
CPU Top Board ...........................................................................................................
CPU Bottom Board ........................................................................................................
CPU Efficiency .............................................................................................................
GPU Load Regulation .....................................................................................................
GPU Enable Turnon.......................................................................................................
GPU Enable Turnoff.......................................................................................................
GPU Switching Node .....................................................................................................
GPU Vcore Ripple .........................................................................................................
GPU Output Load ReleaseWithout Overshoot Reduction ...........................................................
GPU Output Load ReleaseWith Maximum Overshoot Reduction...................................................
GPU Transient From DCM to CCM .....................................................................................
GPU Transient From CCM to DCM .....................................................................................
GPU Bode Plot 12 Vin, 1 V/5 A .........................................................................................
CPU Top Board ...........................................................................................................
CPU Bottom Board ........................................................................................................
5-V Efficiency ..............................................................................................................
5-V Load Regulation ......................................................................................................
5-V Enable Turnon ........................................................................................................
5-V Enable Turnoff ........................................................................................................
5-V Switching Node .......................................................................................................
5-V Vo Ripple ..............................................................................................................
3.3-V Efficiency ............................................................................................................
3.3-V Load Regulation ....................................................................................................
3.3-V Enable Turnon ......................................................................................................
3.3-V Enable Turnoff ......................................................................................................
3.3-V Switching Node .....................................................................................................
3.3-V Vo Ripple ............................................................................................................
5-V/3.3-V TOP Board .....................................................................................................
5-V/3.3-V Bottom Board ..................................................................................................
1.8-V Efficiency ............................................................................................................
1.8-V Load Regulation ....................................................................................................
1.8-V Enable Turnon ......................................................................................................
1.8-V Enable Turnoff ......................................................................................................
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
© 2010, Texas Instruments Incorporated
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52
1.8-V Switching Node ..................................................................................................... 31
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1.8-V Vo Ripple ............................................................................................................ 31
54
1.05-V Efficiency ........................................................................................................... 31
55
1.05-V Load Regulation
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..................................................................................................
1.05-V Enable Turnon ....................................................................................................
1.05-V Enable Turnoff ....................................................................................................
1.05-V Switching Node ...................................................................................................
1.05-V Vo Ripple ..........................................................................................................
1.8-V/1.05-V Top Board ..................................................................................................
1.8-V/1.05-V Bottom Board ..............................................................................................
1.2-V Efficiency ............................................................................................................
1.2-V Load Regulation ....................................................................................................
1.2-V Enable Turnon ......................................................................................................
1.2-V Enable Turnoff ......................................................................................................
1.2-V Switching Node .....................................................................................................
1.2-V Vo Ripple ............................................................................................................
1.2-V Top BoardTest Condition: 12 Vin, 1.2 V/3 A, No Airflow ......................................................
TPS59610EVM-634 Top Layer Assembly Drawing, Top View ......................................................
TPS59610EVM-634 Bottom Assembly Drawing, Bottom View ......................................................
TPS59610EVM-634 Top Copper, Top View ..........................................................................
TPS59610EVM-634 Internal Layer 2, Top View ......................................................................
TPS59610EVM-634 Internal Layer 3, Top View ......................................................................
TPS59610EVM-634 Bottom Layer, Bottom View .....................................................................
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List of Tables
1
TPS59610EVM-634 Electrical Performance Specifications ........................................................... 5
2
Current-Limit Trip Selection .............................................................................................. 13
3
Frequency Selection ...................................................................................................... 13
4
Overshoot Reduction Selection .......................................................................................... 13
5
CPU VID Bits Selection ................................................................................................... 14
6
GPU VID Bits Selection
7
C4 Exit Rate Selection .................................................................................................... 14
8
Overvoltage Protection selection
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.......................................................................................
Onboard Dynamic Load Selection ......................................................................................
Enable Selection ...........................................................................................................
5-V/3.3-V Enable Selection ..............................................................................................
1.8-V/1.05-V Enable Selection ..........................................................................................
SW400(S5), SW401(S3) Enable Selection ............................................................................
1.5-V Enable Selection ...................................................................................................
1.05-V CPU C6 RAM Enable Selection ................................................................................
1.2-V Enable selection ...................................................................................................
Bill of Materials.............................................................................................................
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An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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Description
1
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Description
The TPS59610EVM-634 is designed to use a regulated 12-V (8-V to 14-V) bus to produce 10 regulated
outputs for an Atom™ E6xx Tunnel Creek Power System. The TPS59610EVM-634 is specially designed
to demonstrate the TPS59610 Atom E6xx CPU and GPU Vcore regulators while providing a number of
test points to evaluate their static and dynamic performance.
1.1
Typical Applications
•
1.2
8-V to 14-V Vin Atom E6xx Tunnel Creek Power System for embedded computing platforms
Features
The TPS59610EVM-634 features:
• Complete solution for 8-V to 14-V Vin Atom Tunnel Creek Power System
• Selectable 200/300/400/500-kHz switching frequency for CPU and GPU power
• Selectable current limit for CPU and GPU power
• Selectable output overshoot reduction ( OSR™) for CPU and GPU power
• Switches or jumpers for each output enable
• Onboard dynamic load for CPU, GPU Vcore output
• High efficiency and high density by using TI power block MOSFET
• Convenient test points for probing critical waveforms
• Four-layer printed-circuit board with 2 oz of copper on the outside layers
2
Atom Tunnel Creek Power System Block Diagram
VIN = 8 V -14 V
TI Power Block
ATOM
CPU
CORE
TPS59610
ATOM CPU CORE (5A)
5V SYSTEM (5A)
SYSTEM
5V,3.3V
TPS51120
3.3V SYSTEM (5A)
MOSFETs used
TI Power Block CSD86330Q3D
GPU
CORE
TPS59610
GPU CORE (5A)
TOPCLIFF
IOH
TPS54326
1.2V IOH CORE (3A)
LDO
TPS74801
1.8V DDR CORE (5A)
DDRII 1.8V
AND
CPU VTT
1.05V
TPS59124
1.05V
CPU VTT
(5A )
DDRII
VTT LDO
TPS51100
LDO
TPS74801
1.5V CPU
PLL (0.4A)
0.9V VTT (2A)
1.05V CPU C6
RAM (0.1A)
Figure 1. 8-V to 14-V Vin 2010 Atom Tunnel Creek Power System Block Diagram
4
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
© 2010, Texas Instruments Incorporated
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Electrical Performance Specifications
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3
Electrical Performance Specifications
Table 1. TPS59610EVM-634 Electrical Performance Specifications (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
S
8
12
14
V
10
A
5
mA
INPUT CHARACTERISTICS
VIN input voltage range
VIN
Maximum input current
VIN = 8 V, all full load
No load input current
VIN = 14 V, Io = 0 A
OUTPUT CHARACTERISTICS
CPU (TPS59610)
Output voltage Vcore
Output voltage regulation
Output voltage ripple
VID0 = VID1 = VID2 = VID4 = VID6 = 0, VID3 = VID5 = 1
1.00
Line regulation
V
0.1%
Load regulation (droop) load line
–5.7
VIN = 12 V, Io = 5 A at 300 kHz
Output load current
mΩ
30
0
Output over current
mVpp
5
A
7.2
Switching frequency
Selectable
200
Full load efficiency
VIN = 12 V, 1 V/5 A at 300 kHz
300
A
500
kHz
85.5%
GPU (TPS59610)
Output voltage Vcore
Output voltage regulation
Output voltage ripple
VID0 = VID2 = VID4 = VID5 = 0, VID1 = VID3 = 1, VID6 = 5
V
1.00
Line regulation
V
0.1%
Load regulation(droop) load line
–5.7
VIN = 12 V, Io = 5 A at 300 kHz
30
Output load current
0
Output over current
mΩ
mVpp
5
A
7.2
Switching frequency
Selectable
200
Full load efficiency
VIN = 12 V, 1 V/5 A at 300 kHz
300
A
500
kHz
86.7%
5-V AND 3.3-V SYSTEM (TPS51120)
Output voltage
Output voltage regulation
Output voltage ripple
5/3.3
Line regulation
0.1%
Load regulation
0.1%
VIN = 12 V, Io = 5 A
V
45
Output load current
0
Output over current
mVpp
5
A
10
Switching frequency
Selectable
Full load efficiency
VIN = 12 V, 5 V/5 A, 3.3 V/5 A
A
280/430
kHz
94.7/92.1%
DDR 1.8-V and 1.05-V CPU VTT (TPS59124)
Output voltage
Output voltage regulation
Output voltage ripple
1.8/1.05
Line regulation
Load regulation
1%
VIN = 12 V, Io = 5 A
30
Output load current
0
Output over current
mVpp
5
A
10
Switching frequency
Selectable
Full load efficiency
VIN = 12 V, 1.8 V/5 A, 1.05 V/5 A
(1)
V
0.1%
300/360
A
kHz
90.3/85.1%
Jumpers set to default locations, see Section 6 of this user’s guide.
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Electrical Performance Specifications
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Table 1. TPS59610EVM-634 Electrical Performance Specifications (1) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
S
1.2-V IOH(TPS54326)
Output voltage
Output voltage regulation
Output voltage ripple
1.2
Line regulation
Load regulation
1%
VIN = 12 V, 1.2 Vout, Io = 3 A
Output load current
20
0
Output over current
Switching frequency
Full load efficiency
V
0.1%
12 Vin, 1.2 V/3 A
mVpp
3
A
4.1
A
700
kHz
75.4%
1.5-V CPU PLL(TPS74801)
Output voltage
Output voltage regulation
Output voltage ripple
1.5
Line regulation
Load regulation
1%
VIN = 1.8 V,1.5 Vout, Io = 0.4 A
Output load current
V
0.1%
10
0
Output over current
mVpp
0.4
2
Switching frequency
A
N/A
Full load efficiency
A
kHz
N/A%
0.9-V VTT (TPS51100)
Output voltage
Output voltage regulation
Output voltage ripple
0.9
V
Line regulation
0.1%
Load regulation
±40
mV
10
mVpp
VIN = 1.8 V, 0.9 VTT, Io = 2 A
Output load current
0
Output over current
2
3
Switching frequency
A
N/A
Full load efficiency
A
kHz
N/A%
1.05-V CPU C6 RAM (TPS74801)
Output voltage
Output voltage regulation
Output voltage ripple
1.05
Line regulation
Load regulation
10
0
Output over current
N/A
Full load efficiency
mVpp
0.1
2
Switching frequency
A
A
kHz
N/A%
Operating temperature
6
1%
VIN = 1.8 V, 1.05 Vout, Io = 0.1 A
Output load current
V
0.1%
25
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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TP104
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TP107
© 2010, Texas Instruments Incorporated
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
7
TP103
RT101
150K
1uF
C108
C105 1
R106
6.19k
7 Bits VIDSetting
J107
R123
1
VID3_C TP129 TP130 TP131
VID2_C VID1_C VID0_C
TP128
VID4_C
THERM_C
TP113
DROOP_C ISLEW_C
TP126
VID5_C
TP127
VID6_C
VID5_C
VID4_C
VID3_C
VID2_C
VID1_C
VID0_C
VID6_C
2.00k
R110
R108 1
TP124
R109
0
AGND_C
C104
68pF
VREF_C
R104
45.3k
TP105
10.0k
R102
R115
100k
1uF
C103
R116
100k
TPS59610RHB
U101
8
J106
4
DRVH_C
TP108
C119
0.01uF
R117
10.0k
R118
10.0k
R119
10.0k
R120
10.0k
TRIPSEL: Current limit selection
C117
10uF
D101
MBR0530T
VBST_C
TP112
C110
1uF
DRVL_C
TP110
GND
DPRSLPVRand DPRSTP# setting
DPRSTP#_C
DPRSLPVR_C
R111
5.9
GND
TP118 TP117
R121
1.00k
J104
2
TP119
R122
1.00k
TP121
5
R112
3mohm
+
C111
220uF
J105
9 VR_ONEnable
TP120
OFF
TP122
S101
ON
VR_TT#_C
DPRSTP#_C TP123
PGOOD_C
C120
0.01uF
CLKEN#_C
OFF
MIN
MED
MAX
9
8
7
6
5
4
3
2
1
6
3
1
1
VCORE_C
500kHz
400kHz
300kHz
200kHz
GND
TONSEL: Frequency selection:
Jumper on pin5 and pin6 of J103: 300KHz(Default)
7 bits VIDsetting: Jumper short=High, Open=Low
Default: VID5=VID3=1, Others=0, sets 1.00Vcore
The combination of DPRSLPVRand DPRSTP# sets C4 fast exit rate:
1. No jumper on pin1 and pin2 of J106(Default)
2. Jumper on pin3 and pin4 of J106(Default)
VR_ON: Switch to ON: Enable U101, Switch to OFF: Disable U101
OSRSEL: Overshoot reduction selection:
Jumper on pin7 and pin8 of J105: MAX(Default)
(CHA)
OUTPUT:
1.00V@5A
J103
TP116
J102
TONSEL: Frequency selection
1
(CHB)
Loop Injection
Loop Injection
R107
10
C121 C122 C123
J101
R105
10
Not used
OVPdisable option:
No Jumper on JP101 and enable OVP(Default)
Loop injection and bode plot measurement
TRIPSEL: Current limit selection:
Jumper on pin3 and pin4 of J104: 7.2A(Default)
Note1:
10uF
10uF
10uF
10uF
10uF
C115 C116
C102
100pF
CSN_C
TP102
C112 C113 C114
C101
100pF
TP109
GND
TP114
GND
10uF
C107
TP106
Vin
R103
475
R101
475
OSRSEL: Overshoot reduction selection
10uF
C106
TP125
C118
1800pF
R113
1
1uH
L101
VR_ON_C
DPRSLPVR_C
8.9A
7.2A
6.0A
4.6A
LL_C
TP111
1000pF
C109
OVPSEL: OVPdisable option
R114
78.7k
JP101
CSP_C
TP101
4
PWRMON_C
TP115
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Schematics
Schematics
Figure 2. TPS59610EVM-634 Schematic, Sheet 1 of 5
7
8
0
R209
AGND
TP207
TP204
45.3k
TP203
ISLEW_G
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
© 2010, Texas Instruments Incorporated
TP227
15
VID4_G
VID3_G
VID2_G
VID1_G
VID0_G
VID3_G
VID4_G
TP226
TP230
VID0_G
R223
1
TP229
VID1_G
R215
100k
5 Bits VIDSetting
J207
VID2_G
TP213
THERM_G
RT201
150K
C208
1uF
TP205
DROOP_G
C205 1
TP228
R210
2.00k
R208 1
C204
68pF R206
6.19k
VREF_G
R204
10.0k
R202
U201
J206
12
R211
5.9
VBST_G
TP212
C217
10uF
D201
MBR0530T
C210
1uF
R217
10.0k
R218 R219 R220 R221
10.0k 10.0k 10.0k 1.00k
R222
1.00k
OFF
C220
0.01uF
S201
ON
GND
TP209
C206
10uF
C207
10uF
R212
3mohm
Vin
TP206
GND
OFF
MIN
MED
MAX
TP214
J205
C211
VR_ON_G
TP220
TP223
DPRSLPVR_G
TP201
14
1
1
OSRSEL: Overshoot reduction selection:
Jumper on pin7 and pin8 of J205: MAX(Default)
Loop injection and bode plot measurement
TRIPSEL: Current limit selection:
Jumper on pin3 and pin4 of J204: 7.2A(Default)
(CHA)
J202
GND
VCORE_G
OUTPUT:
1.00V@5A
TP216
500kHz
400kHz
300kHz
200kHz
(CHB)
Loop Injection
Loop Injection
R207
10
R205
10
7 bits VIDsetting: Jumper short=High, Open=Low
Default: VID3=VID1=1, Others=0, sets 1.00Vcore
The combination of DPRSLPVRand DPRSTP# sets C4 fast exit rate:
16 1. No jumper on pin1 and pin2 of J206(Default)
2. Jumper on pin3 and pin4 of J206(Default)
17 VR_ON: Switch to ON: Enable U201, Switch to OFF: Disable U201
15
1
J203
14 TONSEL: Frequency selection:
Jumper on pin5 and pin6 of J203: 300KHz(Default)
13
12
11
11
C222 C223
J201
TONSEL: Frequency selection
10uF 10uF
C215 C216 C221
C202
100pF
CSN_G
TP202
CSP_G
Not used
OVPdisable option:
10
No Jumper on JP201 and enable OVP(Default)
1
Note2:
10uF
C213 C214
10uF 10uF
C201
100pF
R203
475
R201
475
+ 220uF C212
OSRSEL: Overshoot reduction selection
C218
1000pF
TP224
13
1uH
L201
R213
1
LL_G
TP211
C209
1000pF
CLKEN#_G
PG_G
TP221
DPRSTP#_G
TP219
VR_TT#_G
TP225
8.9A
7.2A
6.0A
4.6A
78.7k
R214
JP201
10 OVPSEL: OVPdisable option
17 VR_ONEnable
J204
3.3VBIAS
TP222
TP208
DRVH_G
TP210
DRVL_G
GND
GND
TRIPSEL: Current limit selection
16 DPRSLPVRand DPRSTP# setting
DPRSLPVR_G
DPRSTP#_G
TPS59610RHB
R216
100k
C203
1uF
C219
0.01uF
TP218
TP217
PWRMON_G
TP215
Schematics
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Figure 3. TPS59610EVM-634 Schematic, Sheet 2 of 5
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GND
5Vout
J305
GND
GND
TP304
Vin
TP303
C310
10uF
TP309
5Vout
TP305
Vin
GND
1
21
© 2010, Texas Instruments Incorporated
+
C312
1000pF
R308
1
SW_5V
TP307
33uF
+ C305
+
R302
10.0k
Option input capacitor for hold up
+
L301
4.7uH
C304
22uF
C302
C311 +
330uF
R301
10.0k
5VEnable
J304
18
J301
C308
0.1uF
5V_BIAS
TP311
R306
2.05
R305
0
TP301
PG_5V
PwPd
SKIPSEL
TONSEL
PGOOD1
EN1
VBST1
DRVH1
LL1
DRVL1
C316
1uF
33
32
31
30
29
28
27
26
25
VREF2
TP314
VO1
TP313
C301
1000pF
U301
TPS51120RHB
COM P1
1
2
3
VFB1
4
5
VREF2
GND
6
7
VFB2
R310
3.48k
C317
10uF
5.11
R312
C318
1uF
8
9
10
11
12
13 R307
14 2.05
15
16
C319
10uF
R311
3.48k
EN5
EN3
PGOOD2
EN2
VBST2
DRVH2
LL2
DRVL2
VO2
PGND2
COM P2
24
PGND1
23
CS1
22
V IN
21
VREG5
20
V 5 F IL T
19
VREG3
18
CS2
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17
V5FILT
R303
10.0k
EN_3.3VBIAS
20 3.3V_BIASEnable
C309
0.1uF
3.3V_BIAS
TP312
TP302
PG_3.3V
TP308
C313
1000pF
Not used
C315
10uF
C307
22uF
3.3VEnable
J306
3.3Vout
GND
21
Option input capacitor for hold up
20 3.3VBIASEnable:
1. No Jumper : Always enable internal 3.3VLDOof U301 for CPUand GPUcircuit
3.3VEnable:
19 1. Jumper on(Default): Disable 3.3Vout of U301
2. No Jumper : Enable 3.3Vout of U301
GND
TP310
3.3Vout
TP306
J302
5VEnable:
18 1. Jumper on(Default): Disable 5Vout of U301
2. No Jumper : Enable 5Vout of U301
1
C306
33uF
C314+
330uF
L302
4.7uH
R309
1
Note3:
SW_3.3V
+
19
1
C303
R304
10.0k
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Schematics
Figure 4. TPS59610EVM-634 Schematic, Sheet 3 of 5
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
9
10
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
© 2010, Texas Instruments Incorporated
GND
R419
10.0k
330uF
R423
10.0k
25 1.05V_C6RAMEnable
TP407
R412
1
10
IN
OUT
9
2 IN
OUT
8
3
PG
FB
7
4
D.N.C
BIAS
6
5
GND
EN
11
1
U403
TPS74801DRC
2
3
4
5
1
PwPd
R418
7.87k
R416
6.81k
R404
75.0k
R422
7.87k
R420
2.49k
C401
10uF
R405
28.7k
U402
TPS74801DRC
10
OUT
IN
9
IN
OUT
8
FB
PG
7
BIAS
D.N.C
6
GND
EN
11
SW_1.05V
C412
1000pF
2.2uH
L402
+ C408
J406
J408
EN_1.05V_C6RAM
C423
1uF
C421
4.7uF
EN_1.5V
C417
10uF
24 1.5VEnable
C420
1uF
C418
4.7uF
GND
TP409
1.05Vout
TP408
1.05VEnable
J403
1.05Vout
22
1
C414
R414
10.0k
PwPd
J401
GND
TP413
GND
1.5Vout
3.30
R410
0
R402
VTT
PG_1.05V_C6RAM
J407
TP414
GND
GND
TP416
1.05V_C6RAM
1.05V_C6RAM
C427
10uF
C424
10uF
C428
10uF
C426
10uF
C413
1000pF
R413
1
S3, S5 control:
26 1. S0 state: S3 and S5 ON: VTTREFand VTTON
2. S3 state: S3 OFF and S5 ON, VTTREF on and VTTOFF
3. S4/S5 state: S3 and S5 OFF, VTTREF and VTTOFF
1.05_C6RAMEnable:
25 1. Jumper on(Default): Disable 1.05Vof U403
2. No Jumper : Enable 1.05Vof U403
2
3
4
5
1
Vtt_Ref_GND
TP420
Vtt_Ref
TP419
9
8
7
6
10
C416
10uF
U404
TPS51100DGQ
VDDQSNS VIN
VINLDO S5
GND
VTT
S3
PGND
VTTREF
VTTSNS
11
C406 +
330uF
2.2uH
L401
SW_1.8V
TP406
Not used
1.05VEnable:
22 1. Jumper on(Default): Disable 1.05Vout of U401
2. No Jumper: Enable 1.05Vout of U401
1.8VEnable:
23 1. Jumper on (Default): Disable 1.8Vout of U401
2. No Jumper: Enable 1.8Vout of U401
1.5VEnable:
24 1. Jumper on(Default): Disable 1.5Vof U402
2. No Jumper : Enable 1.5Vof U402
1
Note4:
VTT_GND
VTT
VTT_GND
J409
TP417
VDDQ
C411
22pF
3.48k
C410
1uF
C404
10uF
3.48k
R408
R411
C405
0.1uF
0.9VVTT/ 2A
C409
4.7uF
1.5VCPUPLL @0.4A
1.05VCPUC6 RAM@100mA
J405
TP412
1.5Vout
5V_BIAS
TP405
U401
TPS59124RGE
24
VO1 PGOOD1
23
EN1
VFB1
22
VBST1
GND
21
TONSEL DRVH1
20
LL1
VFB2
19
DRVL1
VO2
18
PGOOD2 PGND1
17
TRIP1
EN2
16
VBST2
V5IN
15
DRVH2 V5FILT
14
TRIP2
LL2
13
DRVL2 PGND2
PwPd
100k
R401
C403
10uF
PG_1.5V
C422
4.7uF
C419
4.7uF
R409
0
1
2
3
4
5
6
7
8
9
10
11
12
TP401
PG_1.8V
TP418
TP415
R421
100k
TP402
PG_1.05V
TP410
R417
100k
C407
0.1uF
R407
100k
75.0k
R406
102k
R403
C402
10uF
SW401
S3
SW400
S5
C425
4.7uF
TP404
GND
J404
TP403
1.8Vout
1.8VEnable
GND
1.8Vout
J402
26 S3 and S5 Control
C429
0.1uF
23
1
C415
R415
10.0k
1.8V@5A
Schematics
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Figure 5. TPS59610EVM-634 Schematic, Sheet 4 of 5
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R513
100k
R511
8.06k
R503
10.0k
R502
5.62k
R501
68.1
C508
0.01uF
C501
1uF
D501
BAT54
R512
10.0k
C509
1uF
EN_1.2V
TP504
PG_1.2V
TP503
C502
0.01uF
GND
TP502
17 16 15 14 13
R504
100k
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
28
R508
10.0k
R507
10.0k
9
12
11
10
J501
TP505
1
R506
1
C506
SW_1.2V
SW501
OFF
ON
U504A:A
SN74HC08D
SW502
GPUDyn Load
OFF
CPUDyn. Load
ON
27 1.2VEnable
C505
0.1uF
On Board Dynamic Load
C510
0.1uF
TP508
DL_CLK
C504
22nF
5 6 7 8
R505
10.0k
1
VBST
VFB
2
VREG5 U501
SW
3
SS TPS54326RGT SW
4
SW
GND
C503
22uF
P w rP d
Vin
VO
VCC
V IN
V IN
PG
EN
PGND
PGND
TP501
U504D:D
U504C:C
U504B:B
L501
1.5uH
C513
1uF
C507
47uF
U503
UCC37324DR
C511
1uF
J502
R509
330
D502
GREEN
GND
TP507
1.2Vout
GND
1.2V
TP506
R510
330
D503
GREEN
100
R515
100
R514
1
C512
R516
0.001
Q501
CSD16407Q5
R518
0.100
R517
0.100
1
C514
R521
0.001
R520
0.100
R519
0.100
Q502
CSD16407Q5
28 On Board Dynamic Load:
1. SW501: ONEnable CPUCore Dynamic load
OFFDisable CPUCore Dynamic load
2. SW502: ONEnable CPUCore Dynamic load
OFFDisable GPUCore Dynamic load
27
1.2VEnable:
1. Jumper on(Default): Disable 1.2Vof U501
2. No Jumper : Enable 1.2Vof U501
Not used
Note5:
1
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Schematics
Figure 6. TPS59610EVM-634 Schematic, Sheet 5 of 5
11
Test Setup
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5
Test Setup
5.1
Test Equipment
Voltage Source VIN: The input voltage source VIN must be a 0-V to 14-V variable dc source capable of
supplying 10 Adc. Connect VIN to J304 as shown in Figure 7.
Multimeters:
V1: Vin at TP303 (VIN) and TP304 (GND)
V2: Vout at each output test point. For example: CPU at J101
A1: Vin input current
Output Load: The output load must be an electronic constant resistance mode load capable of 0 Adc to
10 Adc.
Oscilloscope: A digital or analog oscilloscope can be used to measure the output ripple. The oscilloscope
must be set for 1-MΩ impedance, 20-MHz bandwidth, ac coupling, 2-µs/division horizontal resolution,
50-mV/division vertical resolution. Test points on each output can be used to measure the output ripple
voltage. Do not use a leaded ground connection as this may induce additional noise due to the large
ground loop.
Recommended Wire Gauge:
1. VIN to J304 (12-V input):
The recommended wire size is AWG 16 per input connection, with the total length of wire less than 4
feet (2-foot input, 2-foot return).
2. Each outputs to LOAD:
The minimum recommended wire size is AWG 16, with the total length of wire less than 4 feet (2-foot
output, 2-foot return)
5.2
Recommended Test Setup
DC
Source
VIN
+
-
1.05VC6
1.5V
0.9V
1.8V
1.05V
5V
3.3V
CPU
V2
+
GPU
+
1.2V
V1
+
-
-
-
A1
Load
Figure 7. TPS59610EVM-634 Recommended Test Setup
Figure 7 is the recommended test setup to evaluate the TPS59610EVM-634. Working at an ESD
workstation, ensure that wrist straps, bootstraps, or mats are connected referencing the user to earth
ground before handling the EVM.
12
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Input Connections:
1. Prior to connecting the dc input source VIN, it is advisable to limit the source current from VIN to 10 A
maximum. Ensure that VIN is initially set to 0 V and connected as shown in Figure 7.
2. Connect a voltmeter V1 at TP303 (VIN) and TP304 (GND) to measure VIN input voltage.
3. Connect a current meter A1 between VIN dc source and J304.
Output Connections (For example, CPU testing)
1. Connect the load to J102, and set the load to constant resistance mode to sink 0 Adc before VIN is
applied.
2. Connect a voltmeter V2 at J101 to measure CPU 1-Vcore voltage as shown in Figure 7.
6
Configuration
All jumper selections must be made prior to applying power to the EVM. Users can configure this EVM per
the following configurations.
6.1
6.1.1
CPU and GPU Configuration
Current-Limit Trip Selection (J104 for CPU and J204 for GPU)
The current-limit trip can be set by J104 and J204 TRIPSEL.
Default setting: 7.2 A.
Table 2. Current-Limit Trip Selection
6.1.2
Jumper set to
TRIPSEL
OCP Limit, Typ. (A)
Top (1-2 pin shorted)
5VFILT
8.9
Second (3-4 pin shorted)
3.3VBIAS
7.2
Third (5-6 pin shorted)
VREF
6
Bottom (7-8 pin shorted)
GND
4.6
Frequency Selection (J103 for CPU and J203 for GPU)
The operating frequency can be set by J103 and J203 TONSEL.
Default setting: 300 kHz.
Table 3. Frequency Selection
6.1.3
Jumper set to
TONSEL
Frequency (kHz)
Top (1-2 pin shorted)
5VFILT
500
Second (3-4 pin shorted)
3.3VBIAS
400
Third (5-6 pin shorted)
VREF
300
Bottom (7-8 pin shorted)
GND
200
Overshoot Reduction Selection (J105 for CPU and J205 for GPU)
The overshoot reduction can be set by J105 and J205 OSRSEL.
Default setting: Maximum
Table 4. Overshoot Reduction Selection
Jumper set to
OSR
Overshoot Voltage Reduction
Top(1-2 pin shorted)
5VFILT
OFF
Second (3-4 pin shorted)
3.3VBIAS
Minimum
Third (5-6 pin shorted)
VREF
Medium
Bottom (7-8 pin shorted)
GND
Maximum
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Configuration
6.1.4
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VID Bits Selection
The CPU Vcore voltage can be set by J107( 7-Bit CPU VID).
Default setting: 0101000 for 1.000V
Jumper = 1
No Jumper = 0
Table 5. CPU VID Bits Selection
7-Bit VID Table (1 = 1.05 V, 0 = GND)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vcore(V)
0
0
0
0
0
0
0
1.500
0
0
1
1
0
0
0
1.200
0
1
0
1
0
0
0
1.000
0
1
1
1
0
0
0
0.800
1
0
0
1
0
0
0
0.600
1
0
1
1
0
0
0
0.400
1
1
0
0
0
0
0
0.300
See data sheet for details.
The GPU Vcore voltage can be set by J207 (5-bit GPU VID).
Default setting: 01010 for 1.000V
Table 6. GPU VID Bits Selection
5-Bit VID Table (1 = 1.05 V, 0 = GND)
VID4
VID3
VID2
VID1
VID0
Vcore(V)
0
0
0
0
0
1.250
0
0
1
1
0
1.100
0
1
0
1
0
1.000
1
0
0
1
0
0.800
1
1
0
1
0
0.600
1
1
1
1
1
0.400
See data sheet for details.
6.1.5
Deep Sleep Mode Selection (DPRSLPVR)
The combination of DPRSTP# and DPRSLPVR sets C4 exit rate. These can be set by J106 for CPU and
J206 for GPU.
Default setting: Jumper on DPRSLPVR and no jumper on DPRSTP# of J106 and J206
Table 7. C4 Exit Rate Selection
6.1.6
Jumper set to
C4 exit rate
Jumper on DPRSLPVR
No jumper on DPRSTP#
C4 exit fast
No jumper on DPRSLPVR
No jumper on DPRSTP#
C4 exit slow
Overvoltage Protection Selection (JP101 for CPU and JP201 for GPU)
The overvoltage protection selection can be set by JP101 and JP201, OVPSEL
Default setting: No jumper shorts on JP101 and JP201 to enable OVP
14
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Table 8. Overvoltage Protection selection
Jumper set to
6.1.7
Selection
No jumper
OVP enabled
Jumper shorted
OVP disabled
Onboard Dynamic Load Selection (SW501 for CPU and SW502 for GPU)
The onboard dynamic load can be set by SW501 and SW502.
Default setting: Push SW501 and SW502 to the right to disable the onboard dynamic load.
Table 9. Onboard Dynamic Load Selection
6.1.8
Switch set to
Dynamic Load Selection
Push SW501 to left (On position)
Enable 5-A onboard dynamic load at CPU
Push SW501 to right (Off position)
Disable 5-A onboard dynamic load at CPU
Push SW502 to left (On position)
Enable 5-A onboard dynamic load at GPU
Push SW502 to right (Off position)
Disable 5-A onboard dynamic load at GPU
Enable Selection (S101 for CPU and S201 for GPU)
The Vcore of CPU and GPU can be enabled and disabled by S101 and S201.
Default setting: Push S101 and S201 to the TOP(Off position) to disable both CPU and GPU
Table 10. Enable Selection
6.2
6.2.1
Switch set to
Dynamic Load Selection
Push S101 to bottom (On position)
Enable CPU Vcore
Push S101 to top (Off position)
Disable CPU Vcore
Push S201 to bottom (On position)
Enable GPU Vcore
Push S201 to top (Off position)
Disable GPU Vcore
5-V/3.3-V System Configuration
3.3VBIAS Enable Selection (J303)
3.3VBIAS Enable can be set by J303, EN_3.3VBIAS
Default setting: No Jumper shorts on J303 to enable the 3.3VBIAS
Note: 3.3VBIAS needs to always be enabled for CPU and GPU circuit
6.2.2
5-V/3.3-V Enable Selection (J301 for 5 V and J302 for 3.3 V)
5-V/3.3-V Enable can be set by J301 and J302, EN_5V and EN_3.3V
Default setting: Jumper shorts on J301 and J302 to disable 5 V/3.3 V.
Table 11. 5-V/3.3-V Enable Selection
6.3
6.3.1
Jumper set to
Selection
Jumper on J301
5-V Disabled
No jumper on J301
5-V Enabled
Jumper on J302
3.3-V Disabled
No jumper on J302
3.3-V Enabled
DDR 1.8-V/1.05-V CPU VTT Configuration
1.8-V/1.05-V Enable can be set by J402 for 1.8 V and J401 for 1.05 V, EN_1.8V and EN_1.05V
Default setting: Jumper shorts on J402 to disable 1.8 V. No Jumper on J401 to enable 1.05 V
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Configuration
www.ti.com
Note: 1.05V enable is for VID setting of CPU and GPU
Table 12. 1.8-V/1.05-V Enable Selection
6.4
6.4.1
Jumper set to
Selection
Jumper on J402
1.8V Disabled
No Jumper on J402
1.8V Enabled
Jumper on J401
1.05V Disabled
No Jumper on J401
1.05V Enabled
0.9-V VTT and 0.9-V VTTREF Configuration
0.9-V VTT and 0.9-V VTTREF Enable Selection (SW401 for S3, SW400 for S5)
Default setting: Push SW400 and SW401 to bottom to disable both 0.9VTT and 0.9VTTREF.
Table 13. SW400(S5), SW401(S3) Enable Selection
6.5
6.5.1
State
SW401 set to
SW400 set to
VTT, VTTREF
S0
S3 Top(on)
S5 Top(on)
VTT and VTTREF on
S3
S3 Bottom(off)
S5 Top(on)
VTT off and VTTREF on
S4/S5
S3 Bottom(off)
S5 Bottom(off)
VTT and VTTREF off
1.5-V CPU PLL Configuration
1.5-V Enable Selection (J406)
1.5-V Enable can be set by J406, EN_1.5V
Default setting: Jumper shorts on J406 to disable 1.5 V
Table 14. 1.5-V Enable Selection
6.6
6.6.1
Jumper set to
Selection
No Jumper
1.5V Enabled
Jumper on
1.5V Disabled
1.05-V CPU C6 RAM Configuration
1.05-V CPU C6 RAM Enable Selection (J408)
1.05-V Enable can be set by J408, EN_1.05V_C6RAM
Default setting: Jumper shorts on J408 to disable 1.05-V CPU C6 RAM
Table 15. 1.05-V CPU C6 RAM Enable Selection
Jumper set to
16
Selection
No Jumper
1.05V CPU R6 RAM Enabled
Jumper on
1.05V CPU C6 RAM Disabled
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Test Procedure
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6.7
6.7.1
1.2-V IOH Configuration
1.2-V Enable Selection (J501)
1.2-V Enable can be set by J501, EN_1.2V
Default setting: Jumper shorts on J501 to disable 1.2 V
Table 16. 1.2-V Enable selection
Jumper set to
Selection
No Jumper
1.2V Enabled
Jumper on
1.2V Disabled
7
Test Procedure
7.1
Line/Load Regulation and Efficiency Measurement Procedure
The CPU measurement is performed in the following manner.
1. Set up EVM as described in Section 5.1 and Figure 7.
2. Ensure that the Load is set to constant resistance mode and sink 0 A.
3. Ensure that all the jumper configuration settings are per Section 6
4. Ensure that the S101 VR_ON enable switch is set to OFF before VIN is applied.
5. Increase VIN from 0 V to 12 V. Use V1 to measure VIN voltage.
6. Set switch S101 to ON to enable the controller.
7. Use V2 to measure Vcore_c voltage.
8. Vary Load from 0 Adc to 5 Adc; Vcore_c must remain in load regulation.
9. Vary VIN from 8 V to 14 V; Vcore_c must remain in line regulation.
10. Set switch S101 to OFF to disable the controller.
11. Decrease Load to 0 A.
12. Decrease VIN to 0 V.
Other output testing is the same.
7.2
Onboard Transient Response Measurement
CPU and GPU Only
1. Set up EVM as described in Section 5.1 and Figure 7.
2. Ensure that all the jumper configuration settings are per Section 6
3. Remove the load from J102 for CPU or J202 for GPU
4. Ensure that VR_ON (S101 for CPU and S201 for GPU) is on OFF before VIN is applied.
5. Increase VIN from 0 V to 12 V. Use V1 to measure VIN voltage.
6. Use TP508 (DL_CLK) and TP209 (GND) to measure transient timing signal.
7. Push switch SW501 (CPU) or SW502 (GPU) to ON position (left), and dynamic load LED D503 for
CPU and D502 for GPU illuminate.
8. Measure the Vcore_c or Vcore_G transient response by using TP116 (CPU) or TP216 (GPU).
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Test Procedure
7.3
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Loop Gain/Phase Measurement
CPU and GPU Only
1. Set up EVM as described in Section 5.1 and Figure 7.
2. CPU: Connect the isolation transformer to VSNS of J101 (CPU) and Vcore_C (+)(CPU) of J102.
GPU: Connect the isolation transformer to VSNS of J201 (GPU) and Vcore_G (+)(GPU) of J202
3. CPU: Connect input signal CHA to VSNS pin of J101 and connect output signal CHB to Vcore_C(+) of
J102.
GPU: Connect input signal CHA to VSNS pin of J201, and connect output signal CHB to Vcore_G(+) of
J202.
4. Connect the GND lead of CHA and CHB to GND of TP116 (CPU) and TP216 (GPU).
5. Inject around 50-mV or less signal through the isolate transformer.
6. Sweep the frequency from 100 Hz to 1 MHz with 10-Hz or lower post filter. The control loop gain and
phase margin can be measured.
7. Disconnect isolate transformer from the bode plot setup before making other measurements (signal
injection into feedback may interfere with accuracy of other measurement).
7.4
Equipment Shutdown
1. Shut down Load.
2. Shut down VIN.
18
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Performance Data and Typical Characteristic Curves
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8
Performance Data and Typical Characteristic Curves
Figure 8 through Figure 68 present typical performance curves for TPS59610EVM-634.
Jumpers set to default locations; see Section 6 of this user’s guide
8.1
CPU
100
1.04
VI = 12 V
90
VI = 8 V
1.02
VO - Output Voltage - V
80
Efficiency - %
70
VI = 14 V
60
50
40
30
VI = 12 V
VI = 8 V
SPEC_nom
SPEC_max
1
0.98
VI = 14 V
0.96
20
SPEC_min
10
0.94
0
0.001
0.01
0.1
1
IO - Output Current - A
Figure 8. CPU Efficiency
TPS9610EVM-634 CPU
Enable Start Up
10
0
0.5
1
1.5 2
2.5 3
3.5
IO - Output Current - A
4
4.5
5
Figure 9. CPU Load Regulation
TPS9610EVM-634 CPU
Enable Shut Down
Test Condition: 12 Vin, 1 V/5 A
Test Condition: 12 Vin, 1 V/5 A
CH1: VR_ON
CH1: VR_ON
CH2: 1 Vcore
CH2: 1 Vcore
CH3: PGOOD
CH3: PGOOD
CH4: CLKEN#
CH4: CLKEN#
Figure 10. CPU Enable Turnon
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Figure 11. Enable Turnoff
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Performance Data and Typical Characteristic Curves
TPS9610EVM-634 CPU
Switching Node
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TPS9610EVM-634 CPU
Output Ripple
Test Condition: 12 Vin, 1 V/5 A
Test Condition: 12 Vin, 1 V/5 A
CH1: LL_C
CH1: 1 Vcore Output Ripple
Figure 13. CPU Vcore Ripple
Figure 12. CPU Switching Node
TPS9610EVM-634 CPU
Over Shoot Reduction (OSR)
CH1: 1 Vcore
Test Condition: 12 Vin, 1 V/5 A-0 A
Load Release
TPS9610EVM-634 CPU
Over Shoot Reduction (OSR)
OSR = OFF
Test Condition: 12 Vin, 1 V/5 A-0 A
Load Release
OSR = MAX
CH1: 1 Vcore
CH2: DRVL_C
CH2: DRVL_C
CH3: LL_C
CH3: LL_C
Figure 14. CPU Output Load Release
Without Overshoot Reduction
20
Figure 15. CPU Output Load Release
With Maximum Overshoot Reduction
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TPS9610EVM-634 CPU
Output Transient
TPS9610EVM-634 CPU
Output Transient
Test Condition: 12 Vin, 1 V/0.04 A-5 A Transient
CH1: 1 V core Output
Test Condition: 12 Vin, 1 V/0.04 A-5 A Transient
CH1: 1 V core Output
CH3: LL
CH3: LL
CH4: 1 Vcore Output Current
CH4: 1 Vcore Output Current
Figure 16. CPU Transient From DCM to CCM
Figure 17. CPU Transient From CCM to DCM
Figure 18. CPU Bode Plot 12 Vin, 1 V/5 A
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Performance Data and Typical Characteristic Curves
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TPS59610
Figure 19. CPU Top Board
Figure 20. CPU Bottom Board
Test condition: 12 Vin, 1 V/5 A, no airflow
22
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8.2
GPU
100
90
VI = 12 V
VI = 8 V
1.04
80
Efficiency - %
VO - Output Voltage - V
SPEC_max
70
VI = 14 V
60
50
40
30
1.02
VI = 14 V
VI = 8 V
1
SPEC_nom
20
SPEC_min
VI = 12 V
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
0.98
0
0.5
1
1.5 2
2.5 3
3.5
IO - Output Current - A
4
4.5
5
NOTE: Intel spec calls for 3% offset
at the VID setting
Figure 21. CPU Efficiency
Figure 22. GPU Load Regulation
TPS9610EVM-634 GPU
Enable Start Up
Test Condition: 12 Vin, 1 V/5 A
TPS9610EVM-634 GPU
Enable Shut Down
CH1: VR_ON
CH1: VR_ON
CH2: 1 Vcore
CH2: 1 Vcore
CH3: PGOOD
CH3: PGOOD
CH4: CLKEN#
CH4: CLKEN#
Figure 23. GPU Enable Turnon
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Test Condition: 12 Vin, 1 V/5 A
Figure 24. GPU Enable Turnoff
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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23
Performance Data and Typical Characteristic Curves
TPS9610EVM-634 GPU
Switching Node
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TPS9610EVM-634 GPU
Output Ripple
Test Condition: 12 Vin, 1 V/5 A
Test Condition: 12 Vin, 1 V/5 A
CH1: LL_G
1 Vcore Output Ripple
Figure 25. GPU Switching Node
TPS9610EVM-634 GPU
Over Shoot Reduction (OSR)
Test Condition: 12 Vin, 1 V/5 A-0A
Load Release
Figure 26. GPU Vcore Ripple
TPS9610EVM-634 GPU
Over Shoot Reduction (OSR)
OSR = MAX
OSR = OFF
CH1: 1 Vcore
CH1: 1 Vcore
CH2: DRVL_G
CH2: 1 DRVL_G
CH3: LL_G
CH3: LL_G
Figure 27. GPU Output Load Release
Without Overshoot Reduction
24
Test Condition: 12 Vin, 1 V/5 A-0A
Load Release
Figure 28. GPU Output Load Release
With Maximum Overshoot Reduction
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TPS9610EVM-634 GPU
Output Transient: OSR max
TPS9610EVM-634 GPU
Output Transient
Test Condition: 12 Vin, 1 V/0 A-5 A Transient
Test Condition: 12 Vin, 1 V/0 A-5 A Transient
CH1: 1 Vcore
CH2: 1 Vcore
CH3: LL
CH3: LL
CH4: 1 Vcore Output Current
CH4: 1 Vcore Output Current
Figure 29. GPU Transient From DCM to CCM
Figure 30. GPU Transient From CCM to DCM
Figure 31. GPU Bode Plot 12 Vin, 1 V/5 A
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Performance Data and Typical Characteristic Curves
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CSD86330Q3
TPS59610
Figure 33. CPU Bottom Board
Figure 32. CPU Top Board
Test condition: 12 Vin, 1 V/5 A, no airflow
8.3
5-V/3.3-V System
5.6
100
VI = 8 V
90
80
VI = 12 V
5.4
VI = 14 V
VO - Output Voltage - V
Efficiency - %
70
60
50
40
30
20
5.2
VI = 12 V
VI = 14 V
5
VI = 8 V
4.8
4.6
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
Figure 34. 5-V Efficiency
26
4.4
0
1
2
3
IO - Output Current - A
4
5
Figure 35. 5-V Load Regulation
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TPS9610EVM-634 5 V
Enable Start Up
Test Condition: 12 Vin, 5 V/5 A
TPS9610EVM-634 5 V
Enable Shut Down
Test Condition: 12 Vin, 5 V/5 A
CH1: EN_5 V
CH1: EN_5 V
CH2: 5 Vout
CH2: 5 Vout
CH3: PG_5 V
CH3: PG_5 V
Figure 36. 5-V Enable Turnon
TPS9610EVM-634 5 V
Switching Node
Figure 37. 5-V Enable Turnoff
TPS9610EVM-634 5 V
Output Ripple
Test Condition: 12 Vin, 5 V/5 A
Test Condition: 12 Vin, 5 V/5 A
CH1: 5 V Output Ripple
CH1: SW_5 V
Figure 38. 5-V Switching Node
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Figure 39. 5-V Vo Ripple
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Performance Data and Typical Characteristic Curves
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3.35
100
VI = 8 V
90
80
VI = 12 V
VO - Output Voltage - V
Efficiency - %
70
VI = 14 V
60
50
40
30
VI = 14 V
VI = 12 V
3.3
VI = 8 V
3.25
20
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
Figure 40. 3.3-V Efficiency
TPS9610EVM-634 3.3 V
Enable Start Up
Test Condition: 12 Vin, 3.3 V/5 A
3.2
0
1
2
3
IO - Output Current - A
4
5
Figure 41. 3.3-V Load Regulation
TPS9610EVM-634 3.3 V
Enable Shut Down
Test Condition: 12 Vin, 3.3 V/5 A
CH1: EN_3.3 V
CH1: EN_3.3 V
CH2: 3.3 Vout
CH2: 3.3 Vout
CH3: PG_3.3 V
CH3: PG_3.3 V
Figure 42. 3.3-V Enable Turnon
28
Figure 43. 3.3-V Enable Turnoff
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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TPS9610EVM-634 3.3 V
Switching Node
TPS9610EVM-634 3.3 V
Output Ripple
Test Condition: 12 Vin, 3.3 V/5 A
Test Condition: 12 Vin, 3.3 V/5 A
CH1: 3.3 V Output Ripple
CH1: SW_3.3 V
Figure 45. 3.3-V Vo Ripple
Figure 44. 3.3-V Switching Node
TPS51120
Figure 46. 5-V/3.3-V TOP Board
Figure 47. 5-V/3.3-V Bottom Board
Test condition: 12 Vin, 5 V/5 A and 3.3 V/5 A, no airflow
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Performance Data and Typical Characteristic Curves
8.4
www.ti.com
1.8-V DDR/1.05-V CPU VTT
100
1.95
VI = 12 V
VI = 8 V
90
1.9
80
VI = 14 V
VO - Output Voltage - V
Efficiency - %
70
60
50
40
30
20
VI = 12 V
1.85
VI = 14 V
1.8
VI = 8 V
1.75
1.7
10
0
0.001
1.65
0.01
0.1
1
IO - Output Current - A
10
Figure 48. 1.8-V Efficiency
TPS9610EVM-634 1.8 V
Enable Start Up
0
1
2
3
IO - Output Current - A
4
5
Figure 49. 1.8-V Load Regulation
Test Condition: 12 Vin, 1.8 V/5 A
TPS9610EVM-634 1.8 V
Enable Shut Down
Test Condition: 12 Vin, 1.8 V/5 A
CH1: EN_1.8 V
CH1: EN_1.8 V
CH2: 1.8 Vout
CH2: 1.8 Vout
CH3: PG_1.8 V
CH3: PG_1.8 V
Figure 50. 1.8-V Enable Turnon
30
Figure 51. 1.8-V Enable Turnoff
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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TPS9610EVM-634 1.8 V
Switching Node
TPS9610EVM-634 1.8 V
Output Ripple
Test Condition: 12 Vin, 1.8 V/5 A
Test Condition: 12 Vin, 1.8 V/5 A
CH1: 1.8 V Output Ripple
CH1: SW_1.8 V
Figure 52. 1.8-V Switching Node
Figure 53. 1.8-V Vo Ripple
1.1
100
90
VI = 12 V
VI = 8 V
80
VO - Output Voltage - V
1.08
Efficiency - %
70
VI = 14 V
60
50
40
30
20
VI = 14 V
1.06
VI = 12 V
VI = 8 V
1.04
1.02
10
0
0.001
1
0.01
0.1
1
IO - Output Current - A
Figure 54. 1.05-V Efficiency
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10
0
1
2
3
IO - Output Current - A
4
5
Figure 55. 1.05-V Load Regulation
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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31
Performance Data and Typical Characteristic Curves
TPS9610EVM-634 1.05 V
Enable Start Up
TestCondition:
Condition:12
12Vin,
Vin,1.05
1.05V/5
V/5AA
Test
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TPS9610EVM-634 1.05 V
Enable Shut Down
Test Condition: 12 Vin, 1.05 V/5 A
CH1: EN_1.05 V
CH1: EN_1.05 V
CH2: 1.05 Vout
CH2: 1.05 Vout
CH3: PG_1.05 V
CH3: PG_1.05 V
Figure 56. 1.05-V Enable Turnon
TPS9610EVM-634 1.05 V
Switching Node
Test Condition: 12 Vin, 1.05 V/5 A
Figure 57. 1.05-V Enable Turnoff
TPS9610EVM-634 1.05 V
Output Ripple
Test Condition: 12 Vin, 1.05 V/5 A
CH1: SW_1.05 V
CH1: 1.05 V Output Ripple
Figure 58. 1.05-V Switching Node
32
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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Figure 59. 1.05-V Vo Ripple
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TPS59124
CSD86330Q3D
Figure 60. 1.8-V/1.05-V Top Board
Figure 61. 1.8-V/1.05-V Bottom Board
Test condition: 12 Vin, 1.8 V/5 A and 1.05 V/5 A, no airflow
8.5
1.2-V IOH
1.3
100
90
VI = 8 V
VI = 12 V
1.28
80
VO - Output Voltage - V
1.26
Efficiency - %
70
VI = 14 V
60
50
40
30
1.24
VI = 14 V
1.22
1.2
VI = 8 V
1.18
1.16
20
1.14
10
1.12
0
0.001
VI = 12 V
1.1
0.01
0.1
1
IO - Output Current - A
Figure 62. 1.2-V Efficiency
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10
0
0.5
1
1.5
2
IO - Output Current - A
2.5
3
Figure 63. 1.2-V Load Regulation
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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33
Performance Data and Typical Characteristic Curves
TPS9610EVM-634 1.2 V IOH Core
Enable Start Up
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Test Condition: 12 Vin, 1.2 V/3 A
TPS9610EVM-634 1.2 IOH Core
Enable Shut Down
CH1: EN_1.2 V
CH1: EN_1.2 V
CH2: 1.2 Vout
CH2: 1.2 Vout
CH3: PG_1.2 V
CH3: PG_1.2 V
Figure 64. 1.2-V Enable Turnon
TPS9610EVM-634 1.2 V
Switching Node
Test Condition: 12 Vin, 1.2 V/3 A
Test Condition: 12 Vin, 1.2 V/3 A
Figure 65. 1.2-V Enable Turnoff
TPS9610EVM-634 1.2 V IOH
Output Ripple
CH1: 1.2 V Switching Node
Test Condition: 12 Vin, 1.2 V/3 A
CH1: 1.2 V Output Ripple
Figure 66. 1.2-V Switching Node
Figure 67. 1.2-V Vo Ripple
TPS54326
Figure 68. 1.2-V Top Board
Test Condition: 12 Vin, 1.2 V/3 A, No Airflow
34
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EVM Assembly Drawings and PCB Layout
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9
EVM Assembly Drawings and PCB Layout
The following figures (Figure 69 through Figure 74) show the design of the TPS59610EVM-634 printed
circuit board. The EVM has been designed using 4 Layers circuit board with 2oz copper on outside layers.
Figure 69. TPS59610EVM-634 Top Layer Assembly Drawing, Top View
Figure 70. TPS59610EVM-634 Bottom Assembly Drawing, Bottom View
Figure 71. TPS59610EVM-634 Top Copper, Top View
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EVM Assembly Drawings and PCB Layout
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`
Figure 72. TPS59610EVM-634 Internal Layer 2, Top View
Figure 73. TPS59610EVM-634 Internal Layer 3, Top View
Figure 74. TPS59610EVM-634 Bottom Layer, Bottom View
36
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
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Bill of Materials
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10
Bill of Materials
Table 17 shows the EVM major components list according to the schematic shown in Figure 2 through
Figure 6.
Table 17. Bill of Materials
Qty
RefDes
Description
MFR
Part Number
3
C1, C2, C3
Capacitor, Aluminum, 330uF, 16V, 20%, –40-85°C
Panasonic-ECG
ECA-1CM331B
4
C101, C102, C201, C202
Capacitor, Ceramic, 100pF, 50V, C0G, 10%, 0603
STD
STD
6
C103, C108, C110, C203,
C208, C210
Capacitor, Ceramic, 1uF, 16V, X7R, 20%, 0603
STD
STD
2
C104, C204
Capacitor, Ceramic, 68pF, 50V, C0G, 10%, 0603
STD
STD
8
C106, C107, C206, C207,
C401– C404
Capacitor, Ceramic, 10uF, 25V, X5R, 20%, 1206
STD
STD
3
C109, C209, C301
Capacitor, Ceramic, 1000pF, 50V, X7R, 20%, 0402
STD
STD
2
C111, C211
Capacitor, Aluminum, 220uF, 2V, 20%, 9mohm, 7343
Panasonic-ECG
EEF-SX0D221R
20
C112–C116, C212–C216,
C310, C315, C317, C319,
C416, C417, C424,
C426–C428,
Capacitor, Ceramic, 10uF, 6.3V, X5R, 20%, 0805
STD
STD
2
C117, C217
Capacitor, Ceramic, 10uF, 6.3V, X5R, 20%, 0603
STD
STD
1
C118
Capacitor, Ceramic, 1800pF, 50V, X7R, 20%, 0805
STD
STD
5
C119, C120, C219, C220, C502
Capacitor, Ceramic, 0.01uF, 50V, X7R, 20%, 0603
STD
STD
5
C218, C312, C313, C412, C413
Capacitor, Ceramic, 1000pF, 50V, X7R, 20%, 0805
STD
STD
3
C304, C307, C503
Capacitor, Ceramic, 22uF, 16V, X5R, 20%, 1210
STD
STD
2
C305, C306
Capacitor, Tant cap, 33uF, 16V, 0.045ohms, 20%, 7343D
KEMET
T520V336M016ATE045
3
C308, C309, C510
Capacitor, Ceramic, 0.1uF, 16V, X7R, 20%, 0402
STD
STD
2
C311, C314
Capacitor, Tant cap, 330uF, 6.3V, 0.010ohms, 20%, 7343D
KEMET
T530D337M006ATE010
2
C316, C318
Capacitor, Ceramic, 1uF, 16V, X5R, 20%, 0402
STD
STD
4
C405, C407, C429, C505
Capacitor, Ceramic, 0.1uF, 25V, X7R, 20%, 0603
STD
STD
2
C406, C408
Capacitor, SP cap, 330uF, 2.5V, 0.015ohms, 20%, 7343D
Panasonic-ECG
EEF-CX0E331R
1
C409
Capacitor, Ceramic, 4.7uF, 10V, X5R, 20%, 0603
STD
STD
7
C410, C420, C423, C501,
C509, C511, C513
Capacitor, Ceramic, 1uF, 16V, X7R, 20%, 0603
STD
STD
1
C411
Capacitor, Ceramic, 22pF, 50V, C0G, 20%, 0603
STD
STD
4
C418, C419, C421, C422
Capacitor, Ceramic, 4.7uF, 6.3V, X5R, 20%, 0603
STD
STD
1
C425
Capacitor, Ceramic, 4.7uF, 6.3V, X5R, 20%, 0805
STD
STD
1
C504
Capacitor, Ceramic, 22nF, 16V, X7R, 20%, 0603
STD
STD
1
C507
Capacitor, Ceramic, 47uF, 6.3V, X5R, 20%, 1210
STD
STD
1
C508
Capacitor, Ceramic, 0.01uF, 25V, X7R, 20%, 0402
STD
STD
2
D101, D201
Diode, Schottky, 0.5A, 30V, SOD-123,
On Semi
MBR0530T
1
D501
Diode, Schottky, 200mA, 30V, SOT-23,
Vishay-Liteon
BAT54-V-GS08
2
D502, D503
Diode, LED, Green Clear, 20mcd, 0.079x0.049
Lite On
LTST-C170GKT
2
L101, L201
Inductor, SMT, 1uH, 11.1A , 7.81mohm, 0.256" x 0.280"
TDK
SPM6530T-1R0M120
2
L301, L302
Inductor, SMT, 4.7uH, 6.0A, 25mohm, 6.8mm x 6.8mm
Coiltronics
HCP0704-4R7-R
2
L401, L402
Inductor, SMT, 2.2uH, 10A, 13.6mohm, 0.255" x 0.270"
Vishay
IHLP2525EZER2R2M01
1
L501
Inductor, SMT, 1.5uH, 5.5A, 40.4mohm, 0.204" x 0.216"
Vishay
IHLP2020CZER1R5M11
6
Q101, Q201, Q301,Q302,
Q401, Q402
MOSFET, Synchronous Buck NexFET Power Block SON 3.3 x
3.3mm
TI
CSD86330Q3D
2
Q501, Q502
MOSFET, Nchan, 25V, 31A, 2.5mohm, QFN5X6mm
TI
CSD16407Q5
4
R101, R103, R201, R203
Resistor, Chip, 475, 1/16W, 1%, 0402
STD
STD
15
R102, R117–R120, R202,
R217–R220, R503, R505,
R507, R508, R512
Resistor, Chip, 10k, 1/16W, 1%, 0603
STD
STD
2
R104, R204
Resistor, Chip, 45.3k, 1/16W, 1%, 0603
STD
STD
4
R105, R107, R205, R207
Resistor, Chip, 10, 1/16W, 1%, 0603
STD
STD
2
R514, R515
Resistor, Chip, 100, 1/16W, 1%, 0603
STD
STD
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Bill of Materials
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Table 17. Bill of Materials (continued)
Qty
RefDes
Description
MFR
Part Number
2
R106, R206
Resistor, Chip, 6.19k, 1/16W, 1%, 0603
STD
STD
3
R109, R209, R305
Resistor, Chip, 0, 1/16W, 5%, 0402
STD
STD
2
R110, R210
Resistor, Chip, 2.00k, 1/16W, 1%, 0603
STD
STD
2
R111, R211
Resistor, Chip, 5.90, 1/16W, 1%, 0603
STD
STD
2
R402, R409
Resistor, Chip, 0, 1/16W, 1%, 0603
STD
STD
2
R112, R212
Resistor, Metal Film, 0.003, 1/4W, 1%, 1206
STD
STD
6
R113, R213, R308, R309,
R412, R413
Resistor, Metal Film, 1, 1/4W, 5%, 1206
STD
STD
2
R114, R214
Resistor, Chip, 78.7k, 1/16W, 1%, 0603
STD
STD
3
R115, R116, R215
Resistor, Chip Array, 100k, 62.5mW, 5%, 612
Yageo
TC164-JR-07100KL
4
R121, R122, R221, R222
Resistor, Chip, 1.00k, 1/16W, 1%, 0603
STD
STD
2
R123, R223
Resistor, Chip, 1, 1/16W, 5%, 0603
STD
STD
7
R216, R401, R407, R417,
R421, R504, R513
Resistor, Chip, 100k, 1/16W, 1%, 0603
STD
STD
8
R301, R302, R303, R304,
R414, R415, R419, R423
Resistor, Chip, 10.0k, 1/16W, 1%, 0402
STD
STD
2
R306, R307
Resistor, Chip, 2.05, 1/16W, 5%, 0603
STD
STD
2
R310, R311
Resistor, Chip, 3.48k, 1/16W, 1%, 0402
STD
STD
1
R312
Resistor, Chip, 5.11, 1/16W, 5%, 0402
STD
STD
1
R403
Resistor, Chip, 102k, 1/16W, 1%, 0603
STD
STD
2
R404, R406
Resistor, Chip, 75.0k, 1/16W, 1%, 0603
STD
STD
1
R405
Resistor, Chip, 28.7k, 1/16W, 1%, 0603
STD
STD
1
R416
Resistor, Chip, 6.81k, 1/16W, 1%, 0603
STD
STD
2
R408, R411
Resistor, Chip, 3.48k, 1/16W, 1%, 0603
STD
STD
1
R410
Resistor, Chip, 3.3, 1/16W, 5%, 0603
STD
STD
2
R418, R422
Resistor, Chip, 7.87k, 1/16W, 1%, 0603
STD
STD
1
R420
Resistor, Chip, 2.49k, 1/16W, 1%, 0603
STD
STD
1
R501
Resistor, Chip, 68.1, 1/16W, 1%, 0603
STD
STD
1
R502
Resistor, Chip, 5.62k, 1/16W, 1%, 0603
STD
STD
2
R509, R510
Resistor, Chip, 330, 1/16W, 1%, 0603
STD
STD
1
R511
Resistor, Chip, 8.06k, 1/16W, 1%, 0603
STD
STD
2
R516, R521
Resistor, Chip, 0.001, 2W, 1%, 2512
STD
STD
4
R517–R520
Resistor, Chip, 0.100, 2W, 1%, 2512
STD
STD
2
RT101, RT210
NTC Thermistor, 150k, 0603, 5%
Panasonic-ECG
ERTJ1VV154J
2
U101, U210
IC, Single phase, D-CAP Synchronous Buck Controller, QFN-32
TI
TPS59610RHB
1
U301
IC, Dual Synchronous PWM Controller, QFN-32
TI
TPS51120RHB
1
U401
IC, Dual Synchronous Step down Controller, QFN-24
TI
TPS59124RGE
2
U402, U403
IC, 1.5A LDO Regulator with soft start, SON-10
TI
TPS74801DRC
1
U404
IC, High performance DDRI&II 3A LDO &buffered reference,
MSOP-Power PAD
TI
TPS51100DGQ
1
U501
IC, 4.5-18V Input, 3A Step down Regulator with integrated Switcher, TI
QFN-16
TPS54326RGT
1
U502
IC, Timer, Lower power CMOS, SO-8
TI
TLC555CD
1
U503
IC, Dual 4A high speed low side MOSFET driver, SO-8
TI
UCC37324DR
1
U504
IC, Quadruple 2 Input positive And Gates, SO-14
TI
SN74HC08D
38
An 8-V to 14-V Vin 2010 Atom™ E6xx— Tunnel Creek Power System
© 2010, Texas Instruments Incorporated
SLUU465 – November 2010
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Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding
electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the
technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY
SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING
ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to
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EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER
FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the
product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s
environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and
can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15
of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this
equipment in other environments may cause interference with radio communications, in which case the user at his own expense
will be required to take whatever measures may be required to correct this interference.
EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 8 V to 14 V and the output voltage range of 0.9 V to 5 V .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60° C. The EVM is designed to
operate properly with certain components above 60° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
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【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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SPACER
SPACER
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SPACER
SPACER
SPACER
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
2.
3.
4.
You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even
if the EVM should fail to perform as described or expected.
You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.
Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives
harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in
connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.
Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
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