User's Guide
SLUU796 – January 2012
Using the TPS59640EVM-751 IMVP-7, 3-Phase
CPU/1-Phase GPU SVID Power System
The TPS59640EVM-751 evaluation module (EVM) is a complete solution for the Intel™ IMVP-7 Serial VID
(SVID) Power System from a 9-V to 20-V input bus. This EVM uses the TPS59640 for IMVP-7 3-Phase
CPU and 1-Phase GPU Vcore, TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4 memory rail
(1.2VDDQ, 0.6VTT, and 0.6VTTREF). The TPS59640EVM-751 also uses the 5-mm x 6-mm TI power
block MOSFET (CSD87350Q5D) for high-power density and superior thermal performance.
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Contents
Description ................................................................................................................... 4
1.1
Typical Applications ................................................................................................ 4
1.2
Features ............................................................................................................. 4
TPS59640EVM-751 Power System Block Diagram .................................................................... 5
Electrical Performance Specifications .................................................................................... 6
Schematic .................................................................................................................... 8
Test Setup .................................................................................................................. 21
5.1
Test Equipment ................................................................................................... 21
5.2
Recommended Wire Gage ...................................................................................... 22
5.3
Recommended Test Setup ...................................................................................... 22
5.4
USB Cable Connections ......................................................................................... 23
5.5
Input Connections ................................................................................................ 23
5.6
Output Connections .............................................................................................. 24
Configuration ............................................................................................................... 24
6.1
CPU and GPU Configuration ................................................................................... 24
6.2
1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration ...................................................... 27
6.3
1.05V VCCIO Configuration ..................................................................................... 27
Test Procedure ............................................................................................................ 28
7.1
Line/Load Regulation and Efficiency Measurement Procedure ............................................ 28
7.2
Equipment Shutdown ............................................................................................ 31
Performance Data and Typical Characteristic Curves ................................................................ 32
8.1
CPU3-Phase Operation .......................................................................................... 32
8.2
CPU 2-Phase Operation ......................................................................................... 36
8.3
CPU 1-Phase Operation ......................................................................................... 40
8.4
GPU Operation ................................................................................................... 44
8.5
1.05V VCCIO ...................................................................................................... 48
8.6
1.2 VDDQ .......................................................................................................... 51
EVM Assembly Drawings and PCB layout ............................................................................. 53
Bill of Materials ............................................................................................................. 59
List of Figures
1
TPS59640EVM-751 Power System Block Diagram .................................................................... 5
2
TPS59640EVM-751 EVM Illustration ..................................................................................... 6
3
TPS59640EVM-751 Schematic (1 of 13) ................................................................................ 8
4
TPS59640EVM-751 Schematic (2 of 13) ................................................................................ 9
Intel is a trademark of Intel Corporation.
Windows is a trademark of Microsoft Corporation.
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1
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5
TPS59640EVM-751 Schematic (3 of 13)............................................................................... 10
6
TPS59640EVM-751 Schematic (4 of 13)............................................................................... 11
7
TPS59640EVM-751 Schematic (5 of 13)............................................................................... 12
8
TPS59640EVM-751 Schematic (6 of 13)............................................................................... 13
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TPS59640EVM-751 Schematic (7 of 13)............................................................................... 14
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TPS59640EVM-751 Schematic (8 of 13)............................................................................... 15
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TPS59640EVM-751 Schematic (9 of 13)............................................................................... 16
12
TPS59640EVM-751 Schematic (10 of 13) ............................................................................. 17
13
TPS59640EVM-751 Schematic (11 of 13) ............................................................................. 18
14
TPS59640EVM-751 Schematic (12 of 13) ............................................................................. 19
15
TPS59640EVM-751 Schematic (13 of 13) ............................................................................. 20
16
USB Cable.................................................................................................................. 21
17
TPS59640EVM-751 Recommended Test Setup ...................................................................... 23
18
TPS59640EVM-751 CPU GUI Setup Window ......................................................................... 29
19
TPS59640EVM-751 GPU GUI Setup Window
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20
CPU3 Efficiency
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........................................................................
...........................................................................................................
CPU3 Load Regulation ...................................................................................................
CPU3 Enable Turnon .....................................................................................................
CPU3 Enable Turnoff .....................................................................................................
CPU3 Switching Node (Ripple) .........................................................................................
CPU3 Dynamic VID: SetVID-Slow/Slow ................................................................................
CPU3 Dynamic VID:SetVID-Fast/Fast .................................................................................
CPU3 Dynamic VID:SetVID-Decay/Fast ...............................................................................
CPU3 Output Load Insertion With OSR/USR20k (Min) .............................................................
CPU3 Output Load Release With OSR/USR 20k (Min) ..............................................................
CPU3 Bode Plot at 12Vin, 1.05 V/60 A .................................................................................
CPU3 MOSFET ...........................................................................................................
CPU3 IC ....................................................................................................................
CPU2 Efficiency ...........................................................................................................
CPU2 Load Regulation ...................................................................................................
CPU2 Enable Turnon ....................................................................................................
CPU2 Enable Turnoff ....................................................................................................
CPU2 Switching Node (Ripple) .........................................................................................
CPU2 Dynamic VID: SetVID-Slow/Slow ................................................................................
CPU2 Dynamic VID: SetVID-Fast/Fast ................................................................................
CPU2 Dynamic VID: SetVID-Decay/Fast ..............................................................................
CPU2 Output Load Insertion With OSR/USR 20k (Min) .............................................................
CPU2 Output Load Release With OSR/USR 20k (Min) .............................................................
CPU2 Bode Plot at 12Vin, 1.05 V/55 A .................................................................................
CPU2 MOSFET ...........................................................................................................
CPU2 IC ....................................................................................................................
CPU1 Efficiency ...........................................................................................................
CPU1 Load Regulation ...................................................................................................
CPU1 Enable Turnon ....................................................................................................
CPU1 Enable Turnoff ....................................................................................................
CPU1 Switching Node ...................................................................................................
CPU1 Switching Node and Ripple ......................................................................................
CPU1 Dynamic VID: SetVID-Slow/Slow ...............................................................................
CPU1 Dynamic VID: SetVID-Fast/Fast ................................................................................
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
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..............................................................................
CPU1 Output Load Insertion With OSR/USR 20k (Min) .............................................................
CPU1 Output Load Release With OSR/USR 20k (Min) .............................................................
CPU1 Bode Plot at 12Vin, 1.05 V/33 A .................................................................................
CPU1 MOSFET ...........................................................................................................
CPU1 IC ....................................................................................................................
GPU Efficiency ............................................................................................................
GPU Load Regulation .....................................................................................................
GPU Enable Turnon ......................................................................................................
GPU Enable Turnoff ......................................................................................................
GPU Switching Node .....................................................................................................
GPU Switching Node and Ripple ........................................................................................
GPU Dynamic VID: SetVID-Slow/Slow ................................................................................
GPU Dynamic VID: SetVID-Fast/Fast .................................................................................
GPU Dynamic VID: SetVID-Decay/Fast ...............................................................................
GPU Output Load Insertion With OSR/USR 20k (Min) ..............................................................
GPU Output Load Release With OSR/USR 20k (Min) ..............................................................
GPU Bode Plot at 12Vin, 1.23 V/33 A ..................................................................................
GPU MOSFET ............................................................................................................
GPU IC ......................................................................................................................
1.05-V Efficiency ..........................................................................................................
1.05-V Load Regulation ..................................................................................................
1.05-V Enable Turnon ....................................................................................................
1.05-V Enable Turnoff ....................................................................................................
1.05-V Switching Node ...................................................................................................
1.05-V Ripple...............................................................................................................
1.05-V Transient DCM to CCM .........................................................................................
1.05-V Transient CCM to DCM ..........................................................................................
TPS51219 Thermal........................................................................................................
1.2-V Efficiency ...........................................................................................................
1.2-V Load Regulation ....................................................................................................
1.2-V Enable Turnon .....................................................................................................
1.2-V Enable Turnoff .....................................................................................................
1.2-V Switching Node ....................................................................................................
1.2-V Ripple ................................................................................................................
1.2-V Transient DCM to CCM ...........................................................................................
1.2-V Transient CCM to DCM ...........................................................................................
TPS51916 Thermal........................................................................................................
TPS59640EVM-751 Top Layer Assembly Drawing (Top View) .....................................................
TPS59640EVM-751 Bottom Assembly Drawing (Bottom View) .....................................................
TPS59640EVM-751 Top Copper .......................................................................................
TPS59640EVM-751 Bottom Copper ...................................................................................
TPS59640EVM-751 Internal Layer 2 ..................................................................................
TPS59640EVM-751 Internal Layer 3 ..................................................................................
TPS59640EVM-751 Internal Layer 4 ..................................................................................
TPS59640EVM-751 Internal Layer 5 ...................................................................................
TPS59640EVM-751 Internal Layer 6 ...................................................................................
TPS59640EVM-751 Internal Layer 7 ...................................................................................
CPU1 Dynamic VID: SetVID-Decay/Fast
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Description
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List of Tables
1
TPS59640EVM-751 Electrical Performance Specifications ........................................................... 6
2
Current Limit Trip Selection .............................................................................................. 24
3
CPU Frequency Selection ................................................................................................ 25
4
GPU Frequency Selection ................................................................................................ 25
5
GPU Overshoot/Undershoot Reduction Selection .................................................................... 25
6
GPU Overshoot/Undershoot Reduction Selection .................................................................... 26
7
F2806 DSP Program Mode Selection
26
8
F2806 DSP Program Mode Selection
26
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1
..................................................................................
..................................................................................
Onboard Dynamic Load Selection ......................................................................................
VR_ON Enable Selection.................................................................................................
VDDQ S3, S5 Enable Selection ........................................................................................
VCCIO Output Voltage Selection .......................................................................................
Bill of Materials.............................................................................................................
26
27
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27
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Description
The TPS59640EVM-751 evaluation module is designed to use a 9-V to 20-V input bus to produce six
regulated outputs for the IMVP-7 SVID CPU/GPU Power System. The TPS59640EVM-751 is specially
designed to demonstrate the TPS59640 full IMVP-7 mobile feature while providing a GUI communication
program and a number of test points to evaluate the static and dynamic performance of the TPS59640.
1.1
Typical Applications
•
1.2
IMVP-7 Vcore applications for adapter, battery, NVDC, or 3-V/5-V/12-V rails
Features
The TPS59640EVM-751 features:
• Complete solution for 9-V to 20-V input Intel IMVP-7 SVID Power System
• GUI communication to demonstrate full IMVP-7 mobile feature
• Three-phase CPU Vcore can support up to 94-A output current
• One-Phase GPU Vcore can support up to 33-A output current
• Eight selectable switching frequencies for CPU and GPU power
• Eight levels selectable current limit for CPU and GPU power
• Eight levels selectable output overshoot/undershoot reduction (OSR/USR™) for CPU and GPU power
• Switches or jumpers for each output enable
• Onboard dynamic load for CPU, GPU Vcore and VCCIO output
• High efficiency and high density by using TI power block MOSFET
• Convenient test points for probing critical waveforms
• Eight-layer PCB with 2-oz copper
4
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
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TPS59640EVM-751 Power System Block Diagram
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2
TPS59640EVM-751 Power System Block Diagram
IMVP7
TPS59640
9-20VBAT
CPU Core
(94A)
48 Pin
6x6 QFN
TPS51219
SVID
GPU Core
(33A)
Power Block
16 Pin
3x3 QFN
TPS51916
20 Pin
3x3 QFN
TPS70102PWP
5Vin
20 Pin
PWP
VCCIO: 1.05V/15A
DDR3L/DDR4 Memory Rail
VDDQ: 1.2V/15A
VTT: 0.6V/2A,
VTTREF: 0.6V/10mA
1.8V/500mA
3.3V/250mA
CPU: 0A-32A
On Board Dynamic
Load for CPU, GPU
and VCCIO
GUI communication
USB Cable
A
B
GPU: 0A-19A
VCCIO: 0A-10A
TMS320F2806PZS
TUSB3410RHB
Host Computer
Figure 1. TPS59640EVM-751 Power System Block Diagram
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5
Electrical Performance Specifications
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IMVP7 TPS59640 + TPS51219 + TPS51916 POWER EVM with
CSD87350Q5D Powerblocks
CPU/GPU
VR_ON
Connections
for electronic
loads
CSD87350Q5D
OCL, FSW,
OSR selection
CPU Core
TPS59640
TPS51219
VCCIO
GPU CORE
Sandy Bridge
CPU socket (not
populated)
Intel SVID GUI
from USB
TPS51916
DDR3L/DDR4
Memory Rail
Figure 2. TPS59640EVM-751 EVM Illustration
3
Electrical Performance Specifications
Table 1. TPS59640EVM-751 Electrical Performance Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
20
UNIT
INPUT CHARACTERISTICS
12VBAT input voltage range
VBAT
Maximum input current
VBAT = 12 V, all full load (3-Phase CPU/1-Phase GPU)
9
No-load input current
VBAT=12 V, all no load(3-Phase CPU/1-Phase GPU)
5VIN input voltage range
Vin = 5 V
Maximum input current
VBAT =12 V, all full load
0.3
A
No-load input current
VBAT=12 V, all no load
0.1
A
1.05
V
4.5
V
16.2
A
0.1
A
5
5.5
V
OUTPUT CHARACTERISTICS
CPU (TPS59640)
Output voltage Vcore
Output voltage regulation
6
SVID: address:00 CPU, payload: 1.05 V
Line regulation
0.1%
–1.9
Load regulation(droop) load line
Output voltage ripple
VBAT=12 V, 1.05 V/90 A (3-Phase) at 300 kHz
Output load current
CPU 3-Phase operation
Output over current
Selectable per phase
Switching frequency
Selectable
Full load efficiency
VBAT=12 V, 1.05 V/94 A at 300 kHz
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
mΩ
25
0
mVpp
94
A
600
kHz
37
250
300
A
80.05%
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Electrical Performance Specifications
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Table 1. TPS59640EVM-751 Electrical Performance Specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPU (TPS59640)
Output voltage Vcore
Output voltage regulation
SVID: address:01 GPU, payload: 1.23 V
1.23
Line regulation
–3.9
Load regulation (droop) load line
Output voltage ripple
VBAT = 12 V, 1.23 V/35 A at 385 kHz
Output load current
CPU 3-Phase operation
Output over current
Selectable per phase
Switching frequency
Selectable
Full load efficiency
VBAT = 12 V, 1.23 V/35 A at 385 kHz
V
0.1%
mΩ
30
0
mVpp
35
A
660
kHz
37
275
385
A
81.99%
1.05-V VCCIO (TPS51219)
Output voltage
Output voltage regulation
Output voltage ripple
1.05
Line regulation
0.1%
Load regulation
0.1%
VBAT =12 V, 1.05 V/15 A
Output load current
30
0
Output over current
Switching frequency
Selectable
Full load efficiency
VBAT = 12 V, 1.05 V/15 A
V
mVpp
15
A
24
A
500
kHz
89.27%
DDR3L/DDR4 MEMORY RAIL (TPS51916)
Output voltage
Output voltage regulation
Output voltage ripple
1.2
Line regulation
0.1%
Load regulation
0.1%
VBAT = 12 V, 1.2 V/15 A
Output load current
Switching frequency
Selectable
Full-load efficiency
VBAT = 12 V, 1.2 V/15 A
Operating temperature
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30
0
Output over current
V
mVpp
15
A
500
kHz
90.62%
25
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
A
24
°C
7
3
8
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
5
200k
R21
TP17
C1 6
0.33uF
TP10
C28
220nF
R16
150k
R14
169k
C23
1uF
TP19
2
R5
1
R24
309k
TP7
100pF
C26
4.12k
R22
8.45k
R6
C14
100pF
R3
54.9
R26
0
TP1
4
R25
R15
2.21
R11
2.21
TP16
C24
1uF
C27
1
RT2
100k
1
7
9
TP12
0
R13
0
R12
TP4
C5
10uF
TP15
TP11
C6
10uF
GPU OSR/USR selection: See sheet 5
CPU thrid phase: See sheet 2
GPU phase: See sheet 3
8
9
CPU OSR/USR selection: See sheet 5
GPU OCP selection: See sheet 5
CPU OCP selection: See sheet 5
GPU Switching frequency selection: See sheet 5
CPU Switching frequency selection: See sheet 5
Not used
2.21
R19
TP13
C17
1uF
R9
2.21
C4
10uF
TP3
7
6
5
4
3
1
6
8
R17
10.0k
TP8
TP6
C3
4.7uF
2
TP5
15.4k
R8
C15
1
10
R2
15.4k
1
R20
RT1
100k
C2
2.2uF
TP2
R23
TP18
TPS59640RSL
220nF
C1
R1
71.5k
C7
10uF
1
L2
0.36uH
C9
10uF
+
C18 +
470uF
C10
10uF
TP9
C12
1nF
TP14
C19 + C20 +
470uF
470uF
C11
10uF
C21
470uF
C13
1nF
CPU and GPU Control, 1st and 2nd Phase CPU VCORE
R18
1
C25
C22
1
R10
1
L1
0.36uH
C8
10uF
4
R7
42.2k
R4
130
Schematic
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Note: Jumpers set to default locations; see Section 6 of this user’s guide.
Schematic
Figure 3. TPS59640EVM-751 Schematic (1 of 13)
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TP24
Copyright © 2012, Texas Instruments Incorporated
22uF
22uF
22uF
C 41
C31
10uF
22uF
C40
1uF
C34
C30
10uF
22uF C54 22uF C55 22uF C56
C39
2.21
R27
C29
10uF
C53
TP25
TP21
TP20
22uF
C43
22uF
C57
C42
TP23
22uF
C58
C33
1nF
22uF
C38
2.2uF
C32
10uF
1
C46
C47
10uF
10uF
10uF C61 22uF C62
Not
used
10uF
10uF
C45
22uF C60
0
R30
22uF C59
C44
TP26
R28
2.21
C48
10uF
10uF C63
1
C49
1
C37
1
R29
10uF
C64
TP22
1
C50
10uF
C65
L3
u
0.36
H
22uF
C51
+
1
CPU 3
1
10uF
C66
C35
1
C52
1
1
C36
1
1
rd Phase
VCORE
22uF
1
+
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Schematic
Figure 4. TPS59640EVM-751 Schematic (2 of 13)
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
9
10
TP33
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
22uF
C87
TP34
TP 29
1
C77
TP28
1
C78
22uF
C8 9
1uF
2.21
1
C79
C69
10uF
C73
C68
10u F
R33
22uF
C88
C67
10uF
22uF
C90
1
C80
C76
2.2uF
C70
10uF
1
C91
1
C82
22uF
C92
C81
TP35
2.21
R31
22uF
TP3 0
C71
1nF
1
C93
1
1
C94
Not used
22uF
C83
0
R34
22u F
C84
2 2uF
C95
22uF
C85
22uF
C96
TP31
22uF
C86
1
C75
1
R3 2
1
1
L4
0.36uH
C72
330uF
GPU VCORE
GN D_PWR
+
+
330uF
C74
TP36
TP32
Schematic
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Figure 5. TPS59640EVM-751 Schematic (3 of 13)
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C98
33nF
Copyright © 2012, Texas Instruments Incorporated
C102
33nF
R69
28.7k
C110
33nF
0
R70
0
R68
162k
RT6
100k
0
R64
17.8k
C106
33nF
0
R56
0
R52
R66
R6 3
28.7k
RT5
100k
R51
28.7k
R65
R62
162k
17.8k
R55
R50
162k
0
RT4
100k
17.8k
0
R41
R45
R39
28.7k
R44
R38
162k
0
17.8k
RT3
100k
R36
R35
1
C105
1
C101
1
C97
1
1
1
1
1
C111
1
C109
1
1
C112
1
1
1
C108
C107
1
C104
C103
1
C100
C99
TP45
TP44
TP43
TP42
TP41
TP40
TP39
TP38
1
R67
1
R58
1
R46
1
R37
10
10
1
1
J15
1
R59
10
R53
10
R47
10
0
R57
0
R54
0
R43
0
R42
1
R60
1
R48
1
R61
1
R49
1
1
J16
J14
To controller
To controller
CPU and GPU VCORE:
Current Sense Feedback and Differential Voltage Feedback
A phase can be disabled by pulling the corresponding xCSPx pin to 3.3V.
Default setting for CPU: 3 phase operation
Dafault setting for GPU: 1 phase operation
Phase disable can be done in reverse order.Phase 3, then 2, then 1.
1. CPU 3 Phase operation: R37, R46, R58 open
2. CPU 2 Phase operation: R58 used 0ohm
3. CPU 1 Phase operation: R46 used 0ohm and Connected CSP3 to GND
4. Disable GPU, R67 used 0ohm
Not used
To processor
To processor
J13
R40
10
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Schematic
Figure 6. TPS59640EVM-751 Schematic (4 of 13)
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
11
11
12
R84
R87
R90
R93
R96
R99
R102
R105
R108
R111
R114
R117
39.2k
30.1k
150k
75.0k
56.2k
39.2k
30.1k
24.3k
20.0k
100k
20.0k
24.3k
56.2k
R78
R81
R75
R72
75.0k
150k
100k
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
13
12
11
12
TP47
TP46
24.3k
20.0k
R116
R107
R110
R113
R98
R101
R104
R95
150k
100k
75.0k
56.2k
39.2k
30.1k
R89
R92
R86
30.1k
24.3k
20.0k
R77
R80
R83
R71
R74
75.0k
56.2k
39.2k
100k
150k
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
OVER-CURRENT PROTECTION SELECTION
Over-Shoot /Under-Shoot Reduction Selection:
1. CPU OSR/USR Default Setting: Jumper shorts on pin1 and pin2 to set Max
2. GPU OSR/USR Default Setting: Jumper shorts on pin1 and pin2 to set Max
Over Current Protection Selection:
1. CPU Over Current Protection Per Phase Default Setting: Jumper shorts on pin 7 and pin 8 to set 40A
2. GPU Over Current Protection Default Setting: Jumper shorts on pin7 and pin8 to set 40A
Switching Frequency Selection:
1. CPU Switching Frequency Default Setting: Jumper shorts on pin13 and pin14 to set 300kHz
2. GPU Switching Frequency Default Setting: Jumper shorts on pin 11 and pin12 to set 385kHz
660kHz (MAX)
605kHz
550kHz
495kHz
440kHz
385kHz
330kHz
275kHz (MIN)
600kHz (MAX)
550kHz
500kHz
450kHz
400kHz
350kHz
300kHz
250kHz (MIN)
SWITCHING FREQUENCY SELECTION
R73
R76
R79
R82
R85
R88
R91
R94
75.0k
56.2k
39.2k
30.1k
24.3k
20.0k
R100
R103
R106
R109
R112
R115
R118
100k
75.0k
56.2k
39.2k
30.1k
24.3k
20.0k
R97
150k
100k
150k
Lev el 8 (MAX OS)
Lev el 7
Lev el 6
Lev el 5
Lev el 4
Lev el 3
Lev el 2
Lev el 1 (MIN OS)
Level 8 (MAX OS)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN OS)
OVER-SHOOT/UNDER-SHOOT REDUCTION
Frequenc y, OCP, OSR/USR SELECTIONS
13
Schematic
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Figure 7. TPS59640EVM-751 Schematic (5 of 13)
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Q5
BSS123
14
TP50
To proces sor
D1
GREEN
R119
180
1
15
14
0
R134
0
R133
R128
10.5k
1
R126
C119
0.1uF
R123
1.00k
C124
1nF
TP53
Q6
BSS123
TP49
C125
0.01uF
15
To controller
J25
R130
37.4k
1.00k
R121
C113
1nF
S1: VCCIO Enable Pin
VCCIO Output Selection:
1. Jumper shorts on pin1 and pin2 of J23 to set VCCIO: 1.05V(Default)
2. Jumper shorts on pin2 and pin3 of J23 to set VCCIO: 1.00V
Not used
R135
10
R132
10
R122
10.0k
D2
GREEN
R120
180
0
R131
2.21
R124
C149
1
1
1
22uF
1
C146
C129
C128
1
C150
22uF
C144
TP56
2.21
R125
C116
10uF
22uF
C127
2.2uF
TP52
C115
10uF
C148
C143
22uF
C120
0.1uF
C114
10uF
C147
TP51
TP48
1
C130
0
R129
C117
10uF
1
C145
1
C131
C118
1nF
22uF
C141
C132
22uF
C133
22uF
22uF C137
C126
1
1
1
C134
R127
C135
22uF
1
C138 22uF C139
1
C123 +
TP55
TP57
L5
0.56uH
VCCIO Power Supply
22uF
C142
TP54
1
C136
C121 +
330uF
22uF
C140
+
C122
330uF
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Schematic
Figure 8. TPS59640EVM-751 Schematic (6 of 13)
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
13
14
Q8
BSS123
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
0
R 150
0
R 148
C160
2.2uF
D3
GREEN
R136
180
C157
10uF
R137
10.0k
TP60
16
1
TP70
C164
0.1uF
To controller
J29
C163
0.22uF
C176
1nF
R141
37.4k
0
R146
C156
0.1uF
R142
2.21
R138
10.0k
S3/S5 Enable Control, See datasheet for detail
Not used
R149
20.0k
R147
10.0k
R140
1.00k
R139
10.0k
16
C 162
2.2uF
TP61
1
C174
T P67
2.21
R 143
C175
1
C166
10uF
C165
0
R145
10uF
C170
10uF
C167
Q9
CSD87350Q5D
C152
10uF
C151
10uF
10uF
T P59
T P58
C153
10uF
C168
TP62
1
R144
10uF
C172
C155
1
1
C173
L6
0.56uH
1nF
C169
1
C161
C154
10uF
VDDQ Power Supply
1
C171
10uF
TP68
C158
330uF
TP63
+
+
1
C159
Schematic
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Figure 9. TPS59640EVM-751 Schematic (7 of 13)
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C189
0.01uF
R173
100k
R170
8.06k
C192
0.1uF 0.1uF
C191
D6
BAT54
R171
10.0k
VCCIO_DL
GPU_DL
CPU_DL1
CPU_DL2
1
C179
R158
1
5V Bias Voltage Input
TP77
+
VBAT Voltage Input:
9V- 20V
C193
0.1uF
R165
10.0k
R159
1
R174
10.0k
TP79
C178 TP74
1
TP78
+
TP73
17
R160
1
TP80
TP82
17
1
C180
0.1uF
C181
10uF
100k
R152
10
9
8
7
6
5
4
3
2
1
U8:A
U8:D
U8:C
U8:B
CD74HCT08D
S3
1uF
C194
U10
UCC27324D
C188
1uF
U9
UCC27324D
VIN2
VIN2
GND
R176
330
R177
330
VOU T1
RESET
PGD_1
VSENSE1
PwrPad
R178
330
D7
RED
R179
330
D5
RED
150mA LDO
D8
RED
NC
VOU T1
D4
RED
C186
0.01uF
TP81
NC
VOU T2
VOU T2
SEQUENCE VSENSE2
ENA BLE
MR1
MR2
VIN1
VIN1
NC
U6
TPS70102PWP
1.2V LDO
VCCIO, GPU and CPU Dynamic Load:
1. Switch to "ON" position to enable the Dynamic Load
U7
2. Switch to "OFF" position to disable the Dynamic Load (Default)
TPS71712DCK
1
5
OUT
IN
2
GND
3
4
EN NR/FB
C185
S2
0.1uF
Not used
TP75
TP72
R156
51.1k
1uF
TP86 C190
TP85
R175
0.005
R168
0.05
R166
0.05
30.1k
C183
10uF
TP76
R169
0.05
R167
0.01
C177
10uF
TP71
Q13
CSD16407Q5
30.1k
R154
R155
R151
15.0k
Q12
CSD16407Q5
C184
2.2uF
3.3V LDO
11
12
13
14
15
16
17
18
19
20
1.8V LDO
C187
1uF
R164
0.05
R162
0.01
R172
0.005
Q11
CSD16407Q5
TP83
R163
0.05
R161
0.01
LDOs and Dynamic Loads
TP84
Q10
CSD16407Q5
1
R157
C182
0.1uF
R153
2.00k
www.ti.com
Schematic
Figure 10. TPS59640EVM-751 Schematic (8 of 13)
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
15
16
1
R185
C195
1nF
R186
100
18
1
J35
R192
3.01k
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
Q15
BSS123
D9
GREEN
VR_ON
R203
180
Q16
BSS123
D10
GREEN
TP90
C_PGOOD
R204
180
R206
10.0k
C197
10pF
C198
10pF
C196
0.1uF
Q17
BSS123
D12
GREEN
TP89
G_PGOOD
R205
180
R202
10.0k
1
18
R208
10.0k
TP88
R199
330
1
1
C199
0.1uF
Support and Pull-ups
1
10.0k
10.0k
1
1
1
J 32, J34 are Labview connectors for EVM testing
R194
R181
C200
1uF
0
R198
R207
1.00k
1M
0
R196
R197
R200
1.00k
1M
R195
0
0
R190
1M
R191
1M
1M
R189
1
1M
1M
1M
R188
R183
R184
R182
R180
S4: IMVP-7 VR Enable:
1. Switch to "ON" position to Enable TPS59640 controller
2. Switch to "OFF" position to Disable TPS59640 controller(Default)
Not used
R209
180
D11
RED
VR_HOT
Q14
BSS83P
R201
10.0k
J45, J46 are not used and they are for internal I2C connection
To I2C Terminal
R193
3.01k
R187
10.0k
Jumper to enter
I2C Mode
Logic Signal and Status LED's
LED is ON when the logic signal is in the ACTIVE state
TPS59640 Default Trim
R117=not used, R116 = 1.00k
TP87
1
J33
Schematic
www.ti.com
Figure 11. TPS59640EVM-751 Schematic (9 of 13)
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Schematic
R211
75.0
1
R210
1
R212
130
R213
43.2
1
Not used
uC Socket Main
www.ti.com
Figure 12. TPS59640EVM-751 Schematic (10 of 13)
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Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
17
Schematic
1
1
Not used
uC Socket Others
www.ti.com
Figure 13. TPS59640EVM-751 Schematic (11 of 13)
18
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
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J42
Copyright © 2012, Texas Instruments Incorporated
1
20
J43
R221
475
D13
GREEN
USB Connector
DM
V+
VNC
DP
19
FB1
J41
R222
2.21k
R216 33.2
R215 33.2
TP91 TP92
20
19
1
R214
1.50k
C202
0.1uF
C206
22pF
C208
0.01uF
U14
TUSB3410RHB
For Internal software developmenet
5V Bias option:
1. Jumper shorts on J41, 5V Bias used from USB. If USB 5V is used, external 5V supply from
2. No Jumper shorts on J41, 5V Bias used from external J31 (Default)
Not used
10.0k
R218
C205
22pF
C201
0.1uF
Y1
2
USB to DSP
0
R220
0
R219
C207
0.01uF
1
C204
J31 should not be used.
TP94
TP93
10.0k
R217
1
C203
1
www.ti.com
Schematic
Figure 14. TPS59640EVM-751 Schematic (12 of 13)
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
19
C210
0.1uF
C211
0.1uF
20
C214
0.1uF
U15:B
TMS320F2806PZS
C213
0.1uF
C215
0.1uF
47 GPIO
0
44
GPIO1
45
GPIO2
48
GPIO3
51
GPIO4
53
GPIO5
56
GPIO6
58
GPIO7
60
GPIO8
61 GPIO9
64
GPIO10
70 GPIO11
1
GPIO 12
95
GPIO13
8
GPIO14
9
GPIO15
50
GPIO16
C209
0.1uF
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
79
GPIO27
GPIO26 99
91
GPIO25
GPIO24 83
72
GPIO23
71
GPIO22
67
GPIO21
63
GPIO20
57
GPIO19
54
GPIO18
GPIO17 52
43
GPIO34
5
GPIO33
100
GPIO32
7
GPIO31
6
GPIO30
4
GPIO29
GPIO28 92
U15:A
TMS3 20F2806PZS
15 VDDA2
76
TDO
14 VSSA
73
TDI
2
26
74
VDDAIO
TMS
25
75
VSSAIO
TCK
12
84
VDD1A18
TRST
13
94
VSS1AGND VSS
40
VSS 89
VDD2A18
39
VSS2AGND VSS 87
10
VSS 77
VDD
42
69
VDD
VSS
59 VDD
VSS 62
68 VDD
VSS 55
85 VDD
49
VSS
93
41
VDD
VSS
3
11
VSS
VDDIO
46
2
VSS
VDDIO
65
82
VDDIO
VDDIO
C212
0.1uF
J46
2.74k
R227
21
1
C224
R224
2.00k
X1
ADCREFM
U15:C
TMS320F2806PZS
C217
0.1uF
C227
1
86 X2
78
XRS
16 ADCI
NA7
17 A
DCINA6
18
ADCINA5
19
ADCINA4
20
ADCINA3
29
30
24
27
28
37
35
38
36
C218
0.1 uF
C219
0.1uF
2
6
GREEN
D14
C222
0.1uF
TP96
4 B2
5
B1
3
U18:B
4
VCCA 7
6
VCCB
U17
SN74AVC2T245RSW
1
10
DIR1
DIR2
2 OE
A2 9
3 GND
A1 8
1
5
C221
0.1uF
SN74LVC2G07DCK
U16:A
C220
0.1uF
1
TP97
C226
1uF
TP95
SPISOMI
R226
475
23
22
21
1
Differential Probe Test Point
J46: F2806 DSP Program Mode Selection:
1. Jumper shorts for F2806 DSP Program Mode
2. No Jumper shorts for normal operation (Default)
GUI and Intel VRTT Tool Selection:
1. Jumper shorts to use Intel VRTT Tool (Not us ed)
2. No Jumper shorts to user GUI (Default)
Not us ed
2
5
C225
1uF
6
23
23
23
3
U16:B
U18:A
DSP to S VID
Level Shifting Tranceiver nd Open Drain Buffers for DSP to SVID Translation
ADCINB4 31
32
ADCINB5
33
ADCINB6
34
ADCINB7
23
ADCINA0
22
ADCINA1
ADCINA2 21
80
ADCREFP
EMU0
81
ADCREFIN
EMU1
96
VDD3VFLADCRESEXT
97
TEST1
ADCLO
98
ADCINB0
TEST2
66
XCLKOUT ADCINB1
90
ADCINB2
XCLKIN
88 X1
ADCINB3
R225
2.00k
C216
0.1uF
J48
J47
J45
C223
0.1uF
4
R223
2.00k
22
J 44
1
Schematic
www.ti.com
Figure 15. TPS59640EVM-751 Schematic (13 of 13)
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Test Setup
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5
Test Setup
5.1
Test Equipment
5.1.1
Personal Computer (Host Computer)
Microsoft Windows™ XP or newer with available USB port
5.1.2
USB Cable
The USB cable: standard USB_A to USB_B, 5-pin, mini-B cable. See the Figure 16 illustration.
Figure 16. USB Cable
5.1.3
TPS59640 USB Driver and SVID GUI Installation
Copy the file swrc094f.zip to the host computer.
Copy the file TI-SVID-GUI_1_5_0_1 exe to the host computer.
Extract setup.exe from the aforementioned .zip file.
Double-click on this setup.exe. This loads the TUSB drivers files to the host computer on C:\Program
Files\Texas Instruments Inc\TUSB3410 Single Driver installer\DISK1
5. Then, go to this location on the host computer (C:\Program Files\Texas Instruments Inc\TUSB3410
Single Driver installer\DISK1), and double-click setup.exe. This installs the TUSB driver.
1.
2.
3.
4.
5.1.4
DC Source
12VBAT DC Source: The 12VBAT DC source must be a 0-V to 20-V variable DC source capable of
supplying a 20-Adc current. Connect 12VBAT to J30 as shown in Figure 17.
5Vin DC Source: The 5Vin DC source must be a 0-V to 5-V variable DC source capable of supplying a
1-Adc current. Connect 5Vin to J31 as shown in Figure 17.
5.1.5
•
•
•
•
5.1.6
Meters
V1: 5Vin at TP72(5Vin) and TP75 (GND)
V2: 12VBAT at TP73(VBAT) and TP21 (GND)
V3: CPU Vcore sense voltage at J14; GPU Vcore sense voltage at J16; VDDQ sense voltage at J29,
VCCIO sense voltage at J25
A1: 12VBAT input current
Load
The output load must be an electronic constant current load capable of 0 Adc to 90 Adc.
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21
Test Setup
5.1.7
www.ti.com
Oscilloscope
A digital or analog oscilloscope can be used to measure the output ripple. The oscilloscope must be set
for 1-MΩ impedance, 20-MHz bandwidth, AC coupling, 2-µs/division horizontal resolution, 50-mV/division
vertical resolution. Test points TP27 and TP37 can be used to measure the output ripple voltage for CPU
and GPU. Do not use a leaded ground connection as this can induce additional noise due to the large
ground loop.
5.2
Recommended Wire Gage
1. V5in to J31 (5-V input):
The recommended wire size is 1 x AWG 18 per input connection, with the total length of wire less than
4 feet (2- foot input, 2-foot return).
2. 12VBAT to J30 (12-V input):
The recommended wire size is 1 x AWG 16 per input connection, with the total length of wire less than
4 feet (2-foot input, 2-foot return).
3. J1, J5, J6 (CPU) to LOAD or J11 (GPU) to LOAD or J28 (VDDQ) to LOAD or J24 (VCCIO) to
LOAD
The minimum recommended wire size is 2 x AWG 16, with the total length of wire less than 4 feet
(2-foot output, 2-foot return)
5.3
Recommended Test Setup
Figure 17 is the recommended test setup to evaluate the TPS59640EVM-751. Working at an ESD
workstation, ensure that any wrist straps, bootstraps, or mats are connected referencing the user to earth
ground before handling the EVM.
22
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
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Test Setup
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12VBAT DC
Source
-
+
5Vin DC
Source
+
-
Load
VCCIO
USB Cable
A
+
-
+
-
- +
V3
CPU
- + - +
A1
V2
- +
-
V1
+
+
-
TEXAS
INSTRUMENTS
B
GPU
+
Host Computer
+ VDDQ
Figure 17. TPS59640EVM-751 Recommended Test Setup
5.4
USB Cable Connections
A standard USB_A and 5-pin mini_B USB cable is required to connect the host computer to J42 USB port
(left bottom side). A green LED (D13) lights up near the USB port on the EVM. This indicates that the USB
cable is connected.
5.5
Input Connections
1. Prior to connecting the 5Vin DC source, it is advisable to limit the source current from 5 Vin to 1 A
maximum. Make sure that 5Vin is initially set to 0 V and connected as shown in Figure 17.
2. Prior to connecting the 12VBAT DC source, it is advisable to limit the source current from 12VBAT to
10 A maximum. Make sure that 12VBAT is initially set to 0 V and connected as shown in Figure 17.
3. Connect voltmeters V1 at TP72 (5Vin) and TP75 (GND) to measure 5Vin voltage, V2 at TP73 (12
VBAT), and TP21 (GND) to measure 12VBAT voltage as shown in Figure 17.
4. Connect a current meter A1 between 12VBAT DC source and J30 to measure the 12VBAT input
current.
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Power System
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23
Configuration
5.6
www.ti.com
Output Connections
1. Connect the load to J1, J5, and J6, and set the load to constant resistance mode to sink 0 Adc before
5Vin and 12VBAT are applied. This is for CPU operation.
2. Connect a voltmeter V3 at J14 to measure CPU Vcore sense voltage.
6
Configuration
All jumper selections must be made prior to applying power to the EVM. The user can configure this EVM
per the following configurations.
6.1
6.1.1
CPU and GPU Configuration
CPU/GPU Current Limit Trip Selection (J17 for CPU and J20 for GPU)
The current limit trip can be set by J17 (COCP) and J20 (GOCP).
Default setting: Level 5 for both CPU and GPU.
Table 2. Current Limit Trip Selection
24
Jumper Set to
Connected Resistor
COCP Limit (Typ)
Left (1-2 pin shorted)
150k
Max
Second (3-4 pin shorted)
100k
Level 7
Third (5-6 pin shorted)
75k
Level 6
Fourth (7-8 pin shorted)
56.2k
Level 5
Fifth (9-10 pin shorted)
39.2k
Level 4
Sixth (11-12 pin shorted)
30.1k
Level 3
Seventh (13-14 pin shorted)
24.3k
Level 2
Right (15-16 pin shorted)
20.0k
Min
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6.1.2
CPU Frequency Selection (J18)
The operating frequency can be set by J18
Default setting: 300 kHz for CPU.
Table 3. CPU Frequency Selection
6.1.3
Jumper Set to
Connected Resistor
CPU
Left (1-2 pin shorted)
150k
600 kHz
Second (3-4 pin shorted)
100k
550 kHz
Third (5-6 pin shorted)
75k
500 kHz
Fourth (7-8 pin shorted)
56.2k
450kHz
Fifth (9-10 pin shorted)
39.2k
400kHz
Sixth (11-12 pin shorted)
30.1k
350kHz
Seventh (13-14 pin shorted)
24.3k
300kHz
Right(15-16 pin shorted)
20.0k
250kHz
GPU Frequency Selection (J21)
The operating frequency can be set by J21.
Default setting: 385 kHz for GPU.
Table 4. GPU Frequency Selection
6.1.4
Jumper Set to
Connected Resistor
CPU
Left (1-2 pin shorted)
150k
660kHz
Second (3-4 pin shorted)
100k
605kHz
Third (5-6 pin shorted)
75k
550kHz
Fourth (7-8 pin shorted)
56.2k
495kHz
Fifth (9-10 pin shorted)
39.2k
440kHz
Sixth (11-12 pin shorted)
30.1k
385kHz
Seventh (13-14 pin shorted)
24.3k
330kHz
Right(15-16 pin shorted)
20.0k
275kHz
CPU Overshoot/Undershoot Reduction Selection (J19)
The overshoot/undershoot reduction can be set by J19 CSKIP.
Default setting: Max.
Table 5. GPU Overshoot/Undershoot Reduction Selection
Jumper Set to
Connected Resistor
CPU
Left (1-2 pin shorted)
150k
Max
Second (3-4 pin shorted)
100k
Level 7
Third (5-6 pin shorted)
75k
Level 6
Fourth (7-8 pin shorted)
56.2k
Level 5
Fifth (9-10 pin shorted)
39.2k
Level 4
Sixth (11-12 pin shorted)
30.1k
Level 3
Seventh (13-14 pin shorted)
24.3k
Level 2
Right(15-16 pin shorted)
20.0k
Min
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Configuration
6.1.5
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GPU Overshoot/Undershoot Reduction Selection (J22)
The overshoot/undershoot reduction can be set by J22 GSKIP.
Default setting: Max.
Table 6. GPU Overshoot/Undershoot Reduction Selection
6.1.6
Jumper Set to
Connected Resistor
Right (1-2 pin shorted)
150k
CPU
Max
Second (3-4 pin shorted)
100k
Level 7
Third (5-6 pin shorted)
75k
Level 6
Fourth (7-8 pin shorted)
56.2k
Level 5
Fifth (9-10 pin shorted)
39.2k
Level 4
Sixth (11-12 pin shorted)
30.1k
Level 3
Seventh (13-14 pin shorted)
24.3k
Level 2
Left(15-16 pin shorted)
20.0k
Min
F2806 DSP Program Mode Selection (J46)
The F2806 DSP Program Mode (GUI) Selection can be set by J46.
Default setting: No jumper shorts on J46 for normal operation
Table 7. F2806 DSP Program Mode Selection
Jumper Set to
6.1.7
Program Mode Selection
No jumper on J46
Normal operation
Jumper on J46
Flash the DSP program to the EVM
5Vin Bias Voltage Option (J41)
The 5-Vin bias voltage can be used from USB or externally.
Default setting: No jumper shorts on J41
Table 8. F2806 DSP Program Mode Selection
Jumper Set to
6.1.8
Program Mode Selection
No jumper
5-Vin Bias from J31 external
Jumper shorted
5-Vin Bias from USB, 5 Vin from J31 must not be connected
Onboard Dynamic Load Selection [S3 for CPU, S2 [Upper) for GPU, S2 (Lower) for VCCIO]
The onboard dynamic load can be set by S2 and S3.
Default setting: Push S2 and S3 to OFF position to disable the on board dynamic load.
Table 9. Onboard Dynamic Load Selection
26
Switch Set to
Dynamic Load Selection
Push S3 to ON position
Enable 32-A onboard dynamic load at CPU
Push S3 to OFF position
Disable 32-A onboard dynamic load at CPU
Push S2 (upper) to ON position
Enable 19-A onboard dynamic load at GPU
Push S2 (upper) to OFF position
Disable 19-A onboard dynamic load at GPU
Push S2 (lower) to ON position
Enable 10-A onboard dynamic load at VCCIO
Push S2 (lower) to OFF position
Disable 10-A onboard dynamic load at VCCIO
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6.1.9
IMVP-7 VR_ON Enable Selection (S4)
The IMVP-7 CPU/GPU can be enabled and disabled by S4.
Default setting: Push S4 to OFF position to disable both CPU and GPU.
Table 10. VR_ON Enable Selection
6.2
6.2.1
Switch Set to
VR_ON Selection
Push S4 to ON position
Enable IMVP-7 CPU/GPU Vcore
Push S4 to OFF position
Disable IMVP-7 CPU/GPU Vcore
1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration
VDDQ S3, S5 Enable Selection
The controller can be enabled and disabled by J26 and J27.
Default setting: Jumper shorts on Pin 2 and Pin 3 of J27,
Default setting: Jumper shorts on Pin 2 and Pin 3 of J26
Table 11. VDDQ S3, S5 Enable Selection
State
6.3
6.3.1
J26 (S3) Set to
J27 (S5) Set to
VDDQ
VTTREF
VTT
S0
ON position
ON position
ON
ON
ON
S3
OFF position
ON position
ON
ON
OFF (High-Z)
S4/S5
OFF position
OFF position
OFF (Discharge)
OFF (Discharge)
OFF (Discharge)
1.05V VCCIO Configuration
1.05V Enable Selection (S1)
1.05V enable can be set by S1.
Default setting: Push S1 to OFF position
6.3.2
VCCIO Output Voltage Selection (J23)
The VCCIO output voltage can be selected by J23.
Default setting: Jumper shorts pin 1 and pin 2 of J23
Table 12. VCCIO Output Voltage Selection
Jumper Set to
Selection
Jumper shorts on pin 1 and pin 2
VCCIO: 1.05 V
Jumper shorts on pin 2 and pin 3
VCCIO: 1.00 V
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Test Procedure
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7
Test Procedure
7.1
Line/Load Regulation and Efficiency Measurement Procedure
7.1.1
CPU
1. Set up EVM as described in Section 5.3, Section 5.4, Section 5.5, Section 5.6, and Figure 17.
2. Ensure no jumper shorts are on J46.
3. Ensure all other jumpers configuration settings in this section before 5Vin and 12VBAT are applied.
4. Ensure load is set to constant resistance mode and to sink 0 Adc.
5. Ensure S1 and S4 are in OFF position.
6. Add scope probe on the TP27 for CPU Vcore ripple measurement.
7. Ensure USB cable is connected between host computer and USB port (J42) on the EVM.
8. Increase 5Vin from 0 V to 5 V. Use V1 to measure 5Vin input voltage.
9. Increase 12VBAT from 0 V to 12 V. Use V2 to measure 12VBAT input voltage.
10. Double-click the TI-SVID-GUI_1_5_0_1.exe to launch the GUI program. The GUI window shown in
Figure 18 appears.
11. Push S4 to ON position to enable the VR_ON of TPS59640. VR_ON LED lights up.
12. Now you are ready to send SVID commends. The GUI at start-up defaults:
Address: 00 CPU, Commend: SetVIDslow, Payload: 1.05V
(The user can select the SVID commend by using the pulldown menu.)
13. Click send Commend, and the CPU CPGOOD LED lights up. See the GUI window as shown in
Figure 18.
14. Measure V3: CPU Vcore at J14 and A1: 12VBAT input current
15. Vary CPU LOAD from 0 Adc to 90 Adc. The CPU Vcore must remain in load line.
16. Vary 12VBAT from 9 V to 20 V. The CPU Vcore must remain in line regulation.
17. Push S4 to OFF position to disable CPU Vcore controller.
18. Decrease LOAD to 0 A, and disconnect the LOAD from terminal J1, J5, and J6.
19. Disconnect V3 from J14.
20. Disconnect scope probe from TP27.
28
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Figure 18. TPS59640EVM-751 CPU GUI Setup Window
7.1.2
GPU
Connect the LOAD to GPU terminal J11 and V3 at J16. Ensure correct polarity.
Add scope probe on the TP37 for GPU G_Vcore ripple measurement.
Push S4 to ON position to enable the VR_ON of TPS59640. The VR_ON LED lights up.
Now you are ready to send SVID commends for GPU. Using the pulldown menu:
Address: 01 GPU, Commend: SetVIDslow, Payload: 1.23V
5. Click send Commend, and GPU GPOOD LED lights up. See the GUI window shown Figure 19.
6. Measure V3: GPU G_Vcore at J16 and A1: 12VBAT input current.
7. Vary GPU LOAD from 0 Adc to 30 Adc; GPU Vcore must remain in load line.
8. Vary 12VBAT from 9 V to 20 V; GPU Vcore must remain in line regulation.
9. Push S4 to OFF position to disable GPU Vcore controller.
10. Decrease LOAD to 0 A, and disconnect the LOAD from terminal J11.
11. Disconnect V3 from J16.
12. Disconnect scope probe from TP37.
13. Exit SVID GUI window: click File → click Exit.
1.
2.
3.
4.
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Test Procedure
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14. Disconnect the USB cable between host Computer and EVM.
Figure 19. TPS59640EVM-751 GPU GUI Setup Window
7.1.3
1.
2.
3.
4.
5.
6.
7.
8.
VDDQ
Connect the LOAD to VDDQ terminal J28 and V3 at J29. Ensure correct polarity.
Remove jumper from J27 from pin 2 and pin 3, and put this jumper on pin 1 and pin 2 of J27 to enable
S5 of VDDQ controller. VDDQ PGOOD LED lights up.
Measure V3: VDDQ at J29 and A1: 12Vin input current
Vary VDDQ LOAD from 0 Adc to 15 Adc; VDDQ must remain in the load regulation.
Vary 12VBAT from 9 V to 20 V; VDDQ must remain in the line regulation.
Remove jumper off J27, and short back on pin 2 and pin 3 of J27 to disable VDDQ controller.
Decrease LOAD to 0 A, and disconnect the LOAD from terminal J28.
Disconnect V3 from J29.
7.1.4
VCCIO
1. Connect the LOAD to VCCIO terminal J24 and V3 at J25. Ensure correct polarity.
2. Push S1 to ON position to enable the VCCIO controller. VCCIO EN and PGOOD LEDs light up.
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3.
4.
5.
6.
7.
8.
7.2
Measure V3: VCCIO at J25 and A1: 12Vin input current.
Vary VDDQ LOAD from 0 Adc to 15 Adc; VCCIO must remain in the load regulation.
Vary 12VBAT from 9 V to 20 V; VCCIO must remain in the line regulation.
Push S1 to OFF position to disable VCCIO controller.
Decrease LOAD to 0 A, and disconnect the LOAD from terminal J24.
Disconnect V3 from J25.
Equipment Shutdown
1.
2.
3.
4.
Shut down
Shut down
Shut down
Shut down
load.
12VBAT and 5Vin.
oscilloscope.
host computer.
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Performance Data and Typical Characteristic Curves
8
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Performance Data and Typical Characteristic Curves
Figure 20 through Figure 91 present typical performance curves for TPS59640EVM-751. Jumpers are set
to default locations; see Section 6 of this user’s guide
8.1
CPU3-Phase Operation
95
1.1
VI = 9 V
SPEC (max)
VI = 12 V
90
1.05
20 Vin Vout (V)
IO - Output Voltage - V
9 Vin Vout (V)
Efficiency - %
85
VI = 20 V
80
75
12 Vin Vout (V)
0.95
SPEC (nom)
0.9
SPEC (min)
0.85
70
65
1
0
10
20
30 40 50 60 70
IO - Output Current - A
80
90
100
0.8
0
Figure 20. CPU3 Efficiency
Test condition: 12 Vin, 105 V 90 A
CPU 3 Phase operation
TPS59640EVM
CPU VDIO Turn on
10
20
30
40
50
60
70
80
90
100
IO - Output Current - A
Figure 21. CPU3 Load Regulation
TPS59640EVM
CPU VR_IO Turn off
Test condition: 12 Vin, 105 V 90 A
CPU 3 Phase operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH3: Vcore
CH4: CPGOOD
CH4: CPGOOD
Figure 22. CPU3 Enable Turnon
32
Figure 23. CPU3 Enable Turnoff
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TPS59640EVM
CPU Switching Node
Test condition: 12 Vin, 105 V 90 A
CPU 3 Phase operation
TPS59640EVM
Dynamic VID: Set VID-Set VID-Slow
Test condition: 12 Vin, 105 V-0.6 V, 0.5 A
CPU 2 Phase operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH3: VSW3
CH4: VDIO
CH4: Vcore Ripple
Figure 24. CPU3 Switching Node (Ripple)
TPS59640EVM
Dynamic VID: set VID-Fast/Set VID-Fast
Test condition: 12 Vin, 105 V-06 V, 0.5 A
CPU 2 Phase operation
Figure 25. CPU3 Dynamic VID: SetVID-Slow/Slow
TPS59640EVM
Dynamic VID: Set VID-Decay/Set VID-Fast
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH3: Vcore
CH4: VDIO
CH4: VDIO
Figure 26. CPU3 Dynamic VID:SetVID-Fast/Fast
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Test condition: 12 Vin, 105 V-0.6 V, 2 A
CPU 2 Phase operation
Figure 27. CPU3 Dynamic VID:SetVID-Decay/Fast
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Performance Data and Typical Characteristic Curves
TPS59640EVM
CPU Output Load Insertion with
OSR/USR = 20 k (Min)
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TPS59640EVM
CPU Output Load Release with
OSR/USR = 20 k (Min)
Test condition: 12 Vin, 105 V/0 A-51 A
CPU 3 Phase on board dynamic load
CH1: CSW1
Test condition: 12 Vin, 105 V/0 A-51 A
CPU 3 Phase on board dynamic load
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: VSW3
CH3: CSW3
CH4: Vcore
CH4: Vcore
Figure 28. CPU3 Output Load Insertion With
OSR/USR20k (Min)
Figure 29. CPU3 Output Load Release With OSR/USR
20k (Min)
Figure 30. CPU3 Bode Plot at 12Vin, 1.05 V/60 A
34
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Figure 31. CPU3 MOSFET
Figure 32. CPU3 IC
Test condition: CPU3 12Vin, 1.05 V/60 A, no airflow
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Performance Data and Typical Characteristic Curves
8.2
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CPU 2-Phase Operation
1.1
95
VI = 12 V
VI = 9 V
90
Efficiency - %
85
VO - Output Voltage - V
1.05
VI = 20 V
80
75
0.95
12 Vin Vout - V
20 Vin Vout - V
9 Vin Vout - V
0.9
70
65
0
1
5
10
15
20 25 30 35 40
IO - Output Current - A
45
50
55
0.85
0
Figure 33. CPU2 Efficiency
TPS59640EVM
CPU VDIO Turn on
SPEC - min
Test condition: 12 Vin, 105 V 50 A
CPU 2 Phase operation
SPEC - nom
SPEC - max
5
10
15
20 25 30 35 40
IO - Output Current - A
45
50
55
Figure 34. CPU2 Load Regulation
TPS59640EVM
CPU VR_ON Turn on
CH1: CSW1
Test condition: 12 Vin, 105 V 50 A
CPU 3 Phase operation
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH4: CPGOOD
Figure 35. CPU2 Enable Turnon
36
CH3: Vcore
CH4: CPGOOD
Figure 36. CPU2 Enable Turnoff
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TPS59640EVM
CPU Switching Node
Test condition: 12 Vin, 105 V 50 A
CPU 2 Phase operation
Test Condition: 12Vin,VID: 1.05V-0.6V, 0.5A
TPS59640EVM
CPU 2 Phase operation
Dynamic VID: Set VID-Slow/Set VID-Slow
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH4: VDIO
CH3: Vcore Ripple
Figure 37. CPU2 Switching Node (Ripple)
Test Condition: 12Vin,VID: 1.05V-0.6V, 0.5A
TPS59640EVM
CPU 2 Phase operation
Dynamic VID: Set VID-Fast/Set VID-Fast
Figure 38. CPU2 Dynamic VID: SetVID-Slow/Slow
Test Condition: 12Vin,VID: 1.05V-0.6V, 2A
TPS59640EVM
CPU 2 Phase operation
Dynamic VID: Set VID-Decay/Set VID-Fast
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: Vcore
CH3: Vcore
CH4: VDIO
CH4: VDIO
Figure 39. CPU2 Dynamic VID: SetVID-Fast/Fast
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Figure 40. CPU2 Dynamic VID: SetVID-Decay/Fast
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Performance Data and Typical Characteristic Curves
TPS59640EVM
CPU Output Load Insertion with
OSR/USR = 20 k - Min
Test Condition: 12Vin, 1.05V/0A
CPU 2-Phase on board dynamic load
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TPS59640EVM
CPU Output Load Release with
OSR/USR = 20 k - Min
Test Condition: 12Vin, 1.05V/0A-51A
CPU 2-Phase on board dynamic load
CH1: DYN_C
CH1: DYN_C
CH2: CSW1
CH2: CSW1
CH3: CSW2
CH3: CSW2
CH4: Vcore
CH4: Vcore
Figure 41. CPU2 Output Load Insertion With OSR/USR Figure 42. CPU2 Output Load Release With OSR/USR
20k (Min)
20k (Min)
Figure 43. CPU2 Bode Plot at 12Vin, 1.05 V/55 A
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Figure 44. CPU2 MOSFET
Figure 45. CPU2 IC
Test condition: CPU2 12Vin, 1.05 V/55 A, no airflow
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Performance Data and Typical Characteristic Curves
8.3
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CPU 1-Phase Operation
1.1
95
VI = 9 V
VI = 12 V
1.05
VO - Output Voltage - V
Efficiency - %
90
85
VI = 20 V
80
1
12 Vin Vout - V
20 Vin Vout - V
0.95
9 Vin Vout - V
75
SPEC - min
SPEC - nom
SPEC - max
70
0.9
0
5
10
15
20
25
IO - Output Current - A
30
35
Figure 46. CPU1 Efficiency
TPS59640EVM
CPU VDIO Turn on
Test Condition: 12Vin, 1.05V/0A
CPU 1 Phase operation
0
5
10
15
20
25
IO - Output Current - A
30
35
Figure 47. CPU1 Load Regulation
TPS59640EVM
CPU VR_ON Turn off
CH1: VDIO
Test Condition: 12Vin, 1.05V/20A
CPU 1 Phase operation
CH1: VR_ON
CH2: CSW1
CH2: CSW1
CH3: Vcore
CH3: Vcore
CH4: CPGOOD
CH4: CPGOOD
Figure 48. CPU1 Enable Turnon
40
Figure 49. CPU1 Enable Turnoff
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TPS59640EVM
CPU Switching Node
Test Condition: 12Vin, 1.05V/30A
CPU 1 Phase operation
TPS59640EVM
CPU Output Ripple
Test Condition: 12Vin, 1.05V/30A
CPU 1 Phase operation
CH1: CSW1
CH1: CSW1
CH2: Vcore Ripple
Figure 50. CPU1 Switching Node
TPS59640EVM
Test Condition:12Vin,VID:1.05V-0.6V, 0.5A
Dynamic VID: Set VID-Slow/Set VID-Slow
CPU 1 Phase operation
TPS59640EVM
Dynamic VID:Set VID-Fast/Set VID-Fast
Test Condition: 12Vin,VID: 1.05V-0.6V,0.5A
CPU 1 Phase operation
CH1: VDIO
CH1: VDIO
CH2: CSW1
CH2: CSW1
CH3: Vcore
CH3: Vcore
CH4: CPGOOD
CH4: CPGOOD
Figure 52. CPU1 Dynamic VID: SetVID-Slow/Slow
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Figure 51. CPU1 Switching Node and Ripple
Figure 53. CPU1 Dynamic VID: SetVID-Fast/Fast
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Performance Data and Typical Characteristic Curves
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TPS59640EVM
CPU Output Load Insertion with
OSR/USR = 20 k - Min
Test Condition: 12Vin,VID: 0.6V-1.05V, 0.5A
TPS59640EVM
CPU 1 Phase operation
Dynamic VID: Set VID-Fast/Set VID-Decay
Test Condition: 12Vin, 1.05V/0A-32A
CPU 1-Phase on board dynamic load
CH1: VDIO
CH1: DYN_C
CH2: CSW1
CH2: CSW1
CH3: Vcore
CH4: Vcore
CH4: CPGOOD
Figure 54. CPU1 Dynamic VID: SetVID-Decay/Fast
TPS59640EVM
CPU Output Load Release with
OSR/USR = 20 k - Min
Figure 55. CPU1 Output Load Insertion With OSR/USR
20k (Min)
Test Condition: 12Vin, 1.05V/0A-32A
CPU 2-Phase on board dynamic load
CH1: DYN_C
CH2: CSW1
CH4: Vcore
Figure 56. CPU1 Output Load Release With OSR/USR 20k (Min)
42
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Figure 57. CPU1 Bode Plot at 12Vin, 1.05 V/33 A
Figure 58. CPU1 MOSFET
Figure 59. CPU1 IC
Test condition: CPU1 12Vin, 1.05 V/33 A, no airflow
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Performance Data and Typical Characteristic Curves
8.4
www.ti.com
GPU Operation
95
1.3
VI = 9 V
VI = 12 V
85
1.25
VO - Output Voltage - V
Efficiency - %
90
VI = 20 V
80
1.15
75
70
1.2
12 Vin Vout - V
20 Vin Vout - V
9 Vin Vout - V
1.1
SPEC - min
SPEC - nom
SPEC - max
0
5
10
15
20
25
IO - Output Current - A
30
35
1.05
0
Figure 60. GPU Efficiency
TPS59640EVM
CPU VDIO Turn on
Test Condition: 12Vin, 1.23V/20A
CPU operation
5
30
35
Figure 61. GPU Load Regulation
TPS59640EVM
GPU VR_ON Turn off
Test Condition: 12Vin, 1.23V/20A
GPU operation
CH1: VR_ON
CH1: VDIO
CH2: GSW
CH2: GSW
CH3: G_Vcore
CH3: G_Vcore
CH4: GPGOOD
CH4: GPGOOD
Figure 62. GPU Enable Turnon
44
10
15
20
25
IO - Output Current - A
Figure 63. GPU Enable Turnoff
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TPS59640EVM
GPU Switching Node
Test Condition: 12Vin, 1.23V/30A
GPU operation
TPS59640EVM
GPU Output Ripple
Test Condition: 12Vin, 1.23V/30A
GPU operation
CH1: GSW
CH1: GSW
CH2: G_Vcore Ripple
Figure 64. GPU Switching Node
TPS59640EVM
Test Condition:12Vin,VID: 1.23V-0.6V, 0.5A
Dynamic VID: Set VID-Slow/Set VID-Slow
GPU 2 Phase operation
TPS59640EVM
Dynamic VID: Set VID-Fast/Set VID-Fast
Test Condition: 12Vin,VID: 1.23V-0.6V, 0.5A
GPU operation
CH1: VDIO
CH1: VDIO
CH2: GSW
CH2: GSW
CH3: G_Vcore
CH3: G_Vcore
CH4: GPGOOD
CH4: GPGOOD
Figure 66. GPU Dynamic VID: SetVID-Slow/Slow
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Figure 65. GPU Switching Node and Ripple
Figure 67. GPU Dynamic VID: SetVID-Fast/Fast
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Performance Data and Typical Characteristic Curves
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TPS59640EVM
GPU Output Load Insertion with
OSR/USR = 20 k - Min
TPS59640EVM
Test Condition: 12Vin,VID: 0.6V-1.23V,0.5A
Dynamic VID: Set VID-Fast/Set VID-Decay
GPU operation
Test Condition: 12Vin,1.23V/0A-24A
GPU on board dynamic load
CH1: VDIO
CH1: DYN_G
CH2: GSW
CH2: GSW
CH3: G_Vcore
CH4: G_Vcore
CH4: GPGOOD
Figure 68. GPU Dynamic VID: SetVID-Decay/Fast
TPS59640EVM
GPU Output Load Release with
OSR/USR = 20 k - Min
Figure 69. GPU Output Load Insertion With OSR/USR
20k (Min)
Test Condition: 12Vin,1.23V/0A-24A
GPU on board dynamic load
CH1: DYN_G
CH2: GSW
CH4: G_Vcore
Figure 70. GPU Output Load Release With OSR/USR 20k (Min)
46
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Figure 71. GPU Bode Plot at 12Vin, 1.23 V/33 A
Figure 72. GPU MOSFET
Figure 73. GPU IC
Test condition: GPU 12Vin, 1.23 V/33 A, no airflow
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Performance Data and Typical Characteristic Curves
8.5
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1.05V VCCIO
100
90
1.08
VI = 9 V
80
VI = 12 V
VI = 20 V
VO - Output Voltage - V
Efficiency - %
70
60
50
40
30
VI = 12 V
1.06
VI = 9 V
VI = 20 V
1.04
20
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
100
1.02
0
Figure 74. 1.05-V Efficiency
TPS59640EVM
VCCIO Output Start up
Test Condition: 12Vin, 1.05V/15A
CH1: VCCIO_EN
2
4
14
16
Figure 75. 1.05-V Load Regulation
TPS59640EVM
VCCIO Output Enable Shutdown
Test Condition: 12Vin, 1.05V/15A
CH1: VCCIO_EN
CH2: VCCIO
CH3: VCCIO_PG
Figure 76. 1.05-V Enable Turnon
48
6
8
10
12
IO - Output Current - A
CH2: VCCIO
CH3: VCCIO_PG
Figure 77. 1.05-V Enable Turnoff
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TPS59640EVM
VCCIO Switching Node
Test Condition: 12Vin, 1.05V/15A
TPS59640EVM
VCCIO Output Ripple
Test Condition: 12Vin, 1.05V/15A
CH1: VCCIO_SW
CH1: VCCIO Output Ripple
Figure 78. 1.05-V Switching Node
TPS59640EVM
VCCIO Output Transient from
DCM to CCM
Test Condition: 12Vin, 1.05V/0A-10A
CH1: VCCIO Output Voltage
TPS59640EVM
VCCIO Output Transient from
CCM to DCM
Test Condition: 12Vin, 1.05V/10A-0A
CH1: VCCIO Output Voltage
CH4: VCCIO Output Current
CH4: VCCIO Output Current
Figure 80. 1.05-V Transient DCM to CCM
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Figure 79. 1.05-V Ripple
Figure 81. 1.05-V Transient CCM to DCM
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Performance Data and Typical Characteristic Curves
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Figure 82. TPS51219 Thermal
Test condition: 12Vin, 1.05 V/15 A, no airflow
50
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8.6
1.2 VDDQ
1.26
100
VI = 9 V
90
1.24
VI = 12 V
Efficiency - %
70
VO - Output Voltage - V
80
VI = 20 V
60
50
40
30
20
VI = 12 V
1.22
VI = 20 V
1.20
VI = 9 V
1.18
1.16
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
Figure 83. 1.2-V Efficiency
TPS59640EVM
VDDQ Output S5 Start up
1.14
0
2
4
6
8
10
12
IO - Output Current - A
14
16
Figure 84. 1.2-V Load Regulation
Test Condition: 12Vin, 1.2V/15A
TPS59640EVM
VDDQ Output S5 Shutdown
Test Condition: 12Vin, 1.2V/15A
CH1: VDDQ S5
CH1: VDDQ S5
CH2: VTTREF
CH2: VTTREF
CH3: VDDQ
CH3: VDDQ
CH4: VDDQ_PG
CH4: VDDQ_PG
Figure 85. 1.2-V Enable Turnon
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Figure 86. 1.2-V Enable Turnoff
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Performance Data and Typical Characteristic Curves
TPS59640EVM
VDDQ Output Switching Node
Test Condition: 12Vin, 1.2V/15A
CH1: VDDQ SW
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TPS59640EVM
VDDQ Output Ripple
CH1: VDDQ Output Ripple
Figure 87. 1.2-V Switching Node
TPS59640EVM
VDDQ Output Transient from
DCM to CCM
Test Condition: 12Vin, 1.2V/0A-10A
Figure 88. 1.2-V Ripple
TPS59640EVM
VDDQ Output Transient from
CCM to DCM
CH1: VDDQ Output Voltage
CH1: VDDQ Output Voltage
CH4: VDDQ Output Current
CH4: VDDQ Output Current
Figure 89. 1.2-V Transient DCM to CCM
52
Test Condition: 12Vin, 1.2V/15A
Test Condition: 12Vin, 1.2V/0A-10A
Figure 90. 1.2-V Transient CCM to DCM
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Figure 91. TPS51916 Thermal
Test condition: 12Vin, 1.2 V/15 A, no airflow
9
EVM Assembly Drawings and PCB layout
The following figures (Figure 92 through Figure 101) show the design of the TPS59640EVM-751
printed-circuit board. The EVM has been designed using an eight-layer circuit board with 2 oz o0f copper
on outside layers.
TEXAS
INSTRUMENTS
Figure 92. TPS59640EVM-751 Top Layer Assembly Drawing (Top View)
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EVM Assembly Drawings and PCB layout
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Figure 93. TPS59640EVM-751 Bottom Assembly Drawing (Bottom View)
Figure 94. TPS59640EVM-751 Top Copper
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Figure 95. TPS59640EVM-751 Bottom Copper
Figure 96. TPS59640EVM-751 Internal Layer 2
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EVM Assembly Drawings and PCB layout
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Figure 97. TPS59640EVM-751 Internal Layer 3
Figure 98. TPS59640EVM-751 Internal Layer 4
56
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Figure 99. TPS59640EVM-751 Internal Layer 5
Figure 100. TPS59640EVM-751 Internal Layer 6
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EVM Assembly Drawings and PCB layout
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Figure 101. TPS59640EVM-751 Internal Layer 7
58
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10
Bill of Materials
The EVM major components list according to the schematics shown in Figure 3 to Figure 15.
Table 13. Bill of Materials
QTY
RefDes
Description
MFR
Part Number
3
C1, C28, C163
Capacitor, Ceramic, 220nF, 25V, X7R, 10%, 0603
STD
STD
29
C119,
C180,
C192,
C201,
C211,
C215,
C219,
C164,
Capacitor, Ceramic, 0.1uF, 25V, X7R, 10%, 0603
C191,
C199,
C210,
C214,
C218,
C222, C223
STD
STD
10
C12, C13, C33, C71, C113,
Capacitor, Ceramic, 1nF, 50V, X7R, 10%, 0603
C118, C124, C155, C176, C195
STD
STD
2
C14, C26
Capacitor, Ceramic, 100pF, 50V, C0G, 10%, 0603
STD
STD
1
C16
Capacitor, Ceramic, 0.33uF, 25V, X7R, 10%, 0603
STD
STD
1
C160
Capacitor, Ceramic, 2.2uF, 25V, X7R, 10%, 0805
STD
STD
12
C17, C23, C24, C34, C73,
C187, C188, C190, C194,
C200, C225, C226
Capacitor, Ceramic, 1uF, 25V, X7R, 10%, 0603
STD
STD
4
C18, C19, C20, C21
Capacitor, Aluminum, 2.0V, 470uF, 4mohm, 20%, D2T
Sanyo
2TPLF470M4E
5
C186, C189, C207, C208, C125 Capacitor, Ceramic, 0.01uF, 25V, X7R, 10%, 0603
STD
STD
2
C197, C198
Capacitor, Ceramic, 10pF, 50V, C0G, 10%, 0603
STD
STD
6
C2, C38, C76, C127, C162,
C184
Capacitor, Ceramic, 2.2uF, 25V, X7R, 10%, 0603
STD
STD
2
C205, C206
Capacitor, Ceramic, 22pF, 50V, C0G, 5%, 0603
STD
STD
C120,
C182,
C193,
C202,
C212,
C216,
C220,
C156,
C185,
C196,
C209,
C213,
C217,
C221,
1
C3
Capacitor, Ceramic, 4.7uF, 25V, X7R, 10%, 0805
STD
STD
40
C39, C40, C41, C42, C43, C44, Capacitor, Ceramic, 22uF, 6.3V, X5R, 10%, 0805
C45, C47, C51, C52, C53, C54,
C55, C56, C57, C58, C81, C82,
C83, C84, C85, C86, C87, C88,
C89, C90, C95, C96, C128,
C132, C133, C135, C137,
C138, C140, C141, C142,
C143, C144, C146
STD
STD
24
C4, C5, C6, C7, C8, C9, C10,
Capacitor, Ceramic, 10uF, 25V, X7R, 20%, 1206
C11, C29, C30, C31, C32, C67,
C68, C69, C70, C114, C115,
C116, C117, C151, C152,
C153, C154
STD
STD
20
C46, C48, C59, C60, C61, C62, Capacitor, Ceramic, 10uF, 6.3V, X5R, 10%, 0805
C63, C64, C65, C66, C165,
C166, C167, C168, C170,
C172, C157, C177, C181, C183
STD
STD
5
C72, C74, C121, C122, C158
Capacitor, Aluminum, 2.0V, 330uF, 2mohm, 20%, 7343
Sanyo
2TPF330M6
4
C98, C102, C106, C110
Capacitor, Ceramic, 33nF, 25V, X7R, 10%, 0603
STD
STD
8
D1, D2, D3, D9, D10, D12,
D13, D14
Diode, LED, Green Clear, 20mcd, 0.079x0.049
Lite On
LTST-C170GKT
5
D4, D5, D7, D8, D11
Diode, LED, Red Clear, 20mcd, 0.079x0.049
Lite On
LTST-C170CKT
1
D6
Diode, Schottky, 200mA, 30V, SOT-23,
Vishay-Liteon
BAT54-V-GS08
1
FB1
Bead, SMD, Ferrite, 100MHz Max, 200mA, +/-25%, 0603
WE
74279266A
4
L1, L2, L3, L4
Inductor, SMT, 0.36uH, 35A , 0.82mohm, 10x11.5mm
Toko
FCUL1040-H-R36M
2
L5, L6
Inductor, SMT, 0.56uH, 32A , 1.3mohm, 10x11.2mm
Toko
FDUE1040J-H-R56M
6
Q1, Q2, Q3, Q4, Q7, Q9
MOSFET, Synchronous Buck NexFET Power Block SON 5X6mm
TI
CSD87350Q5D
4
Q10, Q11, Q12, Q13
MOSFET, Nchan, 25V, 31A, 2.5mohm, QFN5X6mm
TI
CSD16407Q5
1
Q14
MOSFET, Pchan, -60V, -0.33A, 2ohm, SOT23
Infineon
BSS83P
6
Q5, Q6, Q8, Q15, Q16, Q17
MOSFET, Nchan, 100V, 0.17A, 6ohm, SOT23
Fairchild
BSS123
1
R1
Resistor, Chip, 71.5k, 1/10W, 1%, 0603
STD
STD
7
R119, R120, R136, R203,
R204, R205, R209
Resistor, Chip, 180, 1/10W, 1%, 0603
STD
STD
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Bill of Materials
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Table 13. Bill of Materials (continued)
QTY
60
MFR
Part Number
19
RefDes
R12, R13, R26, R30, R34, R42, Resistor, Chip, 0, 1/10W, 1%, 0603
R43, R54, R57, R129, R131,
R133, R134, R145, R146,
R148, R150, R219, R220
Description
STD
STD
5
R121, R123, R140, R200, R207 Resistor, Chip, 1.00k, 1/10W, 1%, 0603
STD
STD
14
R122,
R147,
R201,
R217,
Resistor, Chip, 10.0k, 1/10W, 1%, 0603
STD
STD
1
R128
Resistor, Chip, 10.5k, 1/10W, 1%, 0603
STD
STD
2
R130, R141
Resistor, Chip, 37.4k, 1/10W, 1%, 0603
STD
STD
1
R14
Resistor, Chip, 169k, 1/10W, 1%, 0603
STD
STD
1
R151
Resistor, Chip, 15.0k, 1/10W, 1%, 0603
STD
STD
4
R153, R223, R224, R225
Resistor, Chip, 2.00k, 1/10W, 1%, 0603
STD
STD
1
R156
Resistor, Chip, 51.1k, 1/10W, 1%, 0603
STD
STD
1
R157
Resistor, Chip, 1, 1/10W, 1%, 0603
STD
STD
3
R158, R159, R160
Resistor, Chip, 1, 1/10W, 1%, 0805
STD
STD
7
R16, R71, R72, R73, R95, R96, Resistor, Chip, 150k, 1/18W, 1%, 0603
R97
STD
STD
3
R161, R162, R167
Resistor, Chip, 0.01, 1W, 2512
STD
STD
5
R163, R164, R166, R168, R169 Resistor, Chip, 0.05, 1W, 2512
STD
STD
1
R165
Resistor, Chip Array, 10.0k, 62.5mW, 5%, 1206
Yageo
TC164-JR-0710KL
3
R17, R181, R194
Resistor, Chip, 10.0k, 1/16W, 1%, 0402
STD
STD
1
R170
Resistor, Chip, 8.06k, 1/10W, 1%, 0603
STD
STD
2
R172, R175
Resistor, Chip, 0.005, 1W, 2512
STD
STD
5
R176, R177, R178, R179, R199 Resistor, Chip, 330, 1/10W, 1%, 0603
STD
STD
8
R180, R182, R183, R184,
R188, R189, R195, R196
Resistor, Chip, 1M, 1/16W, 1%, 0402
STD
STD
1
R186
Resistor, Chip, 100, 1/10W, 1%, 0603
STD
STD
2
R192, R193
Resistor, Chip, 3.01k, 1/10W, 1%, 0603
STD
STD
7
R2, R40, R47, R53, R59, R132, Resistor, Chip, 10, 1/10W, 1%, 0603
R135
STD
STD
1
R21
Resistor, Chip, 200k, 1/10W, 1%, 0603
STD
STD
1
R211
Resistor, Chip, 75, 1/10W, 1%, 0603
STD
STD
1
R212
Resistor, Chip, 130, 1/10W, 1%, 0603
STD
STD
1
R213
Resistor, Chip, 43.2, 1/10W, 1%, 0603
STD
STD
1
R214
Resistor, Chip, 1.50k, 1/10W, 1%, 0603
STD
STD
2
R215, R216
Resistor, Chip, 33.2, 1/10W, 1%, 0603
STD
STD
1
R22
Resistor, Chip, 4.12k, 1/10W, 1%, 0603
STD
STD
2
R221, R226
Resistor, Chip, 475, 1/10W, 1%, 0603
STD
STD
1
R222
Resistor, Chip, 2.21k, 1/10W, 1%, 0603
STD
STD
1
R227
Resistor, Chip, 2.74k, 1/10W, 1%, 0603
STD
STD
1
R24
Resistor, Chip, 309k, 1/10W, 1%, 0603
STD
STD
1
R3
Resistor, Chip, 54.9, 1/16W, 1%, 0402
STD
STD
4
R35, R44, R55, R65
Resistor, Chip, 17.8k, 1/8W, 1%, 0805
STD
STD
12
R36, R41, R45, R52, R56, R64, Resistor, Chip, 0, 1/16W, 1%, 0402
R66, R70, R190, R191, R197,
R198
STD
STD
4
R38, R50, R62, R68
Resistor, Chip, 162k, 1/10W, 1%, 0603
STD
STD
4
R39, R51, R63, R69
Resistor, Chip, 28.7k, 1/10W, 1%, 0603
STD
STD
1
R4
Resistor, Chip, 130, 1/16W, 1%, 0402
STD
STD
1
R6
Resistor, Chip, 8.45k, 1/10W, 1%, 0603
STD
STD
1
R7
Resistor, Chip, 42.2k, 1/10W, 1%, 0603
STD
STD
8
R74, R75, R76, R98, R99,
R100, R152, R173
Resistor, Chip, 100k, 1/10W, 1%, 0603
STD
STD
R137, R138, R139,
R171, R174, R187,
R202, R206, R208,
R218
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Table 13. Bill of Materials (continued)
QTY
RefDes
Description
MFR
Part Number
6
R77, R78, R79, R101, R102,
R103
Resistor, Chip, 75.0k, 1/10W, 1%, 0603
STD
STD
2
R8, R23
Resistor, Chip, 15.4k, 1/10W, 1%, 0603
STD
STD
6
R80, R81, R82, R104, R105,
R106
Resistor, Chip, 56.2k, 1/10W, 1%, 0603
STD
STD
6
R83, R84, R85, R107, R108,
R109
Resistor, Chip, 39.2k, 1/10W, 1%, 0603
STD
STD
8
R86, R87, R88, R110, R111,
R112, R154, R155
Resistor, Chip, 30.1k, 1/10W, 1%, 0603
STD
STD
6
R89, R90, R91, R113, R114,
R115
Resistor, Chip, 24.3k, 1/10W, 1%, 0603
STD
STD
12
R9, R11, R15, R19, R27, R28,
R31, R33, R124, R125, R142,
R143,
Resistor, Chip, 2.21, 1/10W, 1%, 0603
STD
STD
7
R92, R93, R94, R116, R117,
R118, R149
Resistor, Chip, 20.0k, 1/10W, 1%, 0603
STD
STD
6
RT1, RT2, RT3, RT4, RT5, RT6 NTC Thermistor, 100k, 0603, 5%
Murata
NCP18WF104J03RB
1
U1
IC, 3+1 phase, IMVP-7 VCORE CPU and GPU Controller, QFN-48
TI
TPS59640RSL
1
U11
IC, Timer, Low-Power CMOS, SO-8
TI
TLC555CDR
1
U12
IC, Dual 10 ohm SPDT Analogy Switch, DGS_10P
TI
TS5A23157DGS
1
U13
IC, Nano Power, Open output comparators, PW14
TI
TLV3404IPW
1
U14
IC, USB to series port controller, QFN-32
TI
TUSB3410RHB
1
U15
IC, CMOS programmable controller, QFP-100
TI
TMS320F2806PZS
2
U16, U18
IC, Dual Schmitt-trigger inverter, DCK-6
TI
SN74LVC2G07DCK
1
U17
IC, Dual-bit dual-supply bus transceiver, RSW-10
TI
SN74AVC2T245RSW
2
U2, U3
IC, Dual high voltage, efficient synchronous MOSFET buck driver,
QFN-8
TI
TPS51601ADRB
1
U4
IC, High performance, single synchronous step down controller,
QFN-16
TI
TPS51219RTE
1
U5
IC, Complete DDR2, DDR3 and DDR3L memory power solution,
QFN-20
TI
TPS51916RUK
1
U6
IC, Dual low dropout regulator, 500mA and 250mA outputs, PWP20
TI
TPS70102PWP
1
U7
IC, 150mA, low Iq, wide bandwidth, LDO, SC70
TI
TPS71712DCK
1
U8
IC, Quadruple 2-input positive –AND gates, SO-14
TI
SN74HC08D
2
U9, U10
IC, Dual 4A High speed low side power MOSFET drivers, SO-8
TI
UCC27324D
1
X1
Crystal, controlled oscillators, 0.150”x0.528”
ABRACON
ABLS-20.000MHZ-B2-T
1
Y1
Crystal, controlled oscillators, 0.150”x0.528”
ABRACON
ABLS-12.000MHZ-B2-T
0
XU1
Socket, CPU
Molex
rPGA989
SLUU796 – January 2012
Submit Documentation Feedback
Using the TPS59640EVM-751 IMVP-7, 3-Phase CPU/1-Phase GPU SVID
Power System
Copyright © 2012, Texas Instruments Incorporated
61
Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding
electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the
technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY
SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING
ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to
take any and all appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER
FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the
product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s
environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and
can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15
of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this
equipment in other environments may cause interference with radio communications, in which case the user at his own expense
will be required to take whatever measures may be required to correct this interference.
EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 0 V to 20 V and the output voltage range of 0 V to 1.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 80°C. The EVM is designed to
operate properly with certain components above 80°C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety and environmental measures typically found in end products that incorporate such semiconductor
components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding
electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the
technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY
SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING
ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all
claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to
take any and all appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER
FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of
patents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the
product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s
environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and
can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15
of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this
equipment in other environments may cause interference with radio communications, in which case the user at his own expense
will be required to take whatever measures may be required to correct this interference.
EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of 0 V to 20 V and the output voltage range of 0 V to 1.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 80°C. The EVM is designed to
operate properly with certain components above 80°C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
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【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
2.
3.
4.
You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even
if the EVM should fail to perform as described or expected.
You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.
Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives
harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in
connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.
Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
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