User's Guide
SLUU896 – March 2012
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase
CPU/2-Phase GPU SVID Power System
The TPS59650EVM-753 evaluation module (EVM) is a complete solution for Intel™ IMVP7 Serial
VID(SVID) Power System from a 9V-20V input bus. This EVM uses the TPS59650 for IMVP7 - 3-Phase
CPU and 2-Phase GPU Vcore controller, the TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4
Memory rail (1.2VDDQ, 0.6VTT and 0.6VTTREF) and also uses the (CSD87350Q5D) a 5mm x 6mm TI’s
power block MOSFETs that uses Powerstack™ technology with high-side and low-side MOSFETs for high
power density and superior thermal performance.
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Contents
Description ................................................................................................................... 5
1.1
Typical Applications ................................................................................................ 5
1.2
Features ............................................................................................................. 5
TPS59650EVM-753 Power System Block Diagram .................................................................... 6
Electrical Performance Specifications .................................................................................... 7
Test Setup ................................................................................................................... 8
4.1
Test Equipment ..................................................................................................... 8
4.2
Recommended Wire Gauge ...................................................................................... 9
4.3
Recommended Test Setup ....................................................................................... 9
4.4
USB Cable Connections ......................................................................................... 10
4.5
Input Connections ................................................................................................ 10
4.6
Output Connections .............................................................................................. 11
Configuration ............................................................................................................... 11
5.1
CPU and GPU Configuration ................................................................................... 11
5.2
1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration ...................................................... 13
5.3
1.05V VCCIO Configuration ..................................................................................... 13
Test Procedure ............................................................................................................ 14
6.1
Line/Load Regulation and Efficiency Measurement Procedure ............................................ 14
6.2
Equipment Shutdown ............................................................................................ 17
Performance Data and Typical Characteristic Curves ................................................................ 18
7.1
CPU 3-Phase Operation ......................................................................................... 18
7.2
CPU 2-Phase Operation ......................................................................................... 21
7.3
CPU1-Phase Operation .......................................................................................... 25
7.4
GPU 2 Phase Operation ......................................................................................... 29
7.5
GPU 1 Phase Operation ......................................................................................... 32
7.6
1.05V VCCIO ...................................................................................................... 36
7.7
1.2V VDDQ ........................................................................................................ 39
EVM Assembly Drawings and PCB Layout ............................................................................ 42
Bill of Materials ............................................................................................................. 47
Schematics ................................................................................................................. 50
List of Figures
1
TPS59650EVM-753 Power System Block Diagram .................................................................... 6
2
TPS59650EVM-753 EVM Illustration ..................................................................................... 7
Powerstack is a trademark of Texas Instruments.
Intel is a trademark of Intel.
All other trademarks are the property of their respective owners.
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USB Cable ................................................................................................................... 8
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TPS59650EVM-753 Recommended Test Set Up ..................................................................... 10
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TPS59650EVM-753 CPU GUI set up Window ........................................................................ 15
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TPS59650EVM-753 GPU GUI set up Window ........................................................................ 16
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CPU3 Efficiency
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CPU3 Load regulation .................................................................................................... 18
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CPU3 Enable Turn on
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CPU3 Enable Turn off
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...........................................................................................................
....................................................................................................
....................................................................................................
CPU3 Switching Node(Ripple) ..........................................................................................
CPU3 Dynamic VID: SetVID-Slow/Slow ................................................................................
CPU3 Dynamic VID:SetVID-Fast/Fast .................................................................................
CPU3 Dynamic VID:SetVID-Decay/Fast ...............................................................................
CPU3 Output Load Insertion with OSR/USR middle level ..........................................................
CPU3 Output Load Release with OSR/USR middle level............................................................
CPU3 Bode Plot at 12Vin, 1.05V/60A ..................................................................................
CPU3 MOSFET ...........................................................................................................
CPU3 IC ....................................................................................................................
CPU2 Efficiency ...........................................................................................................
CPU2 Load regulation ....................................................................................................
CPU2 Enable Turn on ....................................................................................................
CPU2 Enable Turn off ....................................................................................................
CPU2 Switching Node(Ripple) ..........................................................................................
CPU2 Dynamic VID: SetVID-Slow/Slow ................................................................................
CPU2 Dynamic VID:SetVID-Fast/Fast .................................................................................
CPU2 Dynamic VID:SetVID-Decay/Fast ...............................................................................
CPU2 Output Load Insertion with OSR/USR middle level ..........................................................
CPU2 Output Load Release with OSR/USR middle level............................................................
CPU2 Bode Plot at 12Vin, 1.05V/55A ..................................................................................
CPU2 MOSFET ...........................................................................................................
CPU2 IC ....................................................................................................................
CPU1 Efficiency ...........................................................................................................
CPU1 Load regulation ....................................................................................................
CPU1 Enable Turn on ....................................................................................................
CPU1 Enable Turn off ....................................................................................................
CPU1 Switching Node ...................................................................................................
CPU1 Switching node and Ripple ......................................................................................
CPU1 Dynamic VID:SetVID-Slow/Slow ................................................................................
CPU1 Dynamic VID:SetVID-Fast/Fast .................................................................................
CPU1 Dynamic VID:SetVID-Decay/Fast ...............................................................................
CPU1 Output Load Insertion with OSR/USR middle level ..........................................................
CPU1 Output Load Release with OSR/USR middle level............................................................
CPU1 Bode Plot at 12Vin, 1.05V/33A ..................................................................................
CPU1 MOSFET ...........................................................................................................
CPU1 IC ....................................................................................................................
GPU2 Efficiency ..........................................................................................................
GPU2 Load regulation ....................................................................................................
GPU2 Enable Turn on ...................................................................................................
GPU2 Enable Turn off ...................................................................................................
GPU2 Switching Node and Ripple .....................................................................................
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GPU2 Dynamic VID:SetVID-Fast/Fast .................................................................................
GPU2 Dynamic VID:SetVID-Decay/Fast ...............................................................................
GPU2 Output Load Insertion with OSR/USR OFF ...................................................................
GPU2 Output Load Release with OSR/USR OFF ....................................................................
GPU2 Bode Plot at 12Vin, 1.23V/50A ..................................................................................
GPU2 MOSFET ...........................................................................................................
GPU2 IC ....................................................................................................................
GPU1 Efficiency ..........................................................................................................
GPU1 Load regulation ....................................................................................................
GPU1 Enable Turn on ...................................................................................................
GPU1 Enable Turn off ...................................................................................................
GPU1 Switching Node ...................................................................................................
GPU1 Switching Node and Ripple .....................................................................................
GPU1 Dynamic VID:SetVID-Slow/Slow ................................................................................
GPU1 Dynamic VID:SetVID-Fast/Fast .................................................................................
GPU1 Dynamic VID:SetVID-Decay/Fast ..............................................................................
GPU1 Output Load Insertion with OSR/USR OFF ....................................................................
GPU1 Output Load Release with OSR/USR OFF ....................................................................
GPU1 Bode Plot at 12Vin, 1.23V/33A ..................................................................................
GPU1 MOSFET ...........................................................................................................
GPU1 IC ....................................................................................................................
1.05V Efficiency ...........................................................................................................
1.05V Load regulation ....................................................................................................
1.05V Enable Turn on ....................................................................................................
1.05V Enable Turn off ....................................................................................................
1.05V Switching Node ...................................................................................................
1.05V Ripple ...............................................................................................................
1.05V Transient DCM TO CCM .........................................................................................
1.05V Transient CCM to DCM ...........................................................................................
TPS51219 Thermal........................................................................................................
1.2V Efficiency ............................................................................................................
1.2V Load regulation ......................................................................................................
1.2V Enable Turn on .....................................................................................................
1.2V Enable Turn off .....................................................................................................
1.2V Switching Node .....................................................................................................
1.2V Ripple .................................................................................................................
1.2V Transient DCM TO CCM ..........................................................................................
1.2V Transient CCM to DCM ............................................................................................
TPS51916 Thermal........................................................................................................
TPS59650EVM-753 Top Layer Assembly Drawing (Top view) .....................................................
TPS59650EVM-753 Bottom Assembly Drawing (Bottom view) .....................................................
TPS59650EVM-753 Top Copper .......................................................................................
TPS59650EVM-753 Bottom Copper ...................................................................................
TPS59650EVM-753 Internal Layer 2 ..................................................................................
TPS59650EVM-753 Internal Layer 3 ..................................................................................
TPS59650EVM-753 Internal Layer 4 ..................................................................................
TPS59650EVM-753 Internal Layer 5 ...................................................................................
GPU2 Dynamic VID:SetVID-Slow/Slow
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TPS59650EVM-753 Internal Layer 6 ................................................................................... 46
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TPS59650EVM-753 Internal Layer 7 ................................................................................... 46
List of Tables
1
TPS59650EVM-753 Electrical Performance Specifications ........................................................... 7
2
Current Limit Trip Selection .............................................................................................. 11
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CPU Frequency Selection ................................................................................................ 11
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GPU Frequency Selection
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F2808 DSP Program Mode Selection ..................................................................................
5Vin Bias Voltage Option (J33) ..........................................................................................
On Board Dynamic Load Selection .....................................................................................
VR_ON Enable Selection.................................................................................................
VDDQ S3, S5 Enable Selection ........................................................................................
1.05V Enable Selection ..................................................................................................
VCCIO Output Voltage Selection .......................................................................................
On Board Dynamic Load Enable/Disable selection ..................................................................
EVM Major Components List ............................................................................................
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Description
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1
Description
The TPS59650EVM-753 is designed to use a 9V-20V Input bus to produce 6 regulated outputs for IMVP7
SVID CPU/GPU Power System. The TPS59650EVM-753 is specially designed to demonstrate the
TPS59650 full IMVP7 mobile feature while providing GUI communication programing and a number of test
points to evaluate the static and dynamic performance of TPS59650.
1.1
Typical Applications
•
1.2
IMVP7 Vcore Applications for Adapter, Battery, NVDC or 3V/5V/12V rails
Features
The TPS59650EVM-753 features:
• Complete solution for 9V-20V Input Intel IMVP7 SVID Power System
• GUI communication to demonstrate full IMVP7 Mobile feature
• 3-Phase CPU Vcore can support up to 94A output current
• 2-Phase GPU Vcore can support up to 46A output current
• 8 Selectable Switching frequency for CPU and GPU power
• 8 Levels selectable current limit for CPU and GPU power
• Switches or Jumpers for each output enable
• On Board Dynamic Load for CPU, GPU Vcore and VCCIO output
• High efficiency and high density by using TI power block MOSFET
• Convenient test points for probing critical waveforms
• Eight Layer PCB with 1oz copper
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TPS59650EVM-753 Power System Block Diagram
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TPS59650EVM-753 Power System Block Diagram
IMVP7
TPS59650
9-20VBAT
Power Block
CPU Core
(94A)
48 Pin
6x6 QFN
SVID
GPU Core
(46A)
TPS51219
16 Pin
3x3 QFN
TPS51916
20 Pin
3x3 QFN
TPS70102PWP
5Vin
20 Pin
PWP
VCCIO: 1.05V/10A
DDR3L/DDR4 Memory Rail
VDDQ: 1.2V/8A
VTT: 0.6V/2A,
VTTREF: 0.6V/10mA
1.8V/500mA
3.3V/250mA
CPU: 0A-32A
On Board Dynamic
Load for CPU, GPU
and VCCIO
GUI communication
USB Cable
A
B
GPU: 0A-19A
VCCIO: 0A-10A
TMS320F2808PZS
TUSB3410RHB
Host Computer
Figure 1. TPS59650EVM-753 Power System Block Diagram
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Electrical Performance Specifications
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CPU/GPU
VR_ON
CPU Load
Connector
CSD87350Q5D
OCL, FSW
selection
CPU Core
TPS59650
TPS51219
VCCIO
GPU CORE
Intel SVID GUI
from USB
GPU Load Connector
TPS51916
DDR3L/DDR4
Memory Rail
Chief River CPU
socket
Figure 2. TPS59650EVM-753 EVM Illustration
3
Electrical Performance Specifications
Table 1. TPS59650EVM-753 Electrical Performance Specifications (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
12
20
V
INPUT CHARACTERISTICS
12VBAT input voltage range
VBAT
Maximum input current
VBAT = 12V, all full load (3-Phase CPU/2-Phase GPU)
9
15.5
A
No load input current
VBAT=12V, all no load(3-Phase CPU/2 Phase GPU)
0.14
A
5VIN input voltage range
5Vin
Maximum input current
VBAT =12 V, all full load
0.3
A
No load input current
VBAT=12V, all no load
0.1
A
SVID: Address:00 CPU, Payload: 1.05V
1.05
V
Line regulation
0.1%
Load regulation(Droop) Load Line
–1.9
mΩ
25
mVpp
4.5
5
5.5
V
OUTPUT CHARACTERISTICS
CPU(TPS59650)
Output voltage Vcore
Output voltage regulation
Output voltage ripple
VBAT=12V, 1.05V/90A(3-Phase) at 300kHz
Output load current
CPU 3-Phase operation
Output over current
Selectable per phase
Switching frequency
Selectable
Full load efficiency
VBAT=12V, 1.05V/95A at 300kHz
0
94
A
600
kHz
37
250
300
A
80.05%
GPU(TPS59650)
Output voltage Vcore
(1)
SVID: Address:01 GPU, Payload: 1.23V
1.23
V
Jumpers set to default locations, see section 6 of this user’s guide
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Test Setup
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Table 1. TPS59650EVM-753 Electrical Performance Specifications (1) (continued)
PARAMETER
Output voltage regulation
Output voltage ripple
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Line regulation
0.1%
Load regulation(Droop) Load Line
–3.9
mΩ
30
mVpp
VBAT=12V, 1.23V/50A 2 Phase at 385kHz
Output load current
0
Output over current
Selectable per phase
Switching frequency
Selectable
Full load efficiency
VBAT=12V, 1.23V/50A 2 Phase at 385KHz
50
A
660
kHz
37
275
385
A
86.58%
1.05V VCCIO (TPS51219)
Output voltage
Output voltage regulation
Output voltage ripple
1.05
Line regulation
0.1%
Load regulation
0.1%
VBAT=12V, 1.05V/10A
Output load current
30
0
Output over current
Switching frequency
Selectable
Full load efficiency
VBAT=12V, 1.05V/10A
V
mVpp
10
A
16
A
500
kHz
89.87%
DDR3L/DDR4 Memory Rail (TPS51916)
Output voltage
Output voltage regulation
Output voltage ripple
1.2
Line regulation
0.1%
Load regulation
0.1%
VBAT=12V, 1.2V/8A
Output load current
30
0
Output over current
Switching frequency
Selectable
Full load efficiency
VBAT=12V, 1.2V/8A
Operating temperature
4
Test Setup
4.1
Test Equipment
4.1.1
V
mVpp
8
A
10
A
500
kHz
89.07%
25
°C
PC Computer (Host Computer)
Microsoft Windows XP or newer with available USB port
4.1.2
USB Cable
The USB Cable: Standard USB_A to USB_B 5 Pin Mini-B cable. See Figure 3 .
Figure 3. USB Cable
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Test Setup
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4.1.3
1.
2.
3.
4.
4.1.4
TPS59650 USB driver and SVID GUI Installation
Copy the both files: setup.exe and setup.msi to the host computer.
Run this setup.exe.
Following installation Instructions, this will install the driver and the Texas Instruments SVID GUI.
It will add the below icon
DC Source
12VBAT DC Source: The 12VBAT DC source should be a 0-20V variable DC source capable of
supplying 20Adc current. Connect 12VBAT to J21 as shown in Figure 4.
5Vin DC Source: The 5Vin DC source should be a 0-5V variable DC source capable of supplying 1Adc
current. Connect 5Vin to J22 as shown in Figure 4.
4.1.5
•
•
•
•
4.1.6
Meters
V1: 5Vin at TP81(5Vin) and TP83(GND)
V2: 12VBAT at TP82(VBAT) and TP24(GND)
V3: CPU Vcore sense voltage at J7; GPU Vcore sense voltage at J9; VDDQ sense voltage at J20,
VCCIO sense voltage at J16
A1: 12VBAT input current
Load
The output load should be an electronic constant current load capable of 0-90Adc.
4.1.7
Oscilloscope
A digital or analog oscilloscope can be used to measure the output ripple. The oscilloscope should be set
for 1MΩ impedance, 20MHz Bandwidth, AC coupling, 2us/division horizontal resolution, 50mV/division
vertical resolution. Test point TP30 and TP46 can be used to measure the output ripple voltage for CPU
and GPU. Do not use a leaded ground connection as this may induce additional noise due to the large
ground loop.
4.2
Recommended Wire Gauge
1. V5in to J22(5V input):
The recommended wire size is 1x AWG #18 per input connection, with the total length of wire less than
4 feet (2 feet input, 2 feet return).
2. 12VBAT to J21(12V input):
The recommended wire size is 1x AWG #16 per input connection, with the total length of wire less than
4 feet (2 feet input, 2 feet return).
3. J1, J2, J3(CPU) to LOAD or J4, J5 (GPU) to LOAD or J19 (VDDQ) to LOAD or J15(VCCIO) to
LOAD:
The minimum recommended wire size is 2x AWG #16, with the total length of wire less than 4 feet (2
feet output, 2 feet return)
4.3
Recommended Test Setup
Figure 4 is the recommended test set up to evaluate the TPS59650EVM-753.Working at an ESD
workstation, make sure that any wrist straps, bootstraps or mats are connected referencing the user to
earth ground before handling the EVM.
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Test Setup
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12VBAT DC
Source
-
-
- +
V3
VCCIO
+
CPU
-
+
+
Load
- +
- +
5Vin DC
Source
+
-
V2
A1
- +
V1
-
+
+
-
GPU
+
USB Cable
A
B
Host Computer
+ _
VDDQ
Figure 4. TPS59650EVM-753 Recommended Test Set Up
4.4
USB Cable Connections
A standard USB_A and 5 pin Mini_B USB cable needed to connect between host computer and J34 USB
port (left bottom side). A GREEN LED(D13) will light up near the USB port on the EVM. This just means
USB cable is connected.
4.5
Input Connections
1. Prior to connecting the 5Vin DC source, it is advisable to limit the source current from 5Vin to 1A
maximum. Make sure 5Vin is initially set to 0V and connected as shown in Figure 4.
2. Prior to connecting the 12VBAT DC source, it is advisable to limit the source current from 12VBAT to
10A maximum. Make sure 12VBAT is initially set to 0V and connected as shown in Figure 4.
3. Connect voltmeters V1 at TP81 (5Vin) and TP83 (GND) to measure 5Vin voltage, V2 at TP82 (VBAT)
and TP24 (GND) to measure 12VBAT voltage as shown in Figure 4.
4. Connect a current meter A1 between 12VBAT DC source and J21 to measure the 12VBAT input
current.
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4.6
Output Connections
1. Connect Load to J1, J2, J3 and set Load to constant resistance mode to sink 0Adc before 5Vin and
12VBAT are applied. This is for CPU operation.
2. Connect a voltmeter V3 at J7 to measure CPU Vcore sense voltage.
5
Configuration
All Jumper selections should be made prior to applying power to the EVM. User can configure this EVM
per following configurations.
5.1
5.1.1
CPU and GPU Configuration
CPU/GPU Current Limit Trip Selection (J10 for CPU and J12 for GPU)
The current limit trip can be set by J10(COCP) and J12(GOCP).
Default setting: Level 5 for both CPU and GPU.
Table 2. Current Limit Trip Selection
Jumper set to
Connected Resistor
Left (1-2 pin shorted)
150k
Max
2nd(3-4 pin shorted)
100k
Level 7
3rd(5-6 pin shorted)
75k
Level 6
4 (7-8 pin shorted)
56.2k
Level 5
5th(9-10 pin shorted)
39.2k
Level 4
6th(11-12 pin shorted)
30.1k
Level 3
7 (13-14 pin shorted)
24.3k
Level 2
Right(15-16 pin shorted)
20.0k
Min
th
th
5.1.2
COCP/GOCP Limit (Typ.)
CPU Frequency Selection (J11)
The operating frequency can be set by J11
Default setting: 300 kHz for CPU
Table 3. CPU Frequency Selection
Jumper set to
Connected Resistor
CPU
Left (1-2 pin shorted)
150k
600 kHz
2nd(3-4 pin shorted)
100k
550 kHz
3 (5-6 pin shorted)
75k
500 kHz
4th(7-8 pin shorted)
56.2k
450 kHz
5th(9-10 pin shorted)
39.2k
400 kHz
rd
th
6 (11-12 pin shorted)
30.1k
350 kHz
7th(13-14 pin shorted)
24.3k
300 kHz
Right(15-16 pin shorted)
20.0k
250 kHz
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Configuration
5.1.3
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GPU Frequency Selection (J13)
The operating frequency can be set by J13
Default setting: 385 kHz for GPU.
Table 4. GPU Frequency Selection
Jumper set to
Connected Resistor
GPU
Left (1-2 pin shorted)
150k
660 kHz
2nd(3-4 pin shorted)
100k
605 kHz
3 (5-6 pin shorted)
75k
550 kHz
4th(7-8 pin shorted)
56.2k
495 kHz
5th(9-10 pin shorted)
39.2k
440 kHz
6th(11-12 pin shorted)
30.1k
385 kHz
7th(13-14 pin shorted)
24.3k
330 kHz
Right(15-16 pin shorted)
20.0k
275 kHz
rd
5.1.4
F2808 DSP Program Mode Selection (J39)
The F2808 DSP Program Mode(GUI) Selection can be set by J39.
Default setting: No Jumper shorts on J39 for normal operation
Table 5. F2808 DSP Program Mode Selection
5.1.5
Jumper set to
Program Mode Selection
No Jumper on J39
Normal Operation
Jumper on J39
Flash the DSP program to the EVM
5Vin Bias Voltage Option (J33)
The 5Vin Bias Voltage can be used from USB or Externally
Default setting: No Jumper shorts on J33
Table 6. 5Vin Bias Voltage Option (J33)
5.1.6
Jumper set to
Selection
No Jumper
5Vin Bias from J22 external
Jumper on J39
5Vin Bias from USB, 5Vin from J22 should not be connected
On Board Dynamic Load Selection (S3 for CPU, S2(upper) for GPU, S2(lower) for VCCIO)
The on board dynamic load can be set by S2 and S3.
Default setting: Push S2 and S3 to “OFF” position to disable the on board dynamic load
Table 7. On Board Dynamic Load Selection
12
Switch set to
Dynamic Load Selection
Push S3 to “ON” position
Enable 32A on board dynamic load at CPU
Push S3 to “OFF” position
Disable 32A on board dynamic load at CPU
Push S2(upper) to “ON” position
Enable 19A on board dynamic load at GPU
Push S2(upper) to “OFF” position
Disable 19A on board dynamic load at GPU
Push S2(lower) to “ON” position
Enable 10A on board dynamic load at VCCIO
Push S2(lower) to “OFF” position
Disable 10A on board dynamic load at VCCIO
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5.1.7
IMVP-7 VR_ON Enable Selection (S4)
The IMVP-7 CPU/GPU can be enabled and disabled by S4
Default setting: Push S4 to “OFF” position to disable both CPU and GPU
Table 8. VR_ON Enable Selection
5.2
5.2.1
Switch set to
VR_ON Selection
Push S4 to “ON” position
Enable IMVP-7 CPU/GPU Vcore
Push S4 to “OFF” position
Disable IMVP-7 CPU/GPU Vcore
1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration
VDDQ S3, S5 Enable Selection
The controller can be enabled and disabled by J18 and J17.
Default setting: Jumper shorts on Pin2 and Pin3 of J18,
Def ault setti ng : Jumper shorts on Pin2 and Pin3 of J17
Table 9. VDDQ S3, S5 Enable Selection
State
5.3
5.3.1
J17 (S3) set to
J18(S5) set to
VDDQ
VTTREF
VTT
S0
ON position
ON position
ON
ON
ON
S3
OFF position
ON position
ON
ON
OFF(High-Z)
S4/S5
OFF position
OFF position
OFF(Discharge)
OFF(Discharge)
OFF(Discharge)
1.05V VCCIO Configuration
1.05V Enable Selection (S1)
1.05V Enable can be set by S1
Default setting: Push S1 to ”OFF” position
Table 10. 1.05V Enable Selection
5.3.2
Jumper set to
Selection
Push S1 to “ON” position
1.05V Enabled
Push S1 to “OFF” position
1.05V Disabled
VCCIO Output Voltage Selection (J14)
The VCCIO Output Voltage can be selected by J14
Default setting: Jumper shorts Pin1 and Pin2 of J14
Table 11. VCCIO Output Voltage Selection
Jumper set to
Selection
Jumper shorts on Pin1 and Pin2
VCCIO: 1.05V
Jumper shorts on Pin2 and Pin3
VCCIO: 1.00V
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Test Procedure
5.3.3
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On Board Dyanamic Load Enable Pin (J23)
The on board dynamic load can be enabled or disabled by J23
Default setting: Jumper shorts on J23
Table 12. On Board Dynamic Load Enable/Disable selection
Jumper set to
Selection
Jumper shorts
Enable on board dynamic load
No Jumper short
Disable on board dynamic load
6
Test Procedure
6.1
Line/Load Regulation and Efficiency Measurement Procedure
6.1.1
1.
2.
3.
4.
5.
6.
7.
8.
9.
CPU
Set up EVM as described in Section 4.3 through Section 4.6 and Figure 4.
Ensure J39 no Jumper shorts on
Ensure all other Jumpers configuration setting by Section 5 before 5Vin and 12VBAT are applied.
Ensure Load is set to constant resistance mode and to sink 0Adc
Ensure S1 and S4 are in “OFF” position
Add scope probe on the TP30 for CPU Vcore ripple measurement
Ensure USB Cable is connected between host computer and USB port(J34) on the EVM
Increase 5Vin from 0V to 5V. Using V1 to measure 5Vin input voltage.
Increase 12VBAT from 0V to 12V. Using V2 to measure 12VBAT input voltage.
10. Double-Click the icon to launch the GUI program. The GUI window shown in Figure 5.
11. Push S4 to “ON” position to enable the VR_ON of TPS59650. VR_ON LED will light up.
12. Now the user is ready to send SVID commends. The GUI at start-up defaults:
Address: 00 CPU, Commend: SetVIDslow, Payload: 1.05V (The user can select the SVID commend by
using the pull-down menu”)
13. Click “send Commend” and CPU CPGOOD LED will light up, See the GUI window as Figure 5.
14. Measure V3: CPU Vcore at J7 and A1: 12VBAT input current
15. Vary CPU LOAD from 0Adc to 94Adc, CPU Vcore must remain in load line
16. Vary 12VBAT from 9V to 20V CPU Vcore must remain in line regulation
17. Push S4 to “OFF” position to disable CPU Vcore controller.
18. Decrease LOAD to 0A and disconnect the LOAD from terminal J1, J2, J3
19. Disconnect V3 from J7.
20. Disconnect scope probe from TP30
14
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Figure 5. TPS59650EVM-753 CPU GUI set up Window
6.1.2
1.
2.
3.
4.
5.
GPU
Connect the LOAD to GPU terminal J4, J5 and V3 at J9. Ensure correct polarity.
Add scope probe on the TP46 for GPU Vcore_G ripple measurement
Push S4 to “ON” position to enable the VR_ON of TPS59650. The VR_ON LED will light up.
Now you are ready to send SVID commends for GPU. Using pull-down menu:
Address: 01 GPU, Commend: SetVIDslow, Payload: 1.23V
Click “send Commend” and GPU GPOOD LED will light up, See the GUI window as Figure 6.
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Test Procedure
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Figure 6. TPS59650EVM-753 GPU GUI set up Window
6. Measure V3: GPU Vcore_G at J9 and A1: 12VBAT input current
7. Vary GPU LOAD from 0Adc to 50Adc, GPU Vcore must remain in load line
8. Vary 12VBAT from 9V to 20V GPU Vcore must remain in line regulation
9. Push S4 to “OFF” position to disable GPU Vcore controller.
10. Decrease LOAD to 0A and disconnect the LOAD from terminal J11
11. Disconnect V3 from J9.
12. Disconnect scope probe from TP46
13. Exit SVID GUI window: click File → click Exit
14. Disconnect the USB cable between host Computer and EVM
16
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6.1.3
VDDQ
1. Connect the LOAD to VDDQ terminal J19 and V3 at J20. Ensure correct polarity.
2. Remove Jumper from J17, J18 from pin2 and pin3 and put this Jumper on pin1 and pin 2 of J18, J17
to enable S5 of VDDQ controller. VDDQ PGOOD LED will light up.
3. Measure V3: VDDQ at J20 and A1: 12Vin input current
4. Vary VDDQ LOAD from 0Adc to 8Adc, VDDQ must remain in the load regulation
5. Vary 12VBAT from 9V to 20V, VDDQ must remain in the line regulation
6. Remove Jumper of J17, J18 and shorts back on pin2 and pin3 of J17, J18 to disable VDDQ controller.
7. Decrease LOAD to 0A and disconnect the LOAD from terminal J19
8. Disconnect V3 from J20.
6.1.4
VCCIO
Connect the LOAD to VCCIO terminal J15 and V3 at J16. Ensure correct polarity.
Push S1 to “ON” position to enable the VCCIO controller. VCCIO EN and PGOOD LED will light up.
Measure V3: VCCIO at J16 and A1: 12Vin input current
Vary VDDQ LOAD from 0Adc to 10Adc, VCCIO must remain in the load regulation
Vary 12VBAT from 9V to 20V, VCCIO must remain in the line regulation
Push S1 to “OFF” position to disable VCCIO controller.
Decrease LOAD to 0A and disconnect the LOAD from terminal J15
Disconnect V3 from J16.
1.
2.
3.
4.
5.
6.
7.
8.
6.2
Equipment Shutdown
1.
2.
3.
4.
Shut down
Shut down
Shut down
Shut down
Load
12VBAT and 5Vin
oscilloscope
host computer
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Performance Data and Typical Characteristic Curves
7
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Performance Data and Typical Characteristic Curves
Figure 7 through Figure 91 present typical performance curves for TPS59650EVM-753. Jumpers set to
default locations, see section 6 of this user’s guide.
7.1
CPU 3-Phase Operation
95
1.1
VIN = 12 V
VIN = 9 V
85
Efficiency - %
VIN = 9 V
1.05
VO - Output Voltage - V
90
VIN = 20 V
80
75
SPEC(max)
1
VIN = 12 V
0.95
VIN = 20 V
0.9
SPEC(min)
SPEC(nom)
0.85
70
65
0
10
20
30 40 50 60 70
IO - Output Current - A
80
90
100
0.8
0
Figure 7. CPU3 Efficiency
10
20
80
90
100
Figure 8. CPU3 Load regulation
TPS59650EVM
Test condition: 12 Vin, 1.05V/60A
TPS59650EVM
Test condition: 12 Vin, 1.05V/60A
CPU VDIO Turn on
CPU 3 Phase operation
CPU VR_ON Turn off
CPU 3 Phase operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: 1.05V core
CH4: CPGOOD
Figure 9. CPU3 Enable Turn on
18
30 40 50 60 70
IO - Output Current - A
CH3: 1.05V core
CH4: CPGOOD
Figure 10. CPU3 Enable Turn off
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TPS59650EVM
CPU Switching node and Output Ripple
Test condition: 12 Vin, 1.05V/60A
CPU 3 Phase operation
TPS59650EVM
CPU Dynamic VID: Set VID-Slow/Slow
Test condition: 12 Vin, 1.05V/1A
CPU 3 Operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: 1.05V core
CH3: CSW3
CH4: VDIO
CH4: 1.05V core Ripple
Figure 11. CPU3 Switching Node(Ripple)
Figure 12. CPU3 Dynamic VID: SetVID-Slow/Slow
TPS59650EVM
Test condition: 12 Vin, 1.05V/1A
TPS59650EVM
Test condition: 12 Vin, 1.05V/1A
CPU Dynamic VID: Set VID-Fast/fast
CPU 3 Operation
CPU Dynamic VID: Set VID-Decay/Fast
CPU 3 Operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: 1.05V core
CH3: 1.05V core
CH4: VDIO
CH4: VDIO
Figure 13. CPU3 Dynamic VID:SetVID-Fast/Fast
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Figure 14. CPU3 Dynamic VID:SetVID-Decay/Fast
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Performance Data and Typical Characteristic Curves
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Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
TPS59650EVM
CPU Output Load Releas with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: CSW3
CH3: CSW3
CH4: 1.05V core
CH4: 1.05V core
Figure 15. CPU3 Output Load Insertion with OSR/USR
middle level
Figure 16. CPU3 Output Load Release with OSR/USR
middle level
Figure 17. CPU3 Bode Plot at 12Vin, 1.05V/60A
Test condition: CPU3 12Vin, 1.05V/60A no airflow
20
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Figure 18. CPU3 MOSFET
7.2
Figure 19. CPU3 IC
CPU 2-Phase Operation
1.1
95
VIN = 12 V
VIN = 12 V
VIN = 9 V
90
VO - Output Voltage - V
1.05
Efficiency - %
85
VIN = 20 V
80
75
VIN = 9 V
1
SPEC(min)
SPEC(nom)
0.95
SPEC(max)
0.9
70
65
0
VIN = 20 V
5
10
15 20 25 30 35 40
IO - Output Current - A
Figure 20. CPU2 Efficiency
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45
50
55
0.85
0
5
10
15 20 25 30 35 40
IO - Output Current - A
45
50
55
Figure 21. CPU2 Load regulation
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Performance Data and Typical Characteristic Curves
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TPS59650EVM
Test condition: 12 Vin, 1.05V/40A
TPS59650EVM
Test condition: 12 Vin, 1.05V/40A
CPU VDIO Turn on
CPU 2 Phase Operation
CPU VR_ON Turn off
CPU 2 Phase Operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: 1.05V core
CH3: 1.05V core
CH4: CPGOOD
CH4: CPGOOD
Figure 22. CPU2 Enable Turn on
Figure 23. CPU2 Enable Turn off
TPS59650EVM
Test condition: 12 Vin, 1.05V/40A
TPS59650EVM
CPU Switching node and Output Ripple
CPU 2 Phase Operation
CPU Dynamic VID: Set VID-Slow/Slow
Test condition: 12 Vin, 1.05V/1A
CPU 2 Operation
CH1: CSW1
CH2: CSW1
CH2: CSW2
CH3: CSW2
CH3: 1.05Vcore
CH4: VDIO
CH4: 1.05Vcore
Figure 24. CPU2 Switching Node(Ripple)
22
Figure 25. CPU2 Dynamic VID: SetVID-Slow/Slow
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TPS59650EVM
Test condition: 12 Vin, 1.05V/1A
TPS59650EVM
Test condition: 12 Vin, 1.05V/1A
CPU Dynamic VID: Set VID-Slow/Slow
CPU 2 Operation
CPU Dynamic VID: Set VID-Decay/Fast
CPU 2 Operation
CH1: CSW1
CH1: CSW1
CH2: CSW2
CH2: CSW2
CH3: 1.05Vcore
CH3: 1.05Vcore
CH4: VDIO
CH4: VDIO
Figure 26. CPU2 Dynamic VID:SetVID-Fast/Fast
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
Figure 27. CPU2 Dynamic VID:SetVID-Decay/Fast
TPS59650EVM
CPU Output Load Release with
OSR/USR middle level
CH1: DYN_C
CH1: DYN_C
CH2: CSW1
CH2: CSW1
CH3: CSW2
CH3: CSW2
CH4: 1.05Vcore
CH4: 1.05Vcore
Figure 28. CPU2 Output Load Insertion with OSR/USR
middle level
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Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
Figure 29. CPU2 Output Load Release with OSR/USR
middle level
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Performance Data and Typical Characteristic Curves
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Figure 30. CPU2 Bode Plot at 12Vin, 1.05V/55A
Test condition: CPU2 12Vin, 1.05V/55A no airflow
Figure 31. CPU2 MOSFET
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Figure 32. CPU2 IC
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7.3
CPU1-Phase Operation
1.1
95
VIN = 12 V
VIN = 12 V
VIN = 20 V
VIN = 9 V
90
VO - Output Voltage - V
Efficiency - %
1.05
85
VIN = 20 V
80
VIN = 9 V
1
SPEC(min)
SPEC(nom)
SPEC(max)
0.95
75
70
0
5
10
15
20
25
IO - Output Current - A
30
Figure 33. CPU1 Efficiency
TPS59650EVM
CPU VDIO Turn on
35
0.9
0
5
10
15
20
25
IO - Output Current - A
30
35
Figure 34. CPU1 Load regulation
Test condition: 12 Vin, 1.05V/20A
CPU 3 Phase on board dynamic load
TPS59650EVM
CPU VR_ON Turn off
Test condition: 12 Vin, 1.05V/20A
CPU 1 Phase operation
CH1: VR_ON
CH1: VDIO
CH2: CSW1
CH2: CSW1
CH3: 1.05Vcore
CH3: 1.05Vcore
CH4: CPGOOD
CH4: CPGOOD
Figure 35. CPU1 Enable Turn on
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Figure 36. CPU1 Enable Turn off
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Performance Data and Typical Characteristic Curves
TPS59650EVM
CPU Switching Node
Test condition: 12 Vin, 1.05V/20A
CPU 1 Phase operation
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TPS59650EVM
CPU Switching Node and Output Ripple
Test condition: 12 Vin, 1.05V/20A
CPU 1 Phase operation
CH1: CSW1
CH1: CSW1
CH2: 1.05Vcore Ripple
Figure 37. CPU1 Switching Node
TPS59650EVM
CPU Dynamic VID: Set VID-Slow/Slow
Figure 38. CPU1 Switching node and Ripple
Test condition: 12 Vin, 1.05V/21A
CPU 1 Operation
TPS59650EVM
CPU Dynamic VID: Set VID-Fast/Fast
CH1: CSW1
CH1: CSW1
CH3: 1.05Vcore
CH3: 1.05Vcore
CH4: VDIO
CH4: VDIO
Figure 39. CPU1 Dynamic VID:SetVID-Slow/Slow
26
Test condition: 12 Vin, 1.05V/1A
CPU 1 Operation
Figure 40. CPU1 Dynamic VID:SetVID-Fast/Fast
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TPS59650EVM
CPU Dynamic VID: Set VID-Decay/Fast
Test condition: 12 Vin, 1.05V/1A
CPU 1 Operation
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-27A
CPU 1 Phase on board dynamic load
CH1: CSW1
CH1: DYN_C
CH2: CSW1
CH3: 1.05Vcore
CH4: VDIO
CH3: 1.05Vcore
Figure 41. CPU1 Dynamic VID:SetVID-Decay/Fast
TPS59650EVM
CPU Output Load Releas with
OSR/USR middle level
Figure 42. CPU1 Output Load Insertion with OSR/USR
middle level
Test condition: 12 Vin, 1.05V/0A-27A
CPU 1 Phase on board dynamic load
CH1: DYN_C
CH2: CSW1
CH3: 1.05Vcore
Figure 43. CPU1 Output Load Release with OSR/USR middle level
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Performance Data and Typical Characteristic Curves
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Figure 44. CPU1 Bode Plot at 12Vin, 1.05V/33A
Test condition: CPU1 12Vin, 1.05V/33A no airflow
Figure 45. CPU1 MOSFET
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Figure 46. CPU1 IC
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7.4
GPU 2 Phase Operation
95
1.3
VIN = 12 V
VIN = 9 V
VO - Output Voltage - V
VIN = 20 V
Efficiency - %
VIN = 9 V
1.25
90
85
VIN = 20 V
1.2
1.15
80
75
70
0
VIN = 12 V
SPEC(min)
1.1
SPEC(nom)
1.05
5
10
15 20 25 30 35
IO - Output Current - A
40
45
Figure 47. GPU2 Efficiency
TPS59650EVM
GPU VDIO Turn on
50
SPEC(max)
1
0
5
10
15 20 25 30 35
IO - Output Current - A
45
50
Figure 48. GPU2 Load regulation
Test condition: 12 Vin, 1.23V/40A
GPU 2 Phase operation
TPS59650EVM
GPU VR_ON Turn off
CH1: GSW1
CH1: GSW1
CH2: GSW2
CH2: GSW2
CH3: 1.23Vcore
Test condition: 12 Vin, 1.23V/40A
GPU 2 Phase operation
CH3: 1.23Vcore
CH4: GPGOOD
CH4: GPGOOD
Figure 49. GPU2 Enable Turn on
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Figure 50. GPU2 Enable Turn off
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Performance Data and Typical Characteristic Curves
TPS59650EVM
GPU Switching Node and Output Ripple
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Test condition: 12 Vin, 1.23V/20A
GPU 2 Phase operation
TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
GPU Dynamic VID: Set VID-Slow/Slow
GPU 2 Operation
CH1: GSW1
CH2: GSW1
CH2: GSW2
CH3: GSW2
CH3: 1.23Vcore_G
CH4: VDIO
CH4: 1.23Vcore Ripple
Figure 51. GPU2 Switching Node and Ripple
Figure 52. GPU2 Dynamic VID:SetVID-Slow/Slow
TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
GPU Dynamic VID: Set VID-Fast/Fast
GPU 2 Operation
GPU Dynamic VID: Set VID-Decay/Fast
GPU 2 Operation
CH1: GSW1
CH1: GSW1
CH2: GSW2
CH2: GSW2
CH3: 1.23Vcore_G
CH3: 1.23Vcore_G
CH4: VDIO
CH4: VDIO
Figure 53. GPU2 Dynamic VID:SetVID-Fast/Fast
30
Figure 54. GPU2 Dynamic VID:SetVID-Decay/Fast
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Test condition: 12 Vin, 1.23V/0A-18A
TPS59650EVM
GPU Output Load Insertion with OSR/USR
GPU
2 Phase on board dynamic load
least reduction
TPS59650EVM
GPU Output Load Release with OSR/USR
least reduction
CH1: DYN_G
Test condition: 12 Vin, 1.23V/0A-18A
GPU 2 Phase on board dynamic load
CH1: DYN_G
CH2: GSW1
CH2: GSW1
CH3: GSW2
CH3: GSW2
CH4: 1.23Vcore
CH4: 1.23Vcore
Figure 55. GPU2 Output Load Insertion with OSR/USR Figure 56. GPU2 Output Load Release with OSR/USR
OFF
OFF
Figure 57. GPU2 Bode Plot at 12Vin, 1.23V/50A
Test condition: GPU2 12Vin, 1.23V/50A no airflow
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Performance Data and Typical Characteristic Curves
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Figure 58. GPU2 MOSFET
7.5
Figure 59. GPU2 IC
GPU 1 Phase Operation
95
1.3
VIN = 9 V
90
1.25
VO - Output Voltage - V
Efficiency - %
VIN = 12 V
85
VIN = 20 V
80
1.2
VIN = 12 V
SPEC(min)
VIN = 20 V
VIN = 9 V
1.1
5
10
15
20
25
IO - Output Current - A
30
35
1.05
0
Figure 60. GPU1 Efficiency
32
SPEC(nom)
1.15
75
70
0
SPEC(max)
5
10
15
20
25
IO - Output Current - A
30
35
Figure 61. GPU1 Load regulation
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TPS59650EVM
GPU VDIO Turn on
Test condition: 12 Vin, 1.05V/20A
GPU 1 Phase operation
TPS59650EVM
GPU VR_ON Turn on
Test condition: 12 Vin, 1.23V/20A
GPU 1 Phase operation
CH1: VR_ON
CH1: VDIO
CH2: GSW1
CH2: GSW1
CH3: 1.23Vcore
CH3: 1.23Vcore
CH4: GPGOOD
CH4: GPGOOD
Figure 62. GPU1 Enable Turn on
TPS59650EVM
GPU Switching Node
Test condition: 12 Vin, 1.23V/0A-18A
GPU 1 Phase operation
Figure 63. GPU1 Enable Turn off
TPS59650EVM
GPU Switching Node and Output Ripple
Test condition: 12 Vin, 1.23V/20A
GPU 1 Phase operation
CH2: GSW1
CH1: GSW1
CH3: 1.23Vcore Ripple
Figure 64. GPU1 Switching Node
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Figure 65. GPU1 Switching Node and Ripple
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Performance Data and Typical Characteristic Curves
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TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
GPU Dynamic VID: Set VID-Slow/Slow
GPU 1 Operation
CPU Dynamic VID: Set VID-Fast/Fast
GPU 1 Operation
CH1: GSW1
CH1: CSW1
CH3: 1.23Vcore_G
CH3: 1.23Vcore_G
CH4: VDIO
CH4: VDIO
Figure 66. GPU1 Dynamic VID:SetVID-Slow/Slow
TPS59650EVM
Test condition: 12 Vin, 1.23V/1A
GPU Dynamic VID: Set VID-Decay/Fast
GPU 1 Operation
Figure 67. GPU1 Dynamic VID:SetVID-Fast/Fast
TPS59650EVM
Test condition: 12 Vin, 1.23V/0A-18A
GPU Output Load Insertion with OSR/USR
least reduction
GPU 1 Phase on board dynamic load
CH1: GSW1
CH1: DYN_G
CH2: GSW1
CH3: 1.23Vcore_G
CH4: VDIO
CH3: 1.23Vcore
Figure 68. GPU1 Dynamic VID:SetVID-Decay/Fast
34
Figure 69. GPU1 Output Load Insertion with OSR/USR
OFF
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Test condition: 12 Vin, 1.23V/0A-18A
TPS59650EVM
GPU Output Load Release with OSR/USR
GPU 1 Phase on board dynamic load
least reduction
CH1: DYN_G
CH2: GSW1
CH3: 1.23Vcore
Figure 70. GPU1 Output Load Release with OSR/USR OFF
Figure 71. GPU1 Bode Plot at 12Vin, 1.23V/33A
Test condition: GPU1 12Vin, 1.23V/33A no airflow
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Figure 72. GPU1 MOSFET
7.6
Figure 73. GPU1 IC
1.05V VCCIO
100
1.08
VIN = 9 V
90
80
Efficiency - %
60
VO - Output Voltage - V
VIN = 12 V
70
VIN = 20 V
50
40
30
1.06
VIN = 12 V
VIN = 9 V
VIN = 20 V
1.04
20
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
100
1.02
Figure 74. 1.05V Efficiency
36
0
2
4
6
IO - Output Current - A
8
10
Figure 75. 1.05V Load regulation
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TPS59650EVM
VCCIO Enable Turn on
Test condition: 12 Vin, 1.05VCCIO/10A
Test condition: 12 Vin, 1.05VCCIO/10A
CH1: VCCIO_EN
CH1: VCCIO_EN
CH2: 1.05VCCIO
CH2: 1.05VCCIO
CH3: VCCIO_PG
CH3: VCCIO_PG
Figure 76. 1.05V Enable Turn on
TPS59650EVM
VCCIO Switching Node
TPS59650EVM
VCCIO Enable Turn off
Test condition: 12 Vin, 1.05VCCIO/10A
Figure 77. 1.05V Enable Turn off
TPS59650EVM
VCCIO Output Ripple
Test condition: 12 Vin, 1.05VCCIO/10A
CH1: SW
CH1: VCCIO Output Ripple
Figure 78. 1.05V Switching Node
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Figure 79. 1.05V Ripple
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Performance Data and Typical Characteristic Curves
TPS59650EVM
VCCIO Output Transient from
DCM to CCM
Test condition: 12 Vin, 1.05VCCIO/0A-10A
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TPS59650EVM
VCCIO Output Transient from
CCM to DCM
CH1: VCCIO Output
Test condition: 12 Vin, 1.05VCCIO/0A-10A
CH1: VCCIO Output
CH2: VCCIO Output current
CH2: VCCIO Output current
Figure 80. 1.05V Transient DCM TO CCM
Figure 81. 1.05V Transient CCM to DCM
Test condition: 12Vin, 1.05V/10A no airflow
Figure 82. TPS51219 Thermal
38
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7.7
1.2V VDDQ
1.26
100
90
VIN = 9 V
1.24
80
VIN = 12 V
VO - Output Voltage - V
Efficiency - %
70
VIN = 20 V
60
50
40
30
1.22
VIN = 12 V
VIN = 20 V
1.20
VIN = 9 V
1.18
20
1.16
10
0
0.001
0.01
0.1
1
IO - Output Current - A
10
Figure 83. 1.2V Efficiency
TPS59650EVM
VDDQ S5 Turn on
1.14
0
2
4
6
IO - Output Current - A
8
Figure 84. 1.2V Load regulation
Test condition: 12 Vin, 1.2VDDQ/8A
TPS59650EVM
VDDQ S5 Turn off
Test condition: 12 Vin, 1.2VDDQ/8A
CH1: VDDQ S5
CH1: VDDQ S5
CH2: VDDQ
CH2: VDDQ
CH3: VTTREF
CH3: VTTREF
CH4: VDDQ_PG
CH4: VDDQ_PG
Figure 85. 1.2V Enable Turn on
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Figure 86. 1.2V Enable Turn off
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Performance Data and Typical Characteristic Curves
TPS59650EVM
VDDQ Output Switching Node
Test condition: 12 Vin, 1.2VDDQ/8A
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TPS59650EVM
VDDQ Output Ripple
Test condition: 12 Vin, 1.2VDDQ/8A
CH1: VDDQ SW
CH1: VDDQ Output Ripple
Figure 87. 1.2V Switching Node
TPS59650EVM
VDDQ Output transient
from DCM to CCM
Test condition: 12 Vin, 1.2VDDQ/0A-8A
CH1: VDDQ Output
Figure 88. 1.2V Ripple
TPS59650EVM
VDDQ Output transient
from CCM to DCM
Test condition: 12 Vin, 1.2VDDQ/0A-8A
CH1: VDDQ Output
CH4: VDDQ Output current
CH4: VDDQ Output current
Figure 89. 1.2V Transient DCM TO CCM
Figure 90. 1.2V Transient CCM to DCM
Test condition: 12Vin, 1.2V/7.5A no airflow
40
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Figure 91. TPS51916 Thermal
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EVM Assembly Drawings and PCB Layout
8
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EVM Assembly Drawings and PCB Layout
The following figures (Figure 92 through Figure 101) show the design of the TPS59650EVM-753 printed
circuit board. The EVM has been designed using 8 Layers circuit board with 1oz copper on outside layers.
Figure 92. TPS59650EVM-753 Top Layer Assembly Drawing (Top view)
Figure 93. TPS59650EVM-753 Bottom Assembly Drawing (Bottom view)
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Figure 94. TPS59650EVM-753 Top Copper
Figure 95. TPS59650EVM-753 Bottom Copper
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Figure 96. TPS59650EVM-753 Internal Layer 2
Figure 97. TPS59650EVM-753 Internal Layer 3
44
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Figure 98. TPS59650EVM-753 Internal Layer 4
Figure 99. TPS59650EVM-753 Internal Layer 5
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EVM Assembly Drawings and PCB Layout
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Figure 100. TPS59650EVM-753 Internal Layer 6
Figure 101. TPS59650EVM-753 Internal Layer 7
46
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Bill of Materials
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9
Bill of Materials
The EVM major components list according to the schematic shown in the following pages.
Table 13. EVM Major Components List
QTY
REF DES
Description
MFR
Part Number
11
C1, C12, C31, C69, C74,
C124, C159, C121, C130,
C184, C204
Capacitor, Ceramic, 1nF, 50V, X7R, 10%, 0603
STD
STD
5
C104, C108, C112, C115,
C118
Capacitor, Ceramic, 33nF, 25V, X7R, 10%, 0603
STD
STD
29
C128,
C201,
C192,
C209,
C218,
C222,
C226,
C230
Capacitor, Ceramic, 0.1uF, 25V, X7R, 10%, 0603
STD
STD
3
C129, C133, C168
Capacitor, Polymer, 330uF, 2V, 6mohm, 20%, 7343
Sanyo
2TPF330M6
2
C13, C26
Capacitor, Ceramic, 100pF, 50V, C0G, 10%, 0603
STD
STD
3
C131, C239, C246
Capacitor, Ceramic, 10nF, 50V, X7R, 10%, 0603
STD
STD
6
C15, C16, C19, C20, C76,
C77
Capacitor, Polymer, 470uF, 2V, 4mohm, 20%, D2T
Sanyo
2TPLF470M4E
1
C166
Capacitor, Ceramic, 2.2uF, 6.3V, X5R, 10%, 0805
STD
STD
1
C17
Capacitor, Ceramic, 0.33uF, 6.3V, X7R, 10%, 0603
STD
STD
1
C171
Capacitor, Ceramic, 0.22uF, 50V, X7R, 10%, 0603
STD
STD
15
C18, C23, C33, C75, C80,
C196, C202, C208, C195,
C200, C242, C250, C22,
C233, C234
Capacitor, Ceramic, 1uF, 25V, X7R, 10%, 0603
STD
STD
7
C193, C36, C79, C82, C7,
C135, C170
Capacitor, Ceramic, 2.2uF, 6.3V, X5R, 10%, 0603
STD
STD
3
C194, C197, C215
Capacitor, Ceramic, 0.01uF, 50V, X7R, 10%, 0603
STD
STD
28
C2, C3, C4, C5, C8, C9, C10,
C11, C27, C28, C29, C30,
C65, C66, C67, C68, C70,
C71, C72, C73, C122, C123,
C125, C126, C160, C161,
C162, C163
Capacitor, Ceramic, 10uF, 25V, X7R, 20%, 1206
STD
STD
2
C205, C206
Capacitor, Ceramic, 10pF, 50V, C0G, 10%, 0603
STD
STD
2
C213, C214
Capacitor, Ceramic, 22pF, 50V, C0G, 10%, 0603
STD
STD
2
C240, C248
Capacitor, Ceramic, 0.22uF, 25V, X7R, 10%, 0402
STD
STD
2
C241, C249
Capacitor, Ceramic, 220pF, 25V, X7R, 10%, 0402
STD
STD
2
C243, C251
Capacitor, Ceramic, 680pF, 25V, X7R, 10%, 0402
STD
STD
2
C244, C252
Capacitor, Ceramic, 100pF, 25V, C0G, 10%, 0402
STD
STD
2
C245, C253
Capacitor, Ceramic, 1.8nF, 25V, X7R, 10%, 0402
STD
STD
2
C247, C254
Capacitor, Ceramic, 2200pF, 25V, X7R, 10%, 0402
STD
STD
44
C37, C38, C39, C40, C41,
C42, C43, C45, C49, C50,
C51, C52, C53, C54, C55,
C56, C87, C88, C89, C90,
C91, C92, C93, C94, C95,
C100, C101, C102, C136,
C140, C141, C143, C145,
C146, C147, C148, C150,
C151, C152, C154, C235,
C236, C237, C238
Capacitor, Ceramic, 22uF, 6.3V, X5R, 10%, 0805
STD
STD
20
C44, C46, C57, C58, C59,
C60, C61, C62, C63, C64,
C173, C174, C175, C176,
C180, C182, C165, C185,
C189, C191
Capacitor, Ceramic, 10uF, 6.3V, X5R, 10%, 0805
STD
STD
1
C6
Capacitor, Ceramic, 4.7uF, 6.3V, X5R, 10%, 0805
STD
STD
8
D1, D2, D3, D9, D10, D12,
D13, D14
Diode, LED, Green Clear, 20mcd, 0.079x0.049
Lite On
LTST-C170GKT
C164,
C127,
C203,
C210,
C219,
C223,
C227,
C198,
C172,
C207,
C216,
C220,
C224,
C228,
C199,
C188,
C190,
C217,
C221,
C225,
C229,
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Bill of Materials
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Table 13. EVM Major Components List (continued)
QTY
REF DES
Description
MFR
Part Number
5
D4, D5, D7, D8, D11
Diode, LED, Red Clear, 20mcd, 0.079x0.049
Lite On
LTST-C170CKT
1
D6
Diode, Schottky, 200mA, 30V, SOT-23,
Vishay-Liteon
BAT54-V-GS08
1
FB1
Bead, SMD,Ferrite, 100MHz Max, 200mA, +/-25%, 0603
WE
74279266A
5
L1, L2, L3, L4, L5
Inductor, SMT, 0.36uH, 35A , 0.82mohm, 10x11.5mm
Toko
FCUL1040-H-R36M
1
L6
Inductor, SMT, 0.42uH, 17A , 1.5mohm, 8.7x7.0mm
Panasonic
ETQP4LR42AFM
1
L7
Inductor, SMT, 1.0uH, 8.1A , 6.9mohm, 7.3x6.6mm
Panasonic
ETQP3W1R0WFN
7
Q1, Q2, Q3, Q4, Q5, Q8, Q10 MOSFET, Synchronous Buck NexFET Power Block SON 5X6mm
TI
CSD87350Q5D
4
Q11, Q12, Q13, Q14
MOSFET, Nchan, 25V, 31A, 2.5mohm, QFN5X6mm
TI
CSD16407Q5
1
Q15
MOSFET, Pchan, -60V, -0.33A, 2ohm, SOT23
Infineon
BSS83P
6
Q6, Q7, Q9, Q16, Q17, Q18
MOSFET, Nchan, 100V, 0.17A, 6ohm, SOT23
Fairchild
BSS123
1
R1
Resistor, Chip, 42.2k, 1/10W, 1%, 0603
STD
STD
4
R101, R102, R118, R119
Resistor, Chip, 56.2k, 1/10W, 1%, 0603
STD
STD
1
R104
Resistor, Chip, 2.43k, 1/10W, 1%, 0603
STD
STD
7
R106, R107, R122, R123,
R141, R165, R166
Resistor, Chip, 30.1k, 1/10W, 1%, 0603
STD
STD
4
R108, R109, R124, R125
Resistor, Chip, 24.3k, 1/10W, 1%, 0603
STD
STD
22
R12, R15, R24, R31, R36,
R41, R54, R58, R73, R76,
R140, R142, R144, R145,
R156, R157, R159, R161,
R232, R233, R250, R268
Resistor, Chip, 0, 1/10W, 1%, 0603
STD
STD
7
R130, R131, R147, R215,
R216, R217, R222
Resistor, Chip, 180, 1/10W, 1%, 0603
STD
STD
14
R132,
R158,
R214,
R230,
R148, R149, R150,
R183, R185, R205,
R219, R220, R221,
R231
Resistor, Chip, 10.0k, 1/10W, 1%, 0603
STD
STD
5
R133, R134, R151, R213,
R218
Resistor, Chip, 1.00k, 1/10W, 1%, 0603
STD
STD
1
R139
Resistor, Chip, 10.5k, 1/10W, 1%, 0603
STD
STD
1
R152
Resistor, Chip, 22.1k, 1/10W, 1%, 0603
STD
STD
6
R16, R110, R111, R126,
R127, R160
Resistor, Chip, 20.0k, 1/10W, 1%, 0603
STD
STD
1
R163
Resistor, Chip, 15.0k, 1/10W, 1%, 0603
STD
STD
4
R164, R237, R238, R239
Resistor, Chip, 2.00k, 1/10W, 1%, 0603
STD
STD
1
R167
Resistor, Chip, 51.1k, 1/10W, 1%, 0603
STD
STD
1
R168
Resistor, Chip, 1, 1/10W, 1%, 0603
STD
STD
1
R176
Resistor, Chip Array, 10.0k, 62.5mW, 5%, 1206
Yageo
TC164-JR-0710KL
3
R169, R170, R171
Resistor, Chip, 1, 1/8W, 1%, 0805
STD
STD
3
R172, R173, R178
Resistor, Chip, 0.01, 1W, 1%, 2512
STD
STD
5
R174, R175, R177, R179,
R180
Resistor, Chip, 0.05, 1W, 1%, 2512
STD
STD
5
R176, R177, R178, R179,
R199
Resistor, Chip, 330, 1/10W, 1%, 0603
STD
STD
7
R18, R194, R202, R246,
R248, R260, R262
Resistor, Chip, 10.0k, 1/16W, 1%, 0402
STD
STD
2
R181, R189
Resistor, Chip, 0.005, 1W, 1%, 2512
STD
STD
1
R182
Resistor, Chip, 8.06k, 1/10W, 1%, 0603
STD
STD
5
R186, R187, R188, R190,
R212
Resistor, Chip, 330, 1/10W, 1%, 0603
STD
STD
1
R192
Resistor, Chip, 100, 1/10W, 1%, 0603
STD
STD
10
R193, R195, R196, R197,
R198, R199, R203, R204,
R206, R207
Resistor, Chip, 1M, 1/16W, 1%, 0402
STD
STD
1
R2
Resistor, Chip, 130, 1/16W, 1%, 0402
STD
STD
48
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Table 13. EVM Major Components List (continued)
QTY
REF DES
Description
MFR
Part Number
20
R43, R49, R51, R60, R65,
R71, R75, R85, R87, R93,
R200, R201, R208, R209,
R243, R249, R253, R254,
R263, R265
Resistor, Chip, 0, 1/16W, 1%, 0402
STD
STD
1
R21
Resistor, Chip, 200k, 1/10W, 1%, 0603
STD
STD
2
R210, R211
Resistor, Chip, 3.01k, 1/10W, 1%, 0603
STD
STD
1
R224
Resistor, Chip, 75, 1/10W, 1%, 0603
STD
STD
1
R225
Resistor, Chip, 130, 1/10W, 1%, 0603
STD
STD
1
R226
Resistor, Chip, 43.2, 1/10W, 1%, 0603
STD
STD
1
R227
Resistor, Chip, 1.50k, 1/10W, 1%, 0603
STD
STD
2
R228, R229
Resistor, Chip, 33.2, 1/10W, 1%, 0603
STD
STD
1
R23
Resistor, Chip, 4.02k, 1/10W, 1%, 0603
STD
STD
2
R234, R236
Resistor, Chip, 470, 1/10W, 1%, 0603
STD
STD
1
R235
Resistor, Chip, 2.21k, 1/10W, 1%, 0603
STD
STD
2
R240, R241
Resistor, Chip, 2.74k, 1/10W, 1%, 0603
STD
STD
2
R242, R251
Resistor, Chip, 2.21, 1/16W, 1%, 0402
STD
STD
2
R244, R255
Resistor, Chip, 475k, 1/16W, 1%, 0402
STD
STD
2
R245, R257
Resistor, Chip, 5.62k, 1/16W, 1%, 0402
STD
STD
2
R252, R264
Resistor, Chip, 2.00k, 1/16W, 1%, 0402
STD
STD
1
R258
Resistor, Chip, 3.09k, 1/16W, 1%, 0402
STD
STD
1
R259
Resistor, Chip, 20.0k, 1/16W, 1%, 0402
STD
STD
7
R26, R97, R98, R114, R115,
R162, R184
Resistor, Chip, 100k, 1/10W, 1%, 0603
STD
STD
1
R267
Resistor, Chip, 1.37k, 1/16W, 1%, 0603
STD
STD
1
R4
Resistor, Chip, 54.9, 1/16W, 1%, 0402
STD
STD
5
R42, R50, R64, R74, R86
Resistor, Chip, 17.8k, 1/8W, 1%, 0805
STD
STD
5
R46, R56, R68, R79, R91
Resistor, Chip, 162k, 1/10W, 1%, 0603
STD
STD
5
R48, R59, R70, R84, R92
Resistor, Chip, 28.7k, 1/10W, 1%, 0603
STD
STD
7
R5, R52, R61, R72, R80,
R143, R146
Resistor, Chip, 10, 1/10W, 1%, 0603
STD
STD
1
R6
Resistor, Chip, 8.25k, 1/10W, 1%, 0603
STD
STD
2
R7, R22
Resistor, Chip, 15.4k, 1/10W, 1%, 0603
STD
STD
14
R8, R11, R14, R20, R28,
R29, R32, R34, R37, R39,
R135, R136, R153, R154
Resistor, Chip, 2.21, 1/10W, 1%, 0603
STD
STD
5
R94, R103, R105, R120,
R121
Resistor, Chip, 39.2k, 1/10W, 1%, 0603
STD
STD
4
R95, R96, R112, R113
Resistor, Chip, 150k, 1/10W, 1%, 0603
STD
STD
4
R99, R100, R116, R117
Resistor, Chip, 75.0k, 1/10W, 1%, 0603
STD
STD
7
RT1, RT2, RT3, RT4, RT5,
RT6, RT7
NTC Thermistor, 100k, 0603, 5%
Murata
NCP18WF104J03RB
1
U1
IC, 3+2 phase, IMVP-7 VCORE CPU and GPU Controller, QFN-48
TI
TPS59650RSL
1
U12
IC, Timer, Low-Power CMOS, SO-8
TI
TLC555CDR
1
U13
IC, Dual 10 ohm SPDT Analogy Switch, DGS_10P
TI
TS5A23157DGS
1
U14
IC, Nano Power, Open output comparators, PW14
TI
TLV3404IPW
1
U15
IC, USB to series port controller, QFN-32
TI
TUSB3410RHB
1
U16
IC, CMOS programmable controller, QFP-100
TI
TMS320F2808PZS
3
U17, U19, U20
IC, Dual Schmitt-trigger inverter, DCK-6
TI
SN74LVC2G07DCK
1
U18
IC, Dual-bit dual-supply bus transceiver, RSW-10
TI
SN74AVC2T245RSW
3
U2, U3, U4
IC, Dual high voltage, efficient synchronous MOSFET buck driver, QFN-8
TI
TPS51601ADRB
1
U5
IC, High performance, single synchronous step down controller, QFN-16
TI
TPS51219RTE
1
U6
IC, Complete DDR2, DDR3 and DDR3L memory power solution, QFN-20
TI
TPS51916RUK
1
U7
IC, Dual low dropout regulator, 500mA and 250mA outputs, PWP20
TI
TPS70102PWP
1
U8
IC, 150mA, low Iq, wide bandwidth, LDO, SC70
TI
TPS71712DCK
SLUU896 – March 2012
Submit Documentation Feedback
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU
SVID Power System
Copyright © 2012, Texas Instruments Incorporated
49
Schematics
www.ti.com
Table 13. EVM Major Components List (continued)
QTY
REF DES
Description
MFR
Part Number
1
U9
IC, Quadruple 2-input positive –AND gates, SO-14
TI
SN74HC08D
2
U10, U11
IC, Dual 4A High speed low side power MOSFET drivers, SO-8
TI
UCC27324D
1
X1
Crystal, controlled oscillators, 0.150”x0.528”
ABRACON
ABLS-20.000MHZ-B2-T
1
Y1
Crystal, controlled oscillators, 0.150”x0.528”
ABRACON
ABLS-12.000MHZ-B2-T
1
XU1
Socket, CPU
Molex
rPGA989
10
Schematics
50
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU
SVID Power System
Copyright © 2012, Texas Instruments Incorporated
SLUU896 – March 2012
Submit Documentation Feedback
6
1
R3
R4
54.9
TP18
R21
200k
TP16
C17
0.33uF
TP9
3
See Sheet 5
for FREQ selection
R16
20.0k
1
R13
C22
1uF
5
See Sheet 5
for OCP selection
and OSR setting
R2
130
0
R24
C26 100pF
4.02k
R23
TP21
C13 100pF
8.25k
R6
TP3
1
C25
RT2
100k
15.4k
R22
TP20
2
TP5
R26
100k
1
R25
1
C14
R18
10.0k
TP8
15.4k
R7
7
2.21
R14
2.21
R11
10
R5
TP17
C7
2.2uF
TP1
See Sheet 3
for GPU Vcore
8
See Sheet 2
for 3rd phase
TP6
RT1
100k
4
See Sheet 5 CPU
See Sheet 5
OCP selection
for FREQ selection and OSR setting
R1
42.2k
TP13
0
R15
CPU thrid phase: See sheet 2
GPU phase: See sheet 3
8
GPU OSR/USR selection: See sheet 5
GPU OCP selection: See sheet 5
CPU OCP selection: See sheet 5
GPU Switching frequency selection: See sheet 5
1
R17
1
C24
1
C21
0
R10
1
TP19
TP11
C8
10uF
C3
10uF
R12
TP4
CPU Switching frequency selection: See sheet 5
Not used
2.21
R20
TP15
C18
1uF
2.21
R8
C2
10uF
7
6
5
4
3
2
1
TP22
C23
1uF
TP10
TP7
C6
4.7uF
TP2
TP14
1
C10
10uF
1
C19 +
470uF
C15 +
470uF
C5
10uF
C20
+ 470uF
TP12
C11
10uF
+
C1
1nF
C16
470uF
C12
1nF
CPU and GPU Control, 1st and 2nd Phase CPU Power
L2
0.36uH
L1
0.36uH
C9
10uF
C4
10uF
22uF
C51
22uF
22uF
22uF
C52
C38
C37
TP29
TP26
22uF
C53
22uF
22uF
C54
1uF
2.21
C39
C33
R29
22uF
C40
1
C36
22uF
22uF C56
Not used
22uF
C55
C41
2.2uF
22uF
C42
R28
2.21
10uF
R31
0
10uF
22uF C58
C43
TP28
C57
TP25
TP24
TP23
10uF
10uF C59
C44
C27
10uF
10uF
22uF C60
C45
C28
10uF
1
C47
C31
1nF
10uF
C62
1
C35
1
1
C48
0.36uH
L3
R30
C30
10uF
TP27
10uF
10uF C61
C46
C29
10uF
10uF
C63
22uF
C49
1
C50
22uF
1
C32
CPU 3rd Phase Power
10uF
C64
+
+
1
C34
C94
22uF
C93
22uF
1
1
22uF
C95
1
C85
TP42
TP44
C84
TP34
C65
10uF
TP37
C83
TP38
TP32
TP31
1
C96
2.21
R32
C66
10uF
1
1
22uF
22uF
1
C88
C82
2.2uF
C79
2.2uF
C69
1nF
C87
C98
1uF
C86
C80
R37
C75
1uF
C68
10uF
2.21
C97
C67
10uF
1
C99
22uF
C89
TP43
R34
2.21
22uF
22uF
22uF
22uF
C101
C91
0
R41
0
R36
22uF
C102
C72
10uF
C90
TP45
2.21
R39
TP39
C71
10uF
C100
TP36
C70
10uF
22uF
C92
C73
10uF
GND_PWR
C74
1nF
1
0.36uH
L4
Not used
1
C81
1
0.36uH
L5
R40
TP41
1
C78
1
R35
TP33
1
GPU Power
1
TP40
C76 +
470uF
C77
+ 470uF
TP35
R91
162k
17.8k
R86
R79
162k
17.8k
R74
R68
162k
17.8k
R64
R56
162k
17.8k
R50
R46
162k
17.8k
R42
R92
28.7k
RT7
100k
R84
28.7k
RT6
100k
R70
28.7k
RT5
100k
R59
28.7k
RT4
100k
R48
28.7k
RT3
100k
C118
33nF
C115
33nF
C112
33nF
C108
33nF
C104
33nF
0
1
1
0
0
1
1
0
0
1
1
0
0
R93
R87, R93 = 0 for DCR sense
R88, R90 = 0 for Resistor Sense
1
1
0
1
C119
1
1
1
1
C120
1
C117
C116
0
R90
R88
R87
1
1
C114
1
1
C110
1
C106
C113
1
C111
1
1
C109
1
C107
1
1
C105
1
C103
1
1
0
R75, R85 = 0 for DCR sense
R77, R78 = 0 for Resistor Sense
R85
R78
R77
R75
R65, R71 = 0 for DCR sense
R66, R67 = 0 for Resistor Sense
R71
R67
R66
R65
R51, R60 = 0 for DCR sense
R53, R57 = 0 for Resistor Sense
R60
R57
R53
R51
R43, R49 = 0 for DCR sense
R44, R45 = 0 for Resistor Sense
R49
R45
R44
R43
TP56
TP55
TP54
TP53
TP52
TP51
TP50
TP49
TP48
TP47
1
R89
1
R83
1
R69
1
R55
1
R47
9
1
J8
J6
10
R80
R72
10
R61
10
R52
10
R76
R73
R58
R54
0
0
0
0
1
1
R81
R62
1
1
1
R82
1
R63
J9
J7
To controller
To controller
Current Feedback Selection and Filtering
Differential Voltage Feedback and termination
A phase can be disabled by pulling the corresponding xCSPx pin to 3.3V.
Default setting for CPU: 3 phase operation
Dafault setting for GPU: 2 phase operation
CPU:
Phase disable can be done in reverse order.Phase 3, then 2, then 1.
1. CPU 3 Phase operation: R47, R55, R69 open
2. CPU 2 Phase operation: R69 used 0ohm
3. CPU 1 Phase operation: R47, R55 used 0ohm
GPU:
1. GPU 2 Phase operation: R83, R89 open
2. GPU 1 Phase operation: R89 used 0ohm
Not used
To processor
To processor
9
13
10
1
1
R129
R128
R96
R98
R100
R102
R105
R107
R109
R111
R113
R115
R117
R119
R121
R123
R125
R127
150k
100k
75.0k
56.2k
39.2k
30.1k
24.3k
20.0k
150k
100k
75.0k
56.2k
39.2k
30.1k
24.3k
20.0k
13
12
11
10
1
11
TP58
TP57
R120
R122
R124
R126
30.1k
24.3k
20.0k
R112
150k
R118
R110
20.0k
39.2k
R108
24.3k
56.2k
R106
30.1k
R116
R103
39.2k
R114
R101
56.2k
75.0k
R99
100k
R97
75.0k
R95
100k
150k
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
Level 8 (MAX)
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1 (MIN)
OVER-CURRENT PROTECTION SELECTION
Optional parts for using TPS51640
Over-Shoot /Under-Shoot Reduction Selection:
1. CPU OSR/USR Default Setting: OSR/USR Reduction middle level
2. GPU OSR/USR Default Setting: OSR/USR Reduction off
Over Current Protection Selection:
1. CPU Over Current Protection Per Phase Default Setting: Jumper shorts on pin 7 and pin 8 to level 5 (set 40A)
2. GPU Over Current Protection Per Phase Default Setting: Jumper shorts on pin 7 and pin 8 to level 5 (set 40A)
Switching Frequency Selection:
1. CPU Switching Frequency Default Setting: Jumper shorts on pin13 and pin14 to set 300kHz
2. GPU Switching Frequency Default Setting: Jumper shorts on pin 11 and pin12 to set 385kHz
Not used
660kHz (MAX)
605kHz
550kHz
495kHz
440kHz
385kHz
330kHz
275kHz (MIN)
600kHz (MAX)
550kHz
500kHz
450kHz
400kHz
350kHz
300kHz
250kHz (MIN)
SWITCHING FREQUENCY SELECTION
R94
39.2k
R104
2.43k
OSR / USR SETTING
Frequency and OCP SELECTIONS for CPU and GPU
12
14
TP62
To processor
Q6
BSS123
D1
GREEN
R130
180
R146
10
10
R143
R139
10.5k
1
R137
R132
10.0k
15
14
1
0
TP65
TP61
C127
0.1uF
C131
10nF
15
J16
R135
2.21
0
R142
TP63
To controller
R141
30.1k
R134
1.00k
C121
1nF
S1: VCCIO Enable Pin
1
1
C156
1
TP60
TP59
1
C137
1
C158
22uF
C148
TP68
R136
2.21
C157
22uF
22uF
C155
22uF C147
C136
C135
2.2uF
TP64
C146
C128
0.1uF
VCCIO Output Selection:
1. Jumper shorts on pin1 and pin2 of J14 to set VCCIO: 1.05V(Default)
2. Jumper shorts on pin2 and pin3 of J14 to set VCCIO: 1.00V
Not used
R145
0
R133
1.00k
C130
1nF
R144
Q7
BSS123
D2
GREEN
R131
180
1
C138
1
C149
0
R140
C122
10uF
C140
C141
C126
10uF
TP66
1
C142
1
C143
+
22uF
1
C152 22uF C153
C134
1
TP67
TP69
L6
0.42uH
R138
C124
1nF
VCCIO Power
C145 22uF
C150 22uF C151
22uF
22uF
22uF
GND_PWR
1
C139
C125
10uF
C123
10uF
1
C144
1
C132
C129
330uF
22uF
C154
+
+
C133
330uF
Q9
BSS123
C165
10uF
0
R161
0
R148
10.0k
C166
2.2uF
R159
TP72
D3
GREEN
R147
180
C171
0.22uF
J20
C172
0.1uF
TP79
R160
20.0k
R158
10.0k
R151
1.00k
1nF
C184
R152
22.1k
0
R157
R149
10.0k
C174
C162
10uF
C175
C161
10uF
1
C169
1
1
10uF
10uF
VDDQ Power
1
1
1
TP76
TP77
C183
L7
1.0uH
C177
C159
1nF
TP75
R155
C176
C163
10uF
10uF C179 10uF C180 10uF C181 10uF C182
S3/S5 Enable Control, See datasheet for detail
1
C160
10uF
C173
0
R156
16
C178
TP78
2.21
R154
Not used
C170
2.2uF
TP74
TP71
1
C164
0.1uF
R153
2.21
TP73
R150
10.0k
16
TP70
+
330uF
C168
+
1
C167
C197
0.01uF
R184
100k
R182
8.06k
C198
0.1uF 0.1uF
C201
R183
10.0k
D6
BAT54
1
1
J23
1
17
R171
TP84
TP82
R185
10.0k
18
C199
0.1uF
10.0k
R176
R170
TP86
R169
1
+ C186
Silk:
VCCIO_DL
GFX_DL
CPU_DL1
CPU_DL2
5V Bias
Voltage Input
TP87
1
+ C187
VBAT Conversion Voltage Input:
9V -20V
18
U9:D
U9:C
U9:B
SN74HC08D
U9:A
C202 1uF
U11
UCC27324D
C196 1uF
U10
UCC27324D
J23: Default setting: Jumper shorts on to
Enable on board dynamic load
330
R186
0.1uF
C192
17
C189
10uF
VCCIO, GPU and CPU Dynamic Load:
1. Switch to "ON" position to enable the Dynamic Load
2. Switch to "OFF" position to disable the Dynamic Load (Default)
C188
0.1uF
Not used
TP83
R162
100k
1
GND_PWR
TP90
TP88
5VIN
TP81
U7
TPS70102PWP
VOUT1
PGD_1
RESET
NR/FB
OUT
D7
RED
R188
330
4
5
11
Q13
C193
2.2 uF
0.005
R189
TP93
30.1k
R166
30.1k
R165
R180
0.05
R178
0.01
C191
10uF
TP85
TP80
Q14
CSD16407Q5
R179
0.05
0.05
R177
R167
51.1k
R163
15.0k
CSD16407Q5
0.01uF
C194
TP89
TP94 C200
1uF
R190
330
D4
RED
150mA LDO
EN
GND
IN
D5
RED
3
2
1
U8
TPS71712DCK
1.2V LDO
NC
VIN2
12
13
14
15
16
17
18
19
20
3.3V LDO
VOUT2
VIN2
PwrPad
VOUT2
GND
SEQUENCE VSENSE2
ENABLE
MR1
VSENSE1
VIN1
MR2
VOUT1
NC
VIN1
NC
R187
330
D8
RED
10
9
8
7
6
5
4
3
2
1
1.8V LDO
Q11
R174
0.05
R172
0.01
DYNAMIC LOADs
TP92
Q12
R175
0.05
R173
0.01
1uF
C195
TP91
0.005
R181
CSD16407Q5
0.1uF
C190
R164
2.00k
CSD16407Q5
1
R168
C185
10uF
1
20
1
R191
C204
1nF
R192
100
19
Q16
BSS123
D9
GREEN
VR_ON
180
R215
BSS123
Q17
D10
GREEN
TP98
C_PGOOD
R216
180
10.0k
R220
10pF
C205
10pF
C206
C203
0.1uF
BSS123
Q18
D12
GREEN
G_PGOOD
TP97
10.0k
R221
R222
180
D11
RED
VR_HOT
BSS83P
Q15
Default Trim: R117 = Not used, R116 = 1.00k
R219
10.0k
R214
10.0k
S4: IMVP-7 VR Enable:
1. Switch to "ON" position to Enable TPS59650 controller
2. Switch to "OFF" position to Disable TPS59650 controller(Default)
Not used
R210
3.01k
R205
10.0k
Jumper to enter
I2C Mode
R217
180
20
19
1
I2C Terminal
J32
R211
3.01k
Logic Signal Termination and Status LED's
LED is ON when the logic signal is in the ACTIVE state
TP95
J30
TP96
1M
1M
1M
R196
R197
R212
330
R199
1M
R218
1.00k
R213
1.00k
C208
1uF
0
0
R202
R194
0.1uF
C207
J24, J31 are labview connections
for EVM testing
10.0k
10.0k
Support and Pull-ups
R208
R209
1M
R206
1M
R204
R207
1M
0
R203
0
R200
R201
1M
1M
R195
R198
1M
R193
1
R223
R224
75.0
R225
130
R226
43.2
1
Not used
uC Socket Main
uC Socket Others
V+
DM
DP
NC
V-
22
J35
J34
GREEN
D13
21
R234
470
FB1
J33
R229
R228
Jumper to use 5V from USB
33.2
33.2
R235
2.21k
22pF
10.0k
R231
C214
22pF
R227
C213
TP99 TP100
C209
0.1uF
22
21
1
1.50k
1
TP102
TP101
10.0k
R230
1
C211
Y1
2
0
R233
0
R232
0.01uF
C215
1
C212
For Internal software developmenet
USB to DSP
5V Bias option:
1. Jumper shorts on J33, 5V Bias used from USB. If USB 5V is used, external 5V supply from J22 should not be used.
2. No Jumper shorts on J33, 5V Bias used from external J22 (Default)
Not used
C210
0.1uF
U15
TUSB3410RHB
4
TP108
3
U20:B
U20:A
R241
2.74k
TP107
C218
0.1uF
C217
0.1uF
6
C219
2
5
C220
C221
0.1uF
VDDIO
VDDIO
VDDIO
VDD
VDD
VDD
VDD
VDD
VDD
1
TCK
TMS
TDI
TDO
50
9
8
95
1
70
64
61
60
58
56
53
51
48
45
44
82
2
11
41
49
55
62
69
77
87
89
94
84
75
74
73
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
GPIO34
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
52
54
57
63
67
71
72
83
91
99
79
92
4
6
7
100
5
43
0.1uF
76
C216
C222
0.1uF
U16:A
TMS320F2808PZS
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TRST
47
VSS2AGND
VDD2A18
VSS1AGND
VDD1A18
VSSAIO
VDDAIO
VSSA2
VDDA2
U16:B
TMS320F2808PZS
0.1uF
TP105
65
46
3
93
85
68
59
42
10
39
40
13
12
25
26
14
15
0.1uF
R240
2.74k
23
J39
1
C231
R237
2.00k
1
C232
X1
20
19
18
17
16
78
86
88
90
66
98
97
96
81
80
R238
2.00k
C223
C224
0.1uF
ADCREFIN
ADCREFP
ADCLO
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
21
22
23
34
33
32
31
30
29
28
27
24
38
35
37
36
C225
0.1uF
C226
TP104
0.1uF
C227
3
U19:B
1
C228
2
5
0.1uF
C229
6 U17:A
GREEN
D14
4
1
TP106
25
24
23
1
Differential Probe Test Point
GUI and Intel VRTT Tool Selection
1. Jumper shorts to use Intel VRTT Tool
2. No Jumper shorts to user GUI (Default)
J39: F2808 DSP Program Mode Selection:
1. Jumper shorts for F2808 DSP Program Mode
2. No Jumper shorts for normal operation (Default)
Not used
6
U19:A
C234
1uF
DSP to SVID
2
5
TP103
470
R236
C233
1uF
0.1uF
U18
SN74AVC2T245RSW
10
1
DIR1
DIR2
9
2 OE
A2
3
8
GND
A1
4
7
B2
VCCA
5
6
VCCB
B1
0.1uF
Level Shifting Tranceiver and Open Drain Buffers for DSP to SVID Translation
ADCINA3
ADCINA4
ADCINA5
ADCINA6
ADCINA7
XRS
X2
X1
XCLKIN
XCLKOUT
TEST2
TEST1
VDD3VFLADCRESEXT
EMU1
EMU0
ADCREFM
U16:C
TMS320F2808PZS
0.1uF
25
25
J38
J40
25
3
U17:B
J37
0.1uF
C230
4
R239
2.00k
J36
24
26
1
0
1
TP111
C235
C236
R253
0
1.8nF
C245
R252
2.00k
C244
100pF
R259
20.0k
C237
22uF
C243
5.62k
22uF
680pF
R245
22uF
C238
C239
10nF
R258
3.09k
2200pF
C247
1uF
C242
22uF
VIN
17
1
R256
SS
IMON
MODE
VOUT
EN
FSET
VFB
COMP
1
TPS51318
U21
VBST
VCCA
GND PGOOD
J42, J43: Optional VCCIO and VDDQ Enable
1. Jumper shorts on J42, J43 to Enable Optional VCCIO and VDDQ
2. No Jumper shorts on J42, J43 to Disable Optional VCCIO and VDDQ
Not used
R250
R247
5V POWER
Voltage Input
2
1
10 11 12 13 14 15
J41
1
3 2
4
16
VIN
PGND
7
SW
8
PGND
9
5
6
TP110
R261
R248
10.0k
R243
0
C240
0.22uF
1
R265
0
C253
1.8nF
C250
1uF
26
R267
1.37k
J42
R264
2.00k
100pF
680pF
5.62k
R246
10.0k
C252
R257
1
C251
R249
0
R244
475k
220pF
C241
R242
2.21
L8
0.42uH
C246
10nF
1
3 2
4
5
0
R268
R266
C254
2200pF
6
17
IMON
MODE
VOUT
SS
FSET
VFB
EN
VBST
VCCA
GND PGOOD
VIN
COMP
1
1
R262
10.0k
R254
0
C248
0.22uF
R263
0
R255
475k
R260
10.0k
C249
220pF
R251 1
2.21
L9
0.42uH
J43
26
Optional Solution for VCCIO and VDDQ
TP112
U22
TPS51318
16
VIN
PGND
7
SW
8
PGND
9
TP109
10 11 12 13 14 15
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjukku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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EVALUATION BOARD/KIT/MODULE (EVM)
WARNINGS, RESTRICTIONS AND DISCLAIMERS
For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in
laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks
associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end
product.
Your Sole Responsibility and Risk. You acknowledge, represent and agree that:
1.
2.
3.
4.
You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug
Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees,
affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.
You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable
regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates,
contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical)
between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to
minimize the risk of electrical shock hazard.
You will employ reasonable safeguards to ensure that your use of the EVM will not result in any property damage, injury or death, even
if the EVM should fail to perform as described or expected.
You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.
Certain Instructions. It is important to operate this EVM within TI’s recommended specifications and environmental considerations per the
user guidelines. Exceeding the specified EVM ratings (including but not limited to input and output voltage, current, power, and
environmental ranges) may cause property damage, personal injury or death. If there are questions concerning these ratings please contact
a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the
specified output range may result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or
interface electronics. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the
load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures
greater than 60°C as long as the input and output are maintained at a normal ambient operating temperature. These components include
but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors which can be identified using the
EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during normal operation, please
be aware that these devices may be very warm to the touch. As with all electronic evaluation tools, only qualified personnel knowledgeable
in electronic measurement and diagnostics normally found in development environments should use these EVMs.
Agreement to Defend, Indemnify and Hold Harmless. You agree to defend, indemnify and hold TI, its licensors and their representatives
harmless from and against any and all claims, damages, losses, expenses, costs and liabilities (collectively, "Claims") arising out of or in
connection with any use of the EVM that is not in accordance with the terms of the agreement. This obligation shall apply whether Claims
arise under law of tort or contract or any other legal theory, and even if the EVM fails to perform as described or expected.
Safety-Critical or Life-Critical Applications. If you intend to evaluate the components for possible use in safety critical applications (such
as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, such as devices
which are classified as FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate
Assurance and Indemnity Agreement.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH
ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
DAMAGES.
Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety
programs, please visit www.ti.com/esh or contact TI.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
REGULATORY COMPLIANCE INFORMATION
As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal
Communications Commission (FCC) and Industry Canada (IC) rules.
For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,
DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer
use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency
interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will
be required to take whatever measures may be required to correct this interference.
General Statement for EVMs including a radio
User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and
power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local
laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this
radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and
unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory
authorities, which is responsibility of user including its acceptable authorization.
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
Caution
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause
harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the
equipment.
FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to
cause harmful interference in which case the user will be required to correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If
this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
on, the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the
equipment.
Concerning EVMs including radio transmitters
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this
device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired
operation of the device.
Concerning EVMs including detachable antennas
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain
approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should
be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.
This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum
permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain
greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.
Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
l'utilisateur pour actionner l'équipement.
Concernant les EVMs avec appareils radio
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est
autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout
brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain
maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à
l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente
(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans
cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
SPACER
【Important Notice for Users of this Product in Japan】
】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1.
2.
3.
Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of
Japan,
Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this
product, or
Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with
respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note
that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.
Texas Instruments Japan Limited
(address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan
http://www.tij.co.jp
【ご使用にあたっての注】
本開発キットは技術基準適合証明を受けておりません。
本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。
日本テキサス・インスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
http://www.tij.co.jp
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For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished
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