SLVS216B − JUNE 1999 − JUNE 2008
features
D
D
D
D
D
D
D
D
D
D
D
D
applications
Up to 150-mA Output Current
Less Than 10-mVpp Output Voltage Ripple
No Inductors Required/Low EMI
Regulated 5-V ±4% Output
Only Four External Components Required
Up to 90% Efficiency
2.7-V to 5.4-V Input Voltage Range
60-µA Quiescent Supply Current
0.05-µA Shutdown Current
Load Isolated in Shutdown
Space-Saving Thermally-Enhanced TSSOP
PowerPAD Package
Evaluation Module Available
(TPS60110EVM−132)
Replaces DC/DC Converters With Inductors in
− Battery-Powered Applications
− Li-Ion Battery to 5-V Conversion
− Portable Instruments
− Battery-Powered Microprocessor
Systems
− Miniature Equipment
− Backup-Battery Boost Converters
− PDAs
− Laptops
− Handheld Instrumentation
− Medical Instruments
output voltage ripple
description
5.2
The TPS60111 features either constant frequency
mode to minimize noise and output voltage ripple
or the power-saving pulse-skip mode to extend
battery life at light loads. The TPS60111 switching
frequency is 300 kHz. The logic shutdown function
reduces the supply current to 1-µA (max) and
disconnects the load from the input. Special
current-control circuitry prevents excessive current from being drawn from the battery during
start-up. This dc/dc converter requires no
inductors and has low EMI. It is available in the
small 20-pin TSSOP PowerPAD package
(PWP).
5.15
VO − Output Voltage − V
The TPS60111 step-up, regulated charge pump
generates a 5-V ±4% output voltage from a 2.7-V
to 5.4-V input voltage (three alkaline, NiCd, or
NiMH batteries; or, one lithium or lithium ion
battery). Output current is 150 mA from a 3-V
input. Only four external capacitors are needed to
build a complete low-noise dc/dc converter. The
push-pull operating mode of two single-ended
charge pumps assures the low output voltage
ripple as current is continuously transferred to the
output. From a 3-V input, the TPS60111 can start
into full load with loads as low as 33 Ω.
5.1
5.05
5
SKIP =COM = CLK = 0 V
VIN = 3.6 V
IO = 150 mA
CO = 22 µF + 10 µF
X5R Ceramic
4.95
4.9
4.85
4.8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
t − Time − µs
typical operating circuit
INPUT
2.7 V to
5.4 V
CIN
4.7 µF
SKIP COM CLK
+
IN
IN
C1F
1 µF
OUT
OUT
TPS60110 FB
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
OUTPUT
5V
150 mA
+ CO
15 µF
C2F
1 µF
SYNC
PGND GND
Figure 1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright 1999 − 2008, Texas Instruments Incorporated
! " #$ %! " &$'(# ! ) !%*
)$#!" # ! "&%# # ! " &% !+% !% " %, " "! $%!"
"! ) ) - !.* )$#! & #%""/ ) %" ! %#%"" (. #($)%
!%"!/ (( & %!% "*
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLVS216B − JUNE 1999 − JUNE 2008
PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
GND
SYNC
ENABLE
FB
OUT
C1+
IN
C1−
PGND
PGND
20
19
18
17
16
15
14
13
12
11
GND
CLK
COM
SKIP
OUT
C2+
IN
C2−
PGND
PGND
Thermal
Pad
Figure 2. Bottom View of PWP Package,
Showing the Thermal Pad
AVAILABLE OPTIONS
PACKAGE
TSSOP†
(PWP)
TPS60111PWP
† This package is available taped and reeled. To order this packaging
option, add an R suffix to the part number (e.g., TPS60111PWPR).
Terminal Functions
TERMINAL
NAME
NO.
I/O
I
DESCRIPTION
CLK
19
Input for external clock signal. If the internal clock is used, connect this terminal to GND.
C1+
6
Positive terminal of the charge-pump capacitor C1F
C1−
8
Negative terminal of the charge-pump capacitor C1F
C2+
15
Positive terminal of the charge-pump capacitor C2F
C2−
13
COM
18
I
Mode selection.
When COM is logic low the charge pump operates in push-pull mode to minimize output ripple. When COM is
connected to IN the regulator operates in single-ended mode requiring only one flying capacitor.
ENABLE
3
I
ENABLE Input. The device turns off, the output disconnects from the input, and the supply current decreases to
0.05 µA when ENABLE is a logic low. ENABLE high may only be applied when VIN is inside the recommended
operating range.
FB
4
I
FEEDBACK input. Connect FB to OUT as close to the load as possible to achieve best regulation. Resistive divider
is on-chip to match internal reference voltage of 1.22 V.
Negative terminal of the charge-pump capacitor C2F
GND
1, 20
IN
7, 14
I
GROUND. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
Supply Input. Connect to an input supply in the 2.7-V to 5.4-V range. Bypass IN to GND with a (CO/2) µF capacitor.
Connect both INs through a short trace.
OUT
5, 16
O
Regulated 5-V power output. Connect both OUTs through a short trace and bypass OUT to GND with the output
filter capacitor CO.
PGND
9−12
PGND power ground. Charge-pump current flows through this pin. Connect all PGNDs together.
SKIP
17
I
Mode selection. When SKIP is logic low the charge pump operates in constant-frequency mode. Thus output ripple
and noise are minimized. When SKIP is connected to IN, the regulator operates in low-quiescent-current
pulse-skip mode.
SYNC
2
I
Selection for external clock signal. Connect to GND to use the internally generated clock signal. Connect to IN
for external synchronization. In this case, the clock signal needs to be fed through CLK.
2
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SLVS216B − JUNE 1999 − JUNE 2008
absolute maximum ratings (unless otherwise noted)†‡
Input voltage range, VI (IN, OUT, ENABLE, SKIP, COM, CLK, FB, SYNC) . . . . . . . . . . . . . . . . −0.3 V to 5.5 V
Differential input voltage, VID (C1+, C2+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VO + 0.3 V)
Differential input voltage, VID (C1−, C2− to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VIN + 0.3 V)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ VENABLE, VSKIP, VCOM, VCLK and VSYNC can exceed VIN up to the maximum rated voltage without increasing the leakage current
drawn by these mode select inputs.
DISSIPATION RATING TABLE 1 − FREE-AIR TEMPERATURE (see Figure 3)
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
70°C
TA = 70
C
POWER RATING
85°C
TA = 85
C
POWER RATING
PWP
700 mW
5.6 mW/°C
448 mW
364 mW
DISSIPATION RATING TABLE 2 − CASE TEMPERATURE (see Figure 4)
PACKAGE
TC ≤ 62.5
62.5°C
C
POWER RATING
DERATING FACTOR
ABOVE TC = 62.5°C
TC = 70
70°C
C
POWER RATING
TC = 85
85°C
C
POWER RATING
PWP
25 W
285.7 mW/°C
22.9 W
18.5 W
DISSIPATION DERATING CURVE§
vs
FREE-AIR TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION§
vs
CASE TEMPERATURE
30
PD − Maximum Continuous Dissipation − W
PD − Maximum Continuous Dissipation − mW
1400
1200
1000
800
PWP Package
RθJA = 178°C/W
600
400
200
0
25
50
75
100
125
150
TA − Free-Air Temperature − °C
25
20
PWP Package
15
10
Measured with the exposed thermal pad
coupled to an infinite heat sink with a
thermally conductive compound (the
thermal conductivity of the compound
is 0.815 W/m ⋅ °C). The RθJC is 3.5°C/W.
5
0
25
Figure 3
50
75
100
125
TC − Case Temperature − °C
150
Figure 4
§ Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum temperature of 150°C.
It is recommended not to exceed a junction temperature of 125°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLVS216B − JUNE 1999 − JUNE 2008
electrical characteristics at CIN = 15 µF, C1F = C2F = 2.2 µF†, CO = 33 µF, TC = −40°C to 85°C,
VIN = 3 V, VFB = VO, VENABLE = VIN, VSKIP = VIN or 0 V and VCOM = VCLK = VSYNC = 0 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
VIN
Input voltage
2.7
IO(MAX)
Maximum output current
150
VO
Output voltage
VO(RIP)
IO(LEAK)
Output voltage ripple
5
5.2
3 V < VIN < 5 V,
0 < IO < 150 mA
4.8
5
5.2
5 V < VIN < 5.4 V,
0 < IO < 150 mA
VSKIP = 0 V
VENABLE = 0 V
4.8
5
10‡
5.25
60
90
Quiescent current
(no-load input current)
IDD(SDN)
fOSC(int)
Shutdown supply current
VIN = 3.6 V,
VIN = 3.6 V
fOSC(ext)
External clock frequency
External clock duty cycle
VSYNC = VIN,
VSYNC = VIN,
Efficiency
IO = 75 mA
VINL
Input voltage low,
ENABLE, SKIP, COM, CLK, SYNC
VIN = 2.7 V
VINH
Input voltage high,
ENABLE, SKIP, COM, CLK, SYNC
VIN = 5.4 V
II(LEAK)
Input leakage current,
ENABLE, SKIP, COM, CLK, SYNC
VENABLE = VSKIP = VCOM = VCLK =
VSYNC = VGND or VIN
Output load regulation
VO = 5 V,
TC = 25°C
1 mA < IO < 150 mA
Output line regulation
3 V < VIN < 5 V,
IO = 75 mA,
VO = 5 V,
TC = 25°C
Short circuit current
VIN = 3.6 V
TC = 25°C
VO = 0 V,
VIN = 2.7 V to 5.4 V
VIN= 2.7V to 5.4 V
V
2.8
V
mVPP
µA
µA
mA
0.05
1
µA
200
300
400
kHz
400
600
800
kHz
20%
80%
80%
0.3 ×
VIN
0.7 ×
VIN
† Use only ceramic capacitors with X5R or X7R dielectric as flying capacitors.
‡ Achieved with CO = 22 µF + 10 µF X5R dielectric ceramic capacitor
POST OFFICE BOX 655303
1
VIN = 3.6 V
VENABLE = 0 V
UNIT
mA
4.8
VSKIP = VIN = 3.6 V
VSKIP = 0 V,
4
5.4
0 < IO < 75 mA,
TC = 25°C
Output leakage current
Internal switching frequency
MAX
2.7 V < VIN < 3 V,
VO(Start-Up) = 5 V,
IO = 150 mA,
VIN = 3.6 V,
IQ
TYP
• DALLAS, TEXAS 75265
V
V
0.01
0.002
0.1
µA
%/mA
0.6
%/V
150
mA
SLVS216B − JUNE 1999 − JUNE 2008
TYPICAL CHARACTERISTICS†
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
100
VIN = 2.7 V
90
V(SKIP) = 0 V
VIN = 3 V
80
70
VIN = 3.6 V
60
Efficiency − %
Efficiency − %
VIN = 3 V
80
70
VIN = 3.3 V
50
40
40
20
20
10
V(SKIP) = VIN
1
VIN = 3.6 V
50
30
0
0.1
VIN = 3.3 V
60
30
10
10
100
0
1000
1
1000
IO − Output Current − mA
Figure 6
Figure 5
QUIESCENT SUPPLY CURRENT
vs
INPUT VOLTAGE
QUIESCENT SUPPLY CURRENT
vs
INPUT VOLTAGE
90
3.6
V(SKIP) = VIN
V(SKIP) = 0 V
I Q − Quiescent Supply Current − mA
85
80
75
70
65
60
55
50
45
40
2.5
100
10
IO − Output Current − mA
I Q − Quiescent Supply Current − µ A
VIN = 2.7 V
90
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
3
3.5
4
4.5
5
5.5
1.6
2.5
VIN − Input Voltage − V
3
3.5
4
4.5
5
5.5
VIN − Input Voltage − V
Figure 7
Figure 8
† TC = 25°C, VCOM = VSYNC = 0 V, CIN = 15 µF, C1F and C2F = 2.2 µF (X7R ceramic), CO = 33 µF, unless otherwise noted
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLVS216B − JUNE 1999 − JUNE 2008
TYPICAL CHARACTERISTICS†
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.3
5.3
V(SKIP) = 0 V
V(SKIP) = VIN
5.2
VIN = 5.4 V
VIN = 4 V
5.1
VO − Output Voltage − V
VO − Output Voltage − V
5.2
VIN = 3.6 V
5
VIN = 3 V
4.9
VIN = 5.4 V
VIN = 4 V
VIN = 3.6 V
5.1
5
VIN = 3 V
4.9
VIN = 2.7 V
VIN = 2.7 V
4.8
4.8
4.7
1
100
10
4.7
1000
1
Figure 10
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5.1
5.1
5.08
5.08
5.06
5.06
VO − Output Voltage − V
VO − Output Voltage − V
V(SKIP) = 0 V
IO = 150 mA
5.02
IO = 1 mA to 10 mA
5
4.98
4.96
5.02
5
4.98
4.96
4.94
4.92
4.92
3
3.5
4
4.5
5
5.5
V(SKIP) = VIN
IO = 1 mA to 150 mA
5.04
4.94
4.9
2.5
4.9
2.5
VIN − Input Voltage − V
3
3.5
4
4.5
VIN − Input Voltage − V
Figure 11
Figure 12
† TC = 25°C, VCOM = VSYNC = 0 V, CIN = 15 µF, C1F and C2F = 2.2 µF (X7R ceramic), CO = 33 µF, unless otherwise noted
6
1000
IO − Output Current − mA
Figure 9
5.04
100
10
IO − Output Current − mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
5.5
SLVS216B − JUNE 1999 − JUNE 2008
TYPICAL CHARACTERISTICS†
OUTPUT VOLTAGE
vs
TIME
OUTPUT VOLTAGE
vs
TIME
5.07
V(SKIP) = 0 V
VIN = 3.6 V
IO = 150 mA
CO = 22 µF + 10 µF
X5R ceramic
5.04
5.03
5.02
5.01
0
2
Pulse-Skip Mode
Constant
Frequency
Mode
VO − Output Voltage − V
VO − Output Voltage − V
5.05
6
4
5.03
5.01
V(SKIP) = VIN
VIN = 3.6 V
IO = 150 mA
4.99
10
8
5.05
0
10
20
t − Time − µs
Figure 13
LOAD TRANSIENT RESPONSE
VO − Output Voltage − V
5.04
5.03
5.02
I O − Output Current − mA
5.01
Constant
Frequency
Mode
V(SKIP) = 0 V
IO = 10 mA to 150 mA
VIN = 3.6 V
100
0
0
2
4
6
8
10
12
14
16
18
20
I O − Output Current − mA
VO − Output Voltage − V
LOAD TRANSIENT RESPONSE
200
50
Figure 14
5.05
300
40
30
t − Time − µs
5.08
V(SKIP) = VIN = 3.6 V
IO = 10 mA to 150 mA
5.06
Pulse-Skip Mode
5.04
5.02
5
300
200
100
0
0
2
4
6
8
10
12
14
16
18
20
t − Time − ms
t − Time − ms
Figure 15
Figure 16
† TC = 25°C, VCOM = VSYNC = 0 V, CIN = 15 µF, C1F and C2F = 2.2 µF (X7R ceramic), CO = 33 µF, unless otherwise noted
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLVS216B − JUNE 1999 − JUNE 2008
TYPICAL CHARACTERISTICS†
LINE TRANSIENT RESPONSE
VO − Output Voltage − V
VO − Output Voltage − V
LINE TRANSIENT RESPONSE
5.08
V(SKIP) = 0 V
IO = 150 mA
5.06
Constant
Frequency
Mode
5.04
5.02
5.08
5.02
5
4
3
2
0
1
2
3
4
5
6
7
8
9
10
V IN − Input Voltage − V
5
5
4
3
2
0
1
2
3
4
5
6
7
8
9
10
t − Time − ms
t − Time − ms
Figure 18
Figure 17
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE‡
FREQUENCY SPECTRUM
PULSE-SKIP MODE‡
90
100
V(SKIP) = 0 V
VIN = 3 V
IO = 150 mA
RBW = 300 Hz
80
70
V(SKIP) = VIN
VIN = 3 V
IO = 150 mA
RBW = 300 Hz
80
60
Output − dB µ V
Output − dB µ V
Pulse-Skip Mode
5.04
5
V IN − Input Voltage − V
V(SKIP) = VIN
IO = 150 mA
5.06
50
40
60
40
30
20
20
10
0
0
0
2.5
7.5
5
10
0
2.5
5
7.5
f − Frequency − MHz
f − Frequency − MHz
Figure 19
Figure 20
† TC = 25°C, VCOM = VSYNC = 0 V, CIN = 15 µF, C1F and C2F = 2.2 µF (X7R ceramic), CO = 33 µF, unless otherwise noted
‡ Test circuit: TPS60110EVM−132 with TPS60111
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10
SLVS216B − JUNE 1999 − JUNE 2008
TYPICAL CHARACTERISTICS†
FREQUENCY SPECTRUM
CONSTANT FREQUENCY MODE‡
FREQUENCY SPECTRUM
PULSE-SKIP MODE‡
90
90
V(SKIP) = 0 V
VIN = 3 V
IO = 10 mA
RBW = 300 Hz
80
70
60
Output − dB µ V
Output − dB µ V
70
V(SKIP) = VIN
VIN = 3 V
IO = 10 mA
RBW = 300 Hz
80
50
40
60
50
40
30
30
20
20
10
10
0
0
0
2.5
5
7.5
10
0
2.5
f − Frequency − MHz
7.5
5
10
f − Frequency − MHz
Figure 21
Figure 22
EFFICIENCY
vs
INPUT VOLTAGE
START-UP TIMING
6
100
IO = 150 mA
90
5
R0 = 33.3 Ω
VIN = 3 V
Efficiency − %
70
VO − Output Voltage − V
80
Skip = High
60
Skip = Low
50
40
30
20
4
3
Enable
2
OUTPUT
1
0
10
0
2.5
3
3.5
4
5
4.5
5.5
−1
0
200
400
600
800
1000
1200
t − Time −µs
VIN − Input Voltage − V
Figure 23
Figure 24
† TC = 25°C, VCOM = VSYNC = 0 V, CIN = 15 µF, C1F and C2F = 2.2 µF (X7R ceramic), CO = 33 µF, unless otherwise noted
‡ Test circuit: TPS60110EVM−132 with TPS60111
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLVS216B − JUNE 1999 − JUNE 2008
detailed description
operating principle
The TPS60111 charge pump provides a regulated 5-V output from a 2.7-V to 5.4-V input. It delivers a maximum
load current of 150 mA. Designed specifically for space critical battery powered applications, the complete
charge pump circuit requires only four external capacitors. The circuit can be optimized for highest efficiency
at light loads or lowest output noise. The TPS60111 consists of an oscillator, a 1.22-V bandgap reference, an
internal resistive feedback circuit, an error amplifier, high current MOSFET switches, a shutdown/start-up
circuit, and a control circuit (Figure 25).
CHARGE PUMP 1
IN
0°
T11
OSCILLATOR
T12
180°
C1+
C1F
T13
SKIP
C1−
T14
OUT
COM
CLK
PGND
CONTROL
CIRCUIT
SYNC
FB
−
CHARGE PUMP 2
IN
+
T21
VREF +
−
T22
C2+
ENABLE
SHUTDOWN/
START-UP
CONTROL
−
T23
+
+
−
T24
C2F
C2−
OUT
0.8 × VIN
PGND
GND
Figure 25. Functional Block Diagram TPS60111
The oscillator runs at a 50% duty cycle. The device consists of two single-ended charge pumps which operate
with 180° phase shift. Each single ended charge pump transfers charge into its transfer capacitor (CxF) in one
half of the period. During the other half of the period (transfer phase), CxF is placed in series with the input to
transfer its charge to CO. While one single-ended charge pump is in the charge phase, the other one is in the
transfer phase. This operation guarantees an almost constant output current which ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name doubler). In order to provide a regulated fixed output voltage of 5 V, the
TPS60111 uses either pulse-skip mode or constant-frequency mode. Pulse-skip mode and constant-frequency
mode are externally selected via the SKIP input pin.
10
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SLVS216B − JUNE 1999 − JUNE 2008
detailed description (continued)
start-up procedure
During start-up, i.e. when ENABLE is set from logic low to logic high, the switches T12 and T14 (charge pump
1), and the switches T22 and T24 (charge pump 2) are conducting to charge up the output capacitor until the
output voltage VO reaches 0.8×VIN. When the start-up comparator detects this limit, the IC begins to operate
in the mode selected with SKIP and COM. This start-up charging of the output capacitor guarantees a short
start-up time and eliminates the need for a Schottky diode between IN and OUT.
pulse-skip mode
In pulse-skip mode (SKIP = high), the error amplifier disables switching of the power stages when it detects an
output higher than 5 V. The oscillator halts. The IC then skips switching cycles until the output voltage drops
below 5 V. Then the error amplifier reactivates the oscillator and switching of the power stages starts again. The
pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except bandgap reference and error amplifier when the output is higher than 5 V. When
switching is disabled from the error amplifier, the load is also isolated from the input. SKIP is a logic input and
should not remain floating. The typical operating circuit of the TPS60111 in pulse skip mode is shown in Figure
1.
constant-frequency mode
When SKIP is low, the charge pump runs continuously at the frequency fOSC. The control circuit, fed from the
error amplifier, controls the charge on C1F and C2F by driving the gates of the FETs T12/T13 and T22/T23,
respectively. When the output voltage falls, the gate drive increases, resulting in a larger voltage across C1F
and C2F. This regulation scheme minimizes output ripple. Since the device switches continuously, the output
noise contains well-defined frequency components, and the circuit requires smaller external capacitors for a
given output ripple. However, constant-frequency mode, due to higher operating current, is less efficient at light
loads than pulse-skip mode.
SKIP COM CLK
INPUT
2.7 V to 5.4 V
CIN
4.7 µF
IN
IN
+
C1F
1 µF
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
OUTPUT
5 V 150 mA
OUT
OUT
TPS60111 FB
+
CO = 33 µF
C2F
1 µF
SYNC
PGND GND
Figure 26. Typical Operating Circuit TPS60111 in Constant Frequency Mode
Table 1. Tradeoffs Between Operating Modes
FEATURE
PULSE-SKIP MODE
(SKIP = High)
Best light-load efficiency
CONSTANT-FREQUENCY MODE
(SKIP = Low)
X
Smallest external component size for a given output ripple
X
Output ripple amplitude
Small amplitude
Very small amplitude
Output ripple frequency
Variable
Constant
Very good
Good
Load regulation
NOTE: Even in pulse-skip mode the output ripple amplitude is small if the push-pull operating mode is selected via COM.
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detailed description (continued)
push-pull operating mode
In push-pull operating mode (COM = low), the two single-ended charge pumps operate with 180° phase shift.
The oscillator signal has a 50% duty cycle. Each single-ended charge pump transfers charge into its transfer
capacitor (CxF) in one-half of the period. During the other half of the period (transfer phase), CxF is placed in
series with the input to transfer its charge to CO. While one single-ended charge pump is in the charge phase,
the other one is in the transfer phase. This operation guarantees an almost constant output current which
ensures a low output ripple. COM is a logic input and should not remain floating. The typical operating circuit
of the TPS60111 in push-pull mode is shown in Figure 1 and Figure 26.
single-ended operating mode
When COM is high, the device runs in single-ended operating mode. The two single-ended charge pumps
operate in parallel without phase shift. They transfer charge into the transfer capacitor (CF) in one half of the
period. During the other half of the period (transfer phase), CF is placed in series with the input to transfer its
charge to CO. In single-ended operating mode only one transfer capacitor (CF = C1F + C2F) is required, resulting
in less board space.
SKIP COM CLK
INPUT
2.7 V to 5.4 V
IN
IN
CIN
4.7 µF
+
OUT
OUT
TPS60111 FB
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
OUTPUT
5 V 150 mA
+
CO = 15 µF
SYNC
PGND GND
CF = 2.2 µF
Figure 27. Typical Operating Circuit TPS60111 in Single-Ended Operating Mode
Table 2. Tradeoffs Between Operating Modes
FEATURE
Output ripple amplitude
PUSH-PULL MODE
(COM = Low)
SINGLE-ENDED MODE
(COM = High)
Small amplitude
Large amplitude
Smallest board space
12
X
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detailed description (continued)
shutdown
Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control
logic. The device typically draws 0.05-µA (1-µA max) of supply current in this mode. Leakage current drawn from
the output is as low as 1 µA max. The device exits shutdown once ENABLE is set high level. The typical no-load
shutdown exit time is 20 µs. When the device is in shutdown, the load is isolated from the input and the output
is high impedance.
external clock signal
If the device operates at a user-defined frequency, an external clock signal can be used. Therefore, SYNC needs
to be connected to IN and the external oscillator signal can drive CLK. The maximum external frequency is
limited to 800 kHz. The switching frequency of the converter is half of the external oscillator frequency. It is
recommended to operate the charge pump in constant-frequency mode if an external clock signal is used so
that the output noise contains only well-defined frequency components.
External Clock
SKIP COM CLK
INPUT
2.7 V to 5.4 V
IN
IN
CIN
4.7 µF
+
C1F
1 µF
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
OUTPUT
5 V 150 mA
OUT
OUT
TPS60111 FB
+
CO = 33 µF
C2F
1 µF
SYNC
PGND GND
Figure 28. Typical Operating Circuit TPS60111 With External Synchronization
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APPLICATION INFORMATION
capacitor selection
The TPS60111 requires only four external capacitors as shown in the basic application circuit. Their values are
closely linked to the output current capacity, output noise requirements, and mode of operation. Generally, the
transfer capacitors (CxF) will be the smallest.
The input capacitor improves system efficiency by reducing the input impedance and stabilizes the input current.
CIN is recommended to be about two to four times as large as CxF.
The output capacitor (CO) can be selected from 8-times to 50-times larger than CxF, depending on the mode
of operation and ripple tolerance†. Tables 3 and 4 show capacitor values recommended for low
quiescent-current operation (pulse-skip mode) and for low output voltage ripple operation (constant-frequency
mode). A recommendation is given for smallest size.
Table 3. Recommended Capacitor Values for Low Quiescent-Current Operation†
(pulse-skip mode)
VIN
[V]
CIN
[µF]
IO [mA]
TANTALUM
3.6
75
3.6
75
3.6
150
3.6
150
CO
[µF]
CxF
[µF]
CERAMIC
4.7
TANTALUM
1
4.7 (X7R)
4.7
15
150
1
1
4.7 (X7R)
CERAMIC
OUTPUT
VOLTAGE
RIPPLE VPP
[mV]
10 (X5R)
15
105
150
1
10 (X5R)
105
† All measurements are done with additional 1-µF X7R ceramic capacitors at input and output.
Table 4. Recommended Capacitor Values for Low Output Voltage Ripple Operation†
(constant-frequency mode)
VIN
[V]
CIN
[µF]
IO
[mA]
TANTALUM
3.6
75
3.6
75
3.6
150
3.6
150
CO
[µF]
CxF
[µF]
CERAMIC
4.7
TANTALUM
1
4.7 (X7R)
4.7
33
1
1
4.7 (X7R)
CERAMIC
10
22 + 10, (X5R)
33
1
14
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17
22 + 10, (X5R)
† All measurements are done with additional 1-µF X7R ceramic capacitors at input and output.
† In constant-frequency mode always select CO ≥ 33 µF
OUTPUT
VOLTAGE
RIPPLE VPP
[mV]
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SLVS216B − JUNE 1999 − JUNE 2008
APPLICATION INFORMATION
For the TPS60111, the smallest board space size can be achieved using Sprague’s 595D-series tantalum
capacitors for input and output. However, with the trend towards high capacitance ceramic capacitors in smaller
size packages, these type of capacitors might soon become competitive in size.
Table 5. Recommended Capacitors
MANUFACTURER
PART NUMBER
CAPACITANCE
TYPE
Taiyo Yuden
LMK212BJ105KG−T
LMK212BJ225MG−T
LMK316BJ475KL−T
JMK316BJ106ML−T
LMK432BJ226MM−T
1 µF
2.2 µF
4.7 µF
10 µF
22 µF
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
AVX
0805ZC105KAT2A
1206ZC225KAT2A
TPSC475K035R0600
TPSC156K020R0450
TPSC336K010R0375
1 µF
2.2 µF
4.7 µF
15 µF
33 µF
Ceramic
Ceramic
Tantalum
Tantalum
Tantalum
Sprague
595D475X0016A2T
595D156X06R3A2T
595D156X0016B2T
595D336X06R3A2T
595D336X0016B2T
595D336X0016C2T
4.7 µF
15 µF
15 µF
33 µF
33 µF
33 µF
Tantalum
Tantalum
Tantalum
Tantalum
Tantalum
Tantalum
Kemet
T494B475M010AS
T494C156K010AS
T494C336K010AS
4.7 µF
15 µF
33 µF
Tantalum
Tantalum
Tantalum
Table 6 lists the manufacturers of recommended capacitors. In most applications surface-mount tantalum
capacitors will be the right choice. However, ceramic capacitors will provide the lowest output voltage ripple due
to their typically lower ESR.
Table 6. Recommended Capacitor Manufacturers
MANUFACTURER
CAPACITOR TYPE
INTERNET
Taiyo Yuden
X7R/X5R ceramic
www.t−yuden.com
AVX
X7R/X5R ceramic
TPS−series tantalum
www.avxcorp.com
Sprague
595D−series tantalum
593D−series tantalum
www.vishay.com
Kemet
T494−series tantalum
www.kemet.com
power dissipation
The power dissipated in the TPS60111 depends on output current and is approximated by:
P DISS + I O
ǒ2 VIN * VOǓ for I Q tt
IO
PDISS must be less than that allowed by the package rating. See the ratings for 20-PowerPAD package
power-dissipation limits and deratings.
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APPLICATION INFORMATION
layout
All capacitors should be soldered in close proximity to the IC. A PCB layout proposal for a two-layer board is
given in Figure 29. Care has been taken to connect both single-ended charge pumps symmetrically to the load
to achive optimized output voltage ripple performance. The proposed layout also provides improved thermal
performance as the exposed leadframe is soldered to the PCB. The bottom layer of the PCB is a ground plain
only. All ground areas on the PCB should be connected. Connect ground areas on top layer to the bottom layer
via through hole connections.
OUT
GND
GND
CLK
SYNC
COM
ENABLE
SKIP
C1+
C2+
GND
C1−
C2−
GND
GND
IN
Figure 29. Recommended PCB Layout for TPS60111 (top view)
The evaluation module designed for the TPS60110 can, with slight modifications, be used for evaluation of the
TPS60111. The EVM can be ordered under literature code SLVP132 or under product code
TPS60110EVM−132.
16
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APPLICATION INFORMATION
applications proposals
TPS60111 with LC output filter for ultra low ripple
For applications where extremely low output ripple is required, a small LC filter is recommended. This is shown
in Figure 30. The addition of a small inductor and filter capacitor will reduce the output ripple well below what
could be achieved with capacitors alone. The corner frequency of 500 kHz was chosen above the 300 kHz
switching frequency to avoid loop stability issues in case the feedback is taken from the output of the LC filter.
Leaving the feedback (FB) connection point before the LC filter, the filter capacitance value can be increased
to achieve even higher ripple attenuation without affecting stability margin.
0.1 µH
SKIP COM CLK
INPUT
2.7 V to 5.4 V
CIN
4.7 µF
IN
IN
+
C1F
1 µF
+
CO = 33 µF
1 µF
OUT
OUT
TPS60111 FB
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
+
OUTPUT
5 V 150 mA
C2F
1 µF
SYNC
PGND GND
Figure 30. TPS60111 With LC Filter for Ultra Low Output Ripple Applications
related information
application reports
For more application information see:
D PowerPAD Application Report (Literature Number: SLMA002)
D TPS6010x/TPS6011x Charge Pump Application Report (Literature Number: SLVA070)
device family products
Other devices in this family are:
PART NUMBER
LITERATURE
NUMBER
TPS60100
SLVS213
Regulated 3.3-V, 200-mA Low-Noise Charge Pump DC/DC Converter
TPS60101
SLVS214
Regulated 3.3-V, 100-mA Low-Noise Charge Pump DC/DC Converter
TPS60110
SLVS215
Regulated 5-V, 300-mA Low-Noise Charge Pump DC/DC Converter
DESCRIPTION
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS60111PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60111
TPS60111PWPG4
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60111
TPS60111PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60111
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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