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TPS60140, TPS60141
SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
TPS6014x Low Power DC-DC Converter Regulated 5-V,
100-mA Charge Pump Voltage Tripler
1 Features
3 Description
•
•
•
•
•
The TPS6014x step-up, regulated charge pumps
generate a 5-V ±4% output voltage from a 1.8-V to
3.6-V input voltage range. The devices are typically
powered by two alkaline, NiCd, or NiMH battery cells
and provide an output current of minimum 100 mA
from a 2-V input. Only four external capacitors are
needed to build a complete voltage tripler charge
pump.
1
•
•
•
•
•
Regulated 5 V ±4% Output Voltage
Up to 100-mA Output Current
1.8-V to 3.6-V Input Voltage Range
65-µA Quiescent Supply Current
0.05-µA Shutdown Current, Battery Is Isolated
From Load in Shutdown
Integrated Low-Battery or Power-Good Indicator
Low-Output Voltage Ripple Over Complete Output
Current Range
Easy-to-Design With Low-EMI Power Supply
Because No Inductors Are Required
Evaluation Module Available (TPS60140EVM-144)
Available in a 6.5-mm × 4.4-mm 20-Pin HTSSOP
Package
2 Applications
•
Replacement of DC-DC Converters With Inductors
in Battery-Powered Applications:
– Two Battery Cells to 5-V Conversions
– Portable Instruments
– Miniature Equipment
– Backup-Battery Boost Converters
– Medical Instruments
– 5-V Smart Card Supplies
The devices regulate the output by using the pulseskip topology. The controller is optimized for lowest
output voltage ripple over the complete output current
range. The output peak current and therefore the
output voltage ripple are drastically reduced
compared to a conventional pulse-skip topology by
regulating the charge pump output resistance. At light
loads the maximum output resistance is limited to
assure a low quiescent current.
The TPS60140 includes a low-battery comparator
that issues a warning if the battery voltage drops
below a user-adjustable threshold voltage. The
TPS60141 features a power-good output that goes
active when the output voltage reaches 90% of its
nominal value.
Device Information(1)
PART NUMBER
TPS6014x
R2
Ci
4.7 µF
C1
2.2 µF
IN
OUT
IN
FB
LBI
LBO
C1+
C2+
C1−
ENABLE
OFF/ON
PGND
C2−
NC
GND
90
Co
10 µF
80
R3 Low
Battery
Warning
C2
2.2 µF
6.50 mm × 4.40 mm
Efficiency vs Output Current
Output
5 V, 100 mA
VI = 2.0 V
Efficiency − %
R1
TPS60140
HTSSOP (20)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Input
1.8 V to 3.6 V
PACKAGE
VI = 2.4 V
70
VI = 2.7 V
60
50
40
30
0.1
1
10
100
1000
IO − Output Current − mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS60140, TPS60141
SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
4
5
8.1
8.2
8.3
8.4
8.5
8.6
5
5
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
9.1 Overview ................................................................... 7
9.2 Functional Block Diagrams ....................................... 7
9.3 Feature Description................................................... 8
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 15
12 Layout................................................................... 15
12.1 Layout Guidelines ................................................. 15
12.2 Layout Example .................................................... 15
12.3 Power Dissipation ................................................. 15
13 Device and Documentation Support ................. 17
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
17
14 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2000) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
5 Description (continued)
The logic shutdown function disables the converter, reduces the supply current to a maximum of 1 µA and
disconnects the output from the input. Special current-control circuitry prevents excessive current from being
drawn from the battery during start-up. This DC/DC converter requires no inductors, therefore, EMI is of little
concern. The TPS6014x operates over a free-air temperature range of –40°C to 85°C. It is available in the small,
thermally enhanced 20-pin HTSSOP package (PWP).
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SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
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6 Device Comparison Table
PART NUMBER
TPS60140
TPS60141
PACKAGE
PACKAGE DESIGNATOR
20-pin thermally enhanced HTSSOP
PWP
DEVICE FEATURES
2-cell to 5 V, 100 mA
Low-battery detector
Power-good detector
7 Pin Configuration and Functions
PWP Package (TPS60140)
20 Pin-HTSSOP
Top View
1
2
3
4
5
6
7
8
9
10
GND
GND
ENABLE
FB
OUT
C1+
IN
C1−
PGND
PGND
20
19
18
17
16
15
14
13
12
11
PWP Package (TPS60141)
20 Pin-HTSSOP
Top View
GND
GND
LBI
LBO
NC
C2+
IN
C2−
PGND
PGND
1
2
3
4
5
6
7
8
9
10
GND
GND
ENABLE
FB
OUT
C1+
IN
C1−
PGND
PGND
20
19
18
17
16
15
14
13
12
11
GND
GND
NC
PG
NC
C2+
IN
C2−
PGND
PGND
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
C1+
6
—
Positive terminal of the flying capacitor C1
C1−
8
—
Negative terminal of the flying capacitor C1
C2+
15
—
Positive terminal of the flying capacitor C2
C2−
13
—
Negative terminal of the flying capacitor C2
ENABLE
3
I
ENABLE input. Connect ENABLE to IN for normal operation. When ENABLE is a logic low, the device turns off and the
supply current decreases to 0.05 µA. The output is disconnected from the input when the device is placed in shutdown.
FB
4
I
Feedback input. Connect FB to OUT as close to the load as possible to achieve best regulation. A resistive divider is on the
chip to match the output voltage to the internal reference voltage of 1.21 V.
1, 2, 19,
20
—
7,14
I
Supply input. Bypass IN to PGND with capacitor CIN. Connect both IN terminals through a short trace.
LBO/PG
17
O
Low battery detector output (TPS60140) or power good output (TPS60141). Open-drain output of the low-battery indicator or
power-good comparator. It can sink 1 mA. TI recommends a 100-kΩ to 1-MΩ pullup. Leave the terminal unconnected if the
low-battery or power-good detector function is not used.
LBI/NC
18
I
Low battery detector input (TPS60140 only). The voltage applied to this terminal is compared to the internal 1.21-V reference
voltage. Connect the terminal to ground if the low-battery comparator is not used. On the TPS60141, this terminal is not
connected to the chip and should remain unconnected.
NC
16
—
Not connected
5
O
Regulated 5-V power output. Bypass OUT to PGND with the output filter capacitor COUT.
9−12
—
Power ground. The charge-pump current flows through this terminal. Connect all PGND terminals together.
GND
IN
OUT
PGND
4
Ground. Analog ground for internal reference and control circuitry. Connect to PGND through a short trace.
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SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
Supply voltage at IN to GND and PGND
−0.3
3.6
V
Voltage at OUT, ENABLE, LBI, LBO, PG, FB to GND and PGND
−0.3
5.4
V
Voltage at C1+ to GND
−0.3
VOUT + 0.3
V
Voltage at C1– to GND
−0.3
VIN + 0.3
V
Voltage at C2+ to GND
−0.3
VOUT + 0.3
V
Voltage at C2– to GND
−0.3
VIN + 0.3
V
150
mA
150
°C
150
°C
Continuous output current
TJ
Maximum junction temperature
Tstg
Storage temperature
(1)
(2)
–55
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
V(ENABLE), V(LBI), V(LBO), and V(PG) can exceed VIN up to the maximum rated voltage without increasing the leakage current drawn by
these inputs.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
IOmax
TJ
NOM
1.8
MAX
UNIT
3.6
V
Continuous output current
100
mA
Operating junction temperature
125
°C
8.4 Thermal Information
THERMAL METRIC
(1)
TPS60140,
TPS60141
PWP (HTSSOP)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
42
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
23
°C/W
RθJB
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
20
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Product Folder Links: TPS60140 TPS60141
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8.5 Electrical Characteristics
CIN = 4.7 µF, C1 = C2 = 2.2 µF, COUT = 10 µF (1) at TC = −40°C to 85°C, VIN = 2 V, FB = VOUT and ENABLE = VIN (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V(UVLO)
Undervoltage lockout threshold
IOmax
Maximum continuous output current
VO
Output voltage
MIN
TYP
MAX
1.6
1.8
TC = 25°C
100
4.8
5.2
2 V < VIN < 3.6 V, 0 < IOUT < IOmax
4.8
5.2
Output leakage current
VIN= 2.4 V, V(ENABLE) = GND
IQ
Quiescent current (no-load input current)
VIN= 2.4 V
I(SD)
Shutdown current
VIN = 2.4 V, V(ENABLE) = GND
f(OSC)
Oscillator frequency
VIL
ENABLE input voltage low
VIN = 1.8 V
VIH
ENABLE input voltage high
VIN = 3.6 V
Ilkg(ENABLE)
ENABLE input leakage current
V(ENABLE) = GND or VIN
Output load regulation
VIN = 2.4 V, 1 mA < IOUT < IOUTmax,
TC = 25°C
Output line regulation
V
mA
1.8 V < VIN < 2 V, VOUT, Start-up = 5 V,
0 < IOUT < IOmax/2, TC = 0°C to 70°C
Ilkg(OUT)
UNIT
V
1
µA
65
90
µA
0.05
1
µA
320
450
kHz
210
0.3 × VI
0.7 × VI
V
V
0.01
0.1
µA
0.003
%/mA
2 V < VIN < 3.6 V, VOUT = 5 V:
IOUT = 75 mA, TC = 25°C
0.08
%/V
Short-circuit current limit
VIN< 2.4 V, VOUT = 0 V, TC = 25°C
100
mA
V(TRIP,LBI)
LBI trip voltage
TPS60140
VIN = 1.8 V to 2.2 V,
Hysteresis 0.8% for rising LBI voltage,
TC = 0°C to 70°C
IIN(LBI)
LBI input current
TPS60140
LBI = 1.3 V
VOUT(LBO)
LBO output voltage low (2)
TPS60140
V(LBI) = 0 V, I(LBO,SINK) = 1 mA
Ilkg(LBO)
LBO output leakage current
TPS60140
V(LBI) = 1.3 V, V(LBO) = 5 V
V(TRIP,PG)
Power-good trip voltage
TPS60141
TC = 0°C to 70°C
Vhys(PG)
Power-good trip voltage
hysteresis
TPS60141
VOUT ramping down, TC = 0°C to 70°C
VOUT(PG)
Power-good output voltage low
TPS60141
VOUT= 0 V, I(PG,SINK) = 1 mA
Ilkg(PG)
Power-good leakage current
TPS60141
VOUT = 5 V, V(PG) = 5 V
I(SC)
(1)
(2)
1.15
0.86 × VO
1.21
1.27
V
20
100
nA
0.4
v
0.01
0.1
µA
0.90 × VO
0.94 × VO
V
0.80%
0.01
0.4
V
0.1
µA
All capacitors are ceramic capacitors of the type X5R or X7R.
During start-up the LBO signal is invalid for the first 500 µs.
8.6 Typical Characteristics
330
TA = 85°C
70
I CC − Supply Current − µ A
f (OSC) − Oscillator Frequency − kHz
75
65
TA = 25°C
60
TA = −40°C
55
50
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
TA = −40°C
325
TA = 25°C
320
315
TA = 85°C
310
305
300
1.8
Figure 1. Quiescent Supply Current vs Input Voltage
6
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2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VI − Input Voltage − V
VI − Input Voltage − V
Figure 2. Oscillator Frequency vs Input Voltage
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SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
9 Detailed Description
9.1 Overview
The TPS6014x devices regulate the output voltage using an improved pulse-skip topology. In pulse-skip mode
the error amplifier disables switching of the power stages when it detects an output voltage higher than 5 V. The
oscillator halts and the controller skips switching cycles. The error amplifier reactivates the oscillator and starts
switching of the power stages again when the output voltage drops below 5 V. The output resistance of the
charge pump is controlled to improve the ripple performance. This limits the output current to the minimum that is
necessary to sustain a regulated output voltage. The benefit is that the ripple performance is nearly as good as
with a linear-regulation topology.
At light loads a conventional pulse-skip regulation mode is used, but the charge pump output resistance is held
at a high level. The pulse-skip regulation minimizes the operating current because the charge pump does not
switch continuously and hence the gate-charge losses of the MOSFETs are reduced. Additionally, all functions
except voltage reference, error amplifier, and low-battery or power-good comparator are deactivated when the
output is higher than 5 V. When switching is disabled by the error amplifier, the load is also isolated from the
input. This improved pulse-skip control topology is also referred to as active-cycle control.
9.2 Functional Block Diagrams
TPS60140
IN
C1+
Oscillator
C1
C1−
_
ENABLE
PGND
IN
Charge Pump
Power Stage
C2+
+
Control
Circuit
C2
+
−
VREF
C2−
OUT
PGND
FB
LBO
Shutdown/
Start-up Control
_
_
+
+
+
−
LBI
+
−
0.8 × VI
VREF
GND
Figure 3. TPS60140 Functional Block Diagram
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Functional Block Diagrams (continued)
TPS60141
IN
C1+
Oscillator
C1
C1−
_
ENABLE
Charge Pump
Power Stage
+
Control
Circuit
C2+
C2
+
−
VREF
PGND
IN
C2−
OUT
PGND
FB
PG
Shutdown/
Start-up Control
_
_
+
+
+
−
0.8 × VI
VREF
+
−
GND
Figure 4. TPS60141 Functional Block Diagram
9.3 Feature Description
9.3.1 Undervoltage Lockout
The TPS6014x devices have an undervoltage lockout feature that deactivates the device and places it in
shutdown mode when the input voltage falls below 1.6 V.
9.3.2 Low-Battery Detector (TPS60140 Only)
The internal low-battery comparator trips at 1.21 V ± 5% when the voltage on pin LBI ramps down. The voltage
V(TRIP) at which the low battery warning is issued can be adjusted with a resistive divider as shown in Figure 5. TI
recommends that the sum of resistors R1 and R2 to be in the 100-kΩ to 1-MΩ range. When choosing R1 and
R2, be aware of the input leakage current into the LBI terminal.
LBO is an open-drain output. TI recommends an external pullup resistor to OUT, in the 100-kΩ to 1-MΩ range.
During start-up, the LBO output signal is invalid for the first 500 µs. LBO is high impedance when the device is
disabled. If the low-battery comparator function is not used, connect LBI to ground and leave LBO unconnected.
8
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Feature Description (continued)
VO
R3
IN
VBAT
LBO
LBI
_
R1
R1 ö
æ
V(TRIP) = 1.21 V ´ ç 1 +
÷
è R2 ø
+
VREF
R2
+
−
Figure 5. Programming of the Low-Battery Comparator Trip Voltage
A 100-nF ceramic capacitor should be connected in parallel to R2 if large line transients are expected. These
voltage drops can inadvertently trigger the low-battery comparator and produce a wrong low-battery warning
signal at the LBO pin.
Formulas to calculate the resistive divider for low battery detection, with V(LBI) = 1.15 V to 1.27 V:
V
R2 = 1 MW ´ LBI
VBAT
R1 = 1 MW - R2
Formulas to calculate the minimum and maximum trip voltage:
R1(min) + R2(max)
Vtrip(min) = VLBI(min) ´
R2(max)
Vtrip(m an) = VLBI(m an) ´
(1)
(2)
(3)
R1(m an) + R2(mi x)
R2(mi x)
(4)
Table 1. Recommended Values for the Resistive Divider From the E96 Series
(±1%)
VI/V
R1/kΩ
R2/kΩ
V(TRIP)MIN/V
V(TRIP)MAX/V
1.8
357
732
1.700
1.902
1.9
365
634
1.799
2.016
2
412
634
1.883
2.112
2.1
432
590
1.975
2.219
2.2
442
536
2.08
2.338
9.3.3 Power-Good Detector (TPS60141)
The power-good (PG) terminal is an open-drain output that is pulled low when the output is out of regulation.
When the output rises to typically 90% of its nominal voltage, the power-good output is released. Power-good is
high impedance in shutdown. In normal operation an external pullup resistor must be connected between PG and
OUT. The resistor should be in the 100-kΩ to 1-MΩ range. If the power-good function is not used, the PG
terminal should remain unconnected.
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9.4 Device Functional Modes
9.4.1 Start-Up Procedure and Shutdown
During start-up (that is, when ENABLE is set from logic low to logic high), the output capacitor is charged up with
a limited current until the output voltage (VO) reaches 0.8 × VI. When the start-up comparator detects this voltage
limit, the IC begins switching. This precharging of the output capacitor ensures a short start-up time. In addition,
the inrush current into an empty output capacitor is limited because the current through the switches is limited
before the charge pump starts switching.
Driving ENABLE low places the device in shutdown mode. This disables all switches, the oscillator, and control
logic. The device typically draws 0.05 µA of supply current in this mode. Leakage current drawn from the output
is as low as 1 µA (maximum). The device exits shutdown once ENABLE is set to a high level. When the device is
in shutdown, the load is isolated from the input.
9.4.2 Short-Circuit Protection
The TPS6014x devices are also short-circuit protected. The output current is limited to typically 100 mA during a
hard short-circuit condition at the output; that is, when VOUT is GND. In this case, the condition to enter the startup mode is met, the device stops switching and controls the on-resistance of the appropriate MOSFET switches
to limit the current.
10
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS6014x charge pumps provide a regulated 5-V output from a 1.8-V to 3.6-V input voltage range. They
can deliver a maximum continuous load current of at least 100 mA at VI = 2 V minimum.
10.2 Typical Application
Input
1.8 V to 3.6 V
R1
R2
Ci
4.7 µF
C1
2.2 µF
TPS60140
IN
OUT
IN
FB
LBI
LBO
C1+
C2+
C1−
C2−
ENABLE
OFF/ON
Output
5 V, 100 mA
PGND
Co
10 µF
R3 Low
Battery
Warning
C2
2.2 µF
NC
GND
Figure 6. Typical Application Schematic
10.2.1 Design Requirements
Designed specifically for space-critical battery-powered applications, the complete charge pump circuit requires
only four external capacitors. The design guideline provides a component selection to operate the device within
the Recommended Operating Conditions.
Table 2 shows the list of components for the Application Curves.
Table 2. Components for Application Curves
REFERENCE
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
C1, C2
2.2 µF
Ceramic flying capacitors
Taiyo Yuden
EMK316BJ225KL-T
CIN
4.7 µF
Ceramic input capacitor
Taiyo Yuden
LMK316BJ475KL-T
COUT
10 µF
Ceramic output capacitor
Taiyo Yuden
JMK316BJ106ML-T
R1
357 kΩ
LBI input voltage
adjustment
E96-Series
R2
619 kΩ
LBI input voltage
adjustment
E96-Series
R3
1 MΩ
Pullup resistor for the
open-drain output LBO
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10.2.2 Detailed Design Procedure
10.2.2.1 Capacitor Selection
The capacitance values of the TPS6014x external capacitors are closely linked to the output current and output
ripple requirements. For lowest ripple, low ESR (< 0.1 Ω) capacitors should be used at the input and output of
the charge pump.
The input capacitor improves system efficiency by reducing the input impedance. It also stabilizes the input
current of the power source. The input capacitor should be chosen according to the power supply used and the
distance from the power source to the converter IC. The input capacitor selection also depends on the output
ripple requirements. CIN is recommended to be about 2-times to 4-times as large as the flying capacitors. The
lower the ESR of the input capacitor CIN, the lower is the output ripple.
The output capacitor COUT can be selected from 2× to 50× larger than the flying capacitor, depending on the
ripple tolerance. The larger COUT and the lower its ESR, the lower will be the output voltage ripple.
Generally, the flying capacitors will be the smallest. Only ceramic capacitors are recommended because of their
low ESR and because they retain their capacitance at the switching frequency. Be aware that, depending on the
material used to manufacture them, ceramic capacitors might lose their capacitance over temperature and
voltage. Ceramic capacitors of type X7R or X5R material will keep their capacitance over temperature and
voltage, whereas Z5U or Y5V-type capacitors will decrease in capacitance. Table 3 lists recommended capacitor
values.
Table 3. Recommended Capacitor Values
IOUT
(mA)
CIN
(µF)
C(xF)
(µF)
COUT
(µF)
VPPTYP
(mV)
0 − 50
4.7
2.2
4.7
40
0 − 100
4.7
2.2
10
40
0 − 100
4.7
2.2
22
18
If the measured output voltage ripple is too high for the application, improvements can be made. The first step is
to increase the capacitance at the output. If the ripple is still too high, the second step would be to increase the
capacitance at the input. For lower output currents, lower value flying capacitors can be used. Table 3 and
Table 4 lists the manufacturers of recommended capacitors.
Table 4. Recommended Capacitors (1)
MANUFACTURER
PART NUMBER
CAPACITANCE
CASE SIZE
TYPE
Taiyo Yuden
LMK212BJ105KG−T
EMK316BJ225KL−T
LMK212BJ225MG−T
LMK316BJ475KL−T
JMK316BJ106ML–T
LMK325BJ106MN−T
LMK432226MM−T
1 µF
2.2 µF
2.2 µF
4.7 µF
10 µF
10 µF
22 µF
805
1206
805
1206
1206
1210
1812
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
AVX
0805ZC105KAT2A
1206ZC225KAT2A
1 µF
2.2 µF
805
1206
Ceramic
Ceramic
(1)
Note: Case code compatibility with EIA 535BAAC and CECC30801 molded chips.
Table 5. Recommended Capacitor Manufacturers
12
MANUFACTURER
CAPACITOR TYPE
INTERNET SITE
Taiyo Yuden
X7R/X5R ceramic
http://www.t−yuden.com/
AVX
X7R/X5R ceramic
http://www.avxcorp.com/
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10.2.3 Application Curves
90
90
IO = 50 mA
80
80
VI = 2.4 V
70
Efficiency − %
Efficiency − %
VI = 2.0 V
VI = 2.7 V
60
70
60
50
50
40
30
0.1
1
10
100
40
1.8
1000
2.0
2.2
IO − Output Current − mA
5.10
5.10
5.05
5.05
5.00
VI = 2.7 V
VI = 3.6 V
2.8
3.0
3.2
3.4
3.6
4.95
VI = 1.8 V
4.90
IO = 1 mA
5.00
IO = 50 mA
4.95
IO = 100 mA
4.90
4.85
4.85
4.80
0.1
1
10
100
4.80
1.8
1000
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
IO − Output Current − mA
VI − Input Voltage − V
Figure 9. Output Voltage vs Output Current
Figure 10. Output Voltage vs Input Voltage
5.25
5.25
VI = 2.4 V
IO = 1 mA
5.20
VI = 2.4 V
IO = 10 mA
5.20
5.15
5.15
VO − Output Voltage − V
VO − Output Voltage − V
2.6
Figure 8. Efficiency vs Input Voltage
VO − Output Voltage − V
VO − Output Voltage − V
Figure 7. Efficiency vs Output Current
VI = 2.4 V
2.4
VI − Input Voltage − V
5.10
5.10
5.05
5.05
5.00
5.00
4.95
4.95
4.90
4.90
4.85
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 11. Output Voltage Ripple
4.85
0
5
10
15
20 25 30
t − Time − µs
35
40
45
50
Figure 12. Output Voltage Ripple
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5.13
60
5.09
5.07
5.05
5.03
5.01
4.99
40
30
IO = 10 mA
20
IO = 1 mA
10
4.97
0
2
4
6
8
10 12
t − Time − µs
14
16
18
0
1.8
20
VO − Output Voltage − V
40
30
I O − Output Current − mA
Vpp − Output Voltage Ripple Amplitude − mV
VI = 2.4 V
50
20
10
0
20
30
40
50
60
70
80
90 100
IO − Output Current − mA
2.8
3.0
3.2
3.4
3.6
5.07
5.05
5.03
260
0
0
2
4
6
8
10 12
t − Time − ms
14
16
18
20
Figure 16. Load Transient Response
IO = 50 mA
5
6
VI = 2.4 V
IO = 100 mA
5
Out
VO − Output Voltage − V
VO − Output Voltage − V
2.6
6
5.07
5.05
5.03
V I − Input Voltage − V
2.4
VI = 2.4 V
Figure 15. Output Voltage Ripple Amplitude vs
Output Current
4
4
3
3
Enable
2
2
1
1
0
0
3.0
2.5
2.0
0
2
4
6
8
10 12
t − Time − ms
14
16
18
20
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−1
−0.1
−1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
t − Time − ms
Figure 17. Line Transient Response
14
2.2
Figure 14. Output Voltage Ripple Amplitude vs
Input Voltage
60
10
2.0
VI − Input Voltage − V
Figure 13. Output Voltage Ripple
0
IO = 100 mA
50
Enable Voltage − V
VO − Output Voltage − V
5.11
Vpp − Output Voltage Ripple Amplitude − mV
VI = 2.4 V
IO = 100 mA
Figure 18. Output Voltage vs Time (Start-Up Timing)
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11 Power Supply Recommendations
The TPS6014x devices have no special requirements for its input power supply. The input power supply's output
current must be rated according to the supply voltage, output voltage and output current of the TPS6014x.
12 Layout
12.1 Layout Guidelines
Careful board layout is necessary due to the high transient currents and switching frequency of the converter. All
capacitors should be soldered in close proximity to the IC. Connect ground and power ground terminals through
a short, low-impedance trace. A PCB layout proposal for a two-layer board is given in Figure 19. The bottom
layer of the board carries only ground potential for best performance. The layout also provides improved thermal
performance as the exposed lead frame of the PowerPAD package is soldered to the PCB.
An evaluation module for the TPS60140 is available and can be ordered under product code
TPS60140EVM−144. The EVM uses the layout shown in Figure 19.
12.2 Layout Example
NOTE: Actual size is 15 mm x 25 mm.
Figure 19. Recommended Component Placement and Board Layout
Table 6. Component Identification
IC1
TPS6014x
C1, C2
Flying capacitors
C3, C6
Input capacitors
C4, C5
Output capacitors
C7
Stabilization capacitor for LBI
R1, R2
Resistive divider for LBI
R3
Pullup resistor for LBO
The best performance of the converter is achieved with additional bypass capacitors C5 and C6 at the input and
output. Capacitor C7 should be included if the large line transients are expected. The capacitors are not required.
They can be omitted in most applications.
12.3 Power Dissipation
The power dissipated in the TPS6014x depends mainly on input voltage and output current and is described by
Equation 5:
P(DISS) = IO ´ (3 ´ VI - VO )
(5)
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Power Dissipation (continued)
By observation of Equation 5, it can be seen that the power dissipation is worse for the highest input voltage VI
and the highest output current IOUT. For an input voltage of 3.6 V and an output current of 100 mA, the calculated
power dissipation P(DISS) is 580 mW. This is also the point where the charge pump operates with its lowest
efficiency, which is only 45%, and hence with the highest power losses.
P(DISS) must be less than that allowed by the package rating. The thermal resistance junction to ambient of the
thermally enhanced TSSOP is 178°C/W for an unsoldered package. The thermal resistance junction to case,
with the exposed thermal pad soldered to an infinitive heat sink, is 3.5°C/W.
With the recommended maximum junction temperature of 125°C and an assumed maximum ambient operating
temperature of 85°C, the maximum allowed thermal resistance junction to ambient of the system can be
calculated using Equation 6.
T max - TA 125°C - 85°C
=
= 69°C / W
RqJA max = J
P(DISS) max
580 mW
(6)
Using a board layout as described in the application information section, RθJA is typically 56°C/W for an
unsoldered PowerPAD™ and 41°C/W for a soldered PowerPAD.
For more information, refer to the PowerPAD application report, PowerPAD™ Thermally Enhanced Package
(SLMA002).
16
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SLVS273A – FEBRUARY 2000 – REVISED NOVEMBER 2015
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package, SLMA002.
• TPS6010x/TPS6011x Charge Pump, SLVA070.
13.3 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS60140
Click here
Click here
Click here
Click here
Click here
TPS60141
Click here
Click here
Click here
Click here
Click here
13.4 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS60140PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60140
TPS60140PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60140
TPS60140PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60140
TPS60141PWP
ACTIVE
HTSSOP
PWP
20
70
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60141
TPS60141PWPR
ACTIVE
HTSSOP
PWP
20
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS60141
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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