SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
D Compact Converter Solution in UltraSmall
features
D Regulated 3.3-V Output Voltage With up to
D
D
D
D
D
D
100-mA Output Current From a 1.8-V to
3.6-V Input Voltage
Less Than 5-mV(PP) Output Voltage Ripple
Achieved With Push-Pull Topology
Integrated Low-Battery and Power-Good
Detector
Switching Frequency Can Be Synchronized
to External Clock Signal
Extends Battery Usage With up to 90%
Efficiency and 35-µA Quiescent Supply
Current
Easy-to-Design, Low Cost, Low EMI Power
Supply Since No Inductors Are Used
0.05-µA Shutdown Current, Battery is
Isolated From Load in Shutdown Mode
D
10-pin MSOP With Only Four External
Capacitors Required
Evaluation Module Available
(TPS60200EVM-145)
applications
D Replaces DC/DC Converters With Inductors
in Battery Powered Applications Like:
− Two Battery Cells to 3.3-V Conversion
− MP3 Portable Audio Players
− Battery-Powered Microprocessor
Systems
− Backup-Battery Boost Converters
− PDA’s, Organizers, and Cordless Phones
− Handheld Instrumentation
− Glucose Meters and Other Medical
Instruments
·
description
The TPS6020x step-up, regulated charge pumps generate a 3.3-V ±4% output voltage from a 1.8-V to 3.6-V
input voltage. The devices are typically powered by two Alkaline, NiCd, or NiMH battery cells and operate down
to a minimum supply voltage of 1.6 V. Continuous output current is a minimum of 100 mA from a 2-V input. Only
four external capacitors are needed to build a complete low-ripple dc/dc converter. The push-pull operating
mode of two single-ended charge pumps assures the low output voltage ripple, as current is continuously
transferred to the output.
TPS60204
7
IN
OUT
5
R1
Ci
2.2 µF
1
LBO
R2
4
C1
1 µF
3
9
OFF/ON
C1+
C2+
C1−
C2−
EN
PEAK OUTPUT CURRENT
vs
INPUT VOLTAGE
Co
2.2 µF
R3
LBI
TPS60204
OUTPUT
3.3 V, 100 mA
350
10
Low Battery
Warning
6
8
C2
1 µF
GND
2
Figure 1. Typical Application Circuit
With Low-Battery Warning
I O − Peak Output Current − mA
INPUT
1.6 V to 3.6 V
300
250
200
150
100
50
0
1.6
2.0
2.4
2.8
3.2
VI − Input Voltage − V
3.6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
!"#$%&#! ' ()$$*!& %' #" +),-(%&#! .%&*
$#.)(&' (#!"#$ '+*("(%&#!' +*$ &/* &*$' #" *0%' !'&$)*!&'
'&%!.%$. 1%$$%!&2 $#.)(&#! +$#(*''!3 .#*' !#& !*(*''%$-2 !(-).*
&*'&!3 #" %-- +%$%*&*$'
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
description (continued)
The devices operate in the newly developed LinSkip mode. In this operating mode, the device switches
seamlessly from the power saving pulse-skip mode at light loads to the low-noise constant-frequency,
linear-regulation mode once the output current exceeds the LinSkip threshold of about 7 mA. Even in pulse-skip
mode, the output ripple is maintained at a very low level because the output resistance of the charge pump is
still regulated.
Three operating modes can be programmed using the EN pin. EN = low disables the device, shuts down all
internal circuits, and disconnects the output from the input. EN = high enables the device and programs it to run
from the internal oscillator. The devices operate synchronized to an external clock signal if EN is clocked; thus,
switching harmonics can be controlled and minimized. The devices include a low-battery detector that issues a
warning if the battery voltage drops below a user-defined threshold voltage, or a power-good detector that goes
active when the output voltage reaches about 90% of its nominal value.
Device options with either a low-battery or power good detector are available. This dc/dc converter requires no
inductors, therefore, EMI of the system is reduced to a minimum. It is available in the small 10-pin MSOP
package (DGS).
DGS PACKAGES
TPS60204
LBI
GND
C1−
C1+
OUT
TPS60205
1
10
2
9
3
8
4
7
5
6
LBO
EN
C2−
IN
C2+
GND
GND
C1−
C1+
OUT
1
10
2
9
3
8
4
7
5
6
PG
EN
C2−
IN
C2+
ACTUAL SIZE
3,05 mm x 4,98 mm
AVAILABLE OPTIONS
TA
−40°C to 85°C
MARKING
DGS
PACKAGE
OUTPUT
CURRENT
(mA)
OUTPUT
VOLTAGE
(V)
TPS60204DGS
AFB
100
3.3
Low-battery detector
TPS60205DGS
AFC
100
3.3
Power-good detector
PART NUMBER†
DEVICE FEATURES
† The DGS package is available taped and reeled. Add R suffix to device type (e.g., TPS60204DGSR) to order
quantities of 2500 devices per reel.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
functional block diagrams
TPS60204 with low-battery detector
Charge Pump 1
0°
IN
Oscillator
180°
C1+
C1
C1−
EN
Charge Pump 2
Control
Circuit
C2+
_
C2−
C2
+
VREF
Shutdown/
Start-Up
Control
+
−
OUT
_
_
+
LBI
+
+
−
0.8 x VI
VREF
GND
+
−
LBO
TPS60205 with power-good detector
Charge Pump 1
0°
Oscillator
180°
IN
C1+
C1
C1−
EN
Charge Pump 2
Control
Circuit
C2+
_
C2−
C2
+
VREF
Shutdown/
Start-Up
Control
+
−
OUT
_
_
+
+
+
−
0.8 x VI
VREF
GND
POST OFFICE BOX 655303
+
−
PG
• DALLAS, TEXAS 75265
3
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
C1+
4
Positive terminal of the flying capacitor C1
C1−
3
Negative terminal of the flying capacitor C1
C2+
6
Positive terminal of the flying capacitor C2
C2−
8
Negative terminal of the flying capacitor C2
Device-enable input. Three operating modes can be programmed with the EN pin.
− EN = Low disables the device. Output and input are isolated in the shutdown.
EN
9
I
− EN = High lets the device run from the internal oscillator.
− If an external clock signal is applied to the EN pin, the device is in syncmode and runs synchronized at the
frequency of the external clock signal.
GND
2
IN
7
I
Ground
Supply input. Bypass IN to GND with a capacitor of the same size as Co.
LBI/GND
1
I
Low-battery detector input for the TPS60204. A low-battery warning is generated at the LBO pin when the voltage
on LBI drops below the threshold of 1.18 V. Connect LBI to GND if the low-battery detector function is not used. For
the TPS60205, this pin has to be connected to ground (GND pin).
LBO/PG
10
O
OUT
5
O
Open-drain low-battery detector output for the TPS60204. This pin is pulled low if the voltage on LBI drops below
the threshold of 1.18 V. A pullup resistor should be connected between LBO and OUT or any other logic supply rail
that is lower than 3.6 V.
Open-drain power-good detector output for the TPS60205. As soon as the voltage on OUT reaches about 90% of
it is nominal value this pin goes active high. A pullup resistor should be connected between PG and OUT or any
other logic supply rail that is lower than 3.6 V.
Regulated 3.3-V power output. Bypass OUT to GND with the output filter capacitor Co.
detailed description
operating principle
The TPS6020x charge pumps provide a regulated 3.3-V output from a 1.8-V to 3.6-V input. They deliver up to
100-mA load current while maintaining the output at 3.3 V ±4%. Designed specifically for space critical battery
powered applications, the complete converter requires only four external capacitors. The device is using the
push-pull topology to achieve lowest output voltage ripple. The converter is also optimized for smallest board
space. It makes use of small sized capacitors, with the highest output current rating per output capacitance and
package size.
The TPS6020x circuits consist of an oscillator, a 1.18-V voltage reference, an internal resistive feedback circuit,
an error amplifier, two charge pump power stages with high current MOSFET switches, a shutdown/start-up
circuit, and a control circuit (see functional block diagrams).
push-pull operating mode
The two single-ended charge pump power stages operate in the so-called push-pull operating mode, i.e., they
operate with a 180°C phase shift. Each single-ended charge pump transfers charge into its transfer capacitor
(C1 or C2) in one half of the period. During the other half of the period (transfer phase), the transfer capacitor
is placed in series with the input to transfer its charge to Co. While one single-ended charge pump is in the charge
phase, the other one is in the transfer phase. This operation assures an almost constant output current which
ensures a low output ripple.
If the clock were to run continuously, this process would eventually generate an output voltage equal to two times
the input voltage (hence the name voltage doubler). In order to provide a regulated fixed output voltage of 3.3 V,
the TPS6020x devices use either pulse-skip or constant-frequency linear-regulation control mode. The mode
is automatically selected based on the output current. If the load current is below the LinSkip current threshold,
it switches into the power-saving pulse-skip mode to boost efficiency at low output power.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
detailed description (continued)
constant-frequency mode
When the output current is higher then the LinSkip current threshold, the charge pump runs continuously at the
switching frequency f(OSC). The control circuit, fed from the error amplifier, controls the charge on C1 and C2
by controlling the gates and hence the rDS(ON) of the integrated MOSFETs. When the output voltage decreases,
the gate drive increases, resulting in a larger voltage across C1 and C2. This regulation scheme minimizes
output ripple. Since the device switches continuously, the output signal contains well-defined frequency
components, and the circuit requires smaller external capacitors for a given output ripple. However,
constant-frequency mode, due to higher operating current, is less efficient at light loads. For this reason, the
device switches seamlessly into the pulse-skip mode when the output current drops below the LinSkip current
threshold.
pulse-skip mode
The regulator enters the pulse-skip mode when the output current is lower than the LinSkip current threshold
of 7 mA. In the pulse-skip mode, the error amplifier disables switching of the power stages when it detects an
output voltage higher than 3.3 V. The controller skips switching cycles until the output voltage drops below 3.3 V.
Then the error amplifier reactivates the oscillator and switching of the power stages starts again. A 30-mV output
voltage offset is introduced in this mode.
The pulse-skip regulation mode minimizes operating current because it does not switch continuously and
deactivates all functions except the voltage reference and error amplifier when the output is higher than 3.3 V.
Even in pulse-skip mode the rDS(ON) of the MOSFETs is controlled. This way the energy per switching cycle that
is transferred by the charge pump from the input to the output is limited to the minimum that is necessary to
sustain a regulated output voltage, with the benefit that the output ripple is kept to a minimum. When switching
is disabled from the error amplifier, the load is also isolated from the input.
start up and shutdown
During start-up, i.e. when EN is set from logic low to logic high, the output capacitor is directly connected to IN
and charged up with a limited current until the output voltage VO reaches 0.8 × VI. When the start-up comparator
detects this limit, the converter begins switching. This precharging of the output capacitor guarantees a short
start-up time. In addition, the inrush current into an empty output capacitor is limited. The converter can start
into a full load, which is defined by a 33-Ω or 66-Ω resistor, respectively.
Driving EN low disables the converter. This disables all internal circuits and reduces the supply current to only
0.05 µA. The device exits shutdown once EN is set high. When the device is disabled, the load is isolated from
the input. This is an important feature in battery operated products because it extends the products shelf life.
synchronization to an external clock signal
The operating frequency of the charge pump is limited to 400 kHz in order to avoid interference in the sensitive
455-kHz IF band. The device can either run from the integrated oscillator, or an external clock signal can be used
to drive the charge pump. The maximum frequency of the external clock signal is 800 kHz. The switching
frequency used internally to drive the charge pump power stages is half of the external clock frequency. The
external clock signal is applied to the EN pin. The device will switch off if the signal on EN is hold low for more
than 10 µs.
When the load current drops below the LinSkip current threshold, the devices will enter the pulse-skip mode
but stay synchronized to the external clock signal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
detailed description (continued)
low-battery detector (TPS60204)
The low-battery comparator trips at 1.18 V ±4% when the voltage on pin LBI ramps down. The voltage V(TRIP)
at which the low-battery warning is issued can be adjusted with a resistive divider as shown in Figure 2. The
sum of resistors R1 and R2 is recommended to be in the 100-kΩ to 1-MΩ range. When choosing R1 and R2,
be aware of the input leakage current into the LBI pin.
LBO is an open drain output. An external pullup resistor to OUT, or any other voltage rail in the appropriate range,
in the 100-kΩ to 1-MΩ range is recommended. During start-up, the LBO output signal is invalid for the first
500 µs. LBO is high impedance when the device is disabled. If the low-battery comparator function is not used,
connect LBI to ground and leave LBO unconnected. The low-battery detector is disabled when the device is
switched off.
VO
IN
VBAT
R3
R1
LBO
+
VREF
V
LBI
_
(TRIP)
ǒ
Ǔ
+ 1.18 V 1 ) R1
R2
R2
+
−
Figure 2. Programming of the Low-Battery Comparator Trip Voltage
A 100-nF ceramic capacitor should be connected in parallel to R2 if large line transients are expected. These
voltage drops can inadvertently trigger the low-battery comparator and produce a wrong low-battery warning
signal at the LBO pin.
Formulas to calculate the resistive divider for low-battery detection, with VLBI = 1.13 V to 1.23 V and the sum
of resistors R1 and R2 equal 1 MΩ:
V
LBI
(1)
Bat
R1 + 1 MW * R2
(2)
R2 + 1 MW
V
Formulas to calculate the minimum and maximum battery voltage:
R1
Bat(min)
+V
Bat(max)
+V
V
LBI(min)
(min)
R2
R1
V
6
LBI(max)
) R2
(max)
(3)
(max)
(max)
R2
) R2
(min)
(4)
(min)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
detailed description (continued)
Table 1. Recommended Values for the Resistive Divider From the E96 Series (±1%)
VIN/V
1.6
R1/kΩ
R2/kΩ
750
VTRIP(MIN)/V
1.524
VTRIP(MAX)/V
1.677
267
1.7
301
1.8
340
681
1.620
1.785
649
1.710
1.887
1.9
2.0
374
619
1.799
1.988
402
576
1.903
2.106
power-good detector (TPS60205)
The power-good output is an open-drain output that pulls low when the output is out of regulation. When the
output rises to within 90% of its nominal voltage, the power-good output is released. Power-good is high
impedance in shutdown. In normal operation, an external pullup resistor must be connected between PG and
OUT, or any other voltage rail in the appropriate range. The resistor should be in the 100-kΩ to 1-MΩ range.
If the PG output is not used, it should remain unconnected.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Voltage range:
IN, OUT, EN, LBI, LBO, PG to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 3.6 V
C1+, C2+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VO + 0.3 V)
C1−, C2− to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VI + 0.3 V)
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table
Continuous output current TPS60204, TPS60205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DGS
424 mW
DERATING FACTOR
ABOVE TA = 25°C
3.4 mW/_C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
187 mW
136 mW
The thermal resistance junction to ambient of the DGS package is RTH−JA = 294°C/W.
recommended operating conditions
MIN
Input voltage range, VI
NOM
1.6
Input capacitor, Ci
Flying capacitors, C1, C2
Output capacitor, Co
MAX
3.6
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
2.2
µF
1
µF
µF
2.2
Operating junction temperature, TJ
UNIT
125
°C
7
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
electrical characteristics at Ci = 2.2 µF, C1 = C2 = 1 µF, CO = 2.2 µF, TA = −40°C to 85°C, VI = 2.4 V,
EN = VI (unless otherwise noted)
IO(MAX)
PARAMETER
TEST CONDITIONS
MIN
Maximum continuous output current
VI = 2 V
1.6 V < VI < 1.8 V, 0 < IO < 0.25 × IO(MAX)
100
1.8 V < VI < 2 V, 0 < IO < 0.5 × IO(MAX)
3.17
3.43
2 V < VI < 3.3 V,
0 < IO < IO(MAX)
3.17
3.43
3.17
Output voltage
VPP
I(Q)
Output voltage ripple
Quiescent current (no-load input current)
0 < IO < IO(MAX)
IO = IO(MAX)
IO = 0 mA, VI = 1.8 V to 3.6 V
I(SD)
f(OSC)
Shutdown supply current
EN = 0 V
Internal switching frequency
f(SYNC)
External clock signal frequency
External clock signal duty cycle
30%
EN input low voltage
EN input high voltage
VI = 1.6 V to 3.6 V
VI = 1.6 V to 3.6 V
Ilkg(EN)
EN input leakage current
EN = 0 V or VI
Output capacitor auto discharge time
EN is set from VI to GND,
Time until VO < 0.5 V
EN = 0 V,
LinSkip threshold
Output line regulation
Short circuit current
V
3.47
5
mVPP
35
70
0.05
1
200
300
400
400
600
800
µA
kHz
70%
V
0.7 × VI
0.01
VI = 2.4 V,
µA
0.1
0.6
ms
5
µA
3
VI = 2.2 V
10 mA < IO < IO(MAX); TA = 25°C
2 V < VI < 3.3 V, IO = 0.5 x IO(MAX),
TA = 25°C
Output load regulation
I(SC)
mA
TA = −40 to 85°C
TA ≤ 65°C
EN = 0 V,
UNIT
0.3 × VI
VIL
VIH
Output leakage current in shutdown
MAX
3
VO
3.3 V < VI < 3.6 V,
TYP
7
mA
0.01
%/mA
0.6
%/V
60
mA
VO = 0 V
electrical characteristics for low-battery comparator of devices TPS60204 at TA = −40°C to 85°C,
VI = 2.4 V and EN = VI (unless otherwise noted)
PARAMETER
V(LBI)
TEST CONDITIONS
LBI trip voltage
LBI trip voltage hysteresis
II(LBI)
VO(LBO)
MIN
VI = 1.6 V to 2.2 V,
Tc = 0°C to 70°C
For rising voltage at LBI
LBI input current
V(LBI) = 1.3 V
V(LBI) = 0 V,
LBO output voltage low
TYP
1.13
1.18
MAX
1.23
10
Ilkg(LBO) LBO leakage current
V(LBI) = 1.3 V,
NOTE: During start-up of the converter the LBO output signal is invalid for the first 500 µs.
0.01
V
mV
2
I(LBO) = 1 mA
V(LBO) = 3.3 V
UNIT
50
nA
0.4
V
0.1
µA
electrical characteristics for power-good comparator of devices TPS60205 at TA = −40°C to 85°C,
VI = 2.4 V and EN = VI (unless otherwise noted)
PARAMETER
V(PG)
Vhys(PG)
Power-good trip voltage
VO(PG)
Ilkg(PG)
Power-good output voltage Low
TEST CONDITIONS
Power-good trip voltage hysteresis
Power-good leakage current
Tc = 0°C to 70°C
VO decreasing, Tc = 0°C to 70°C
VO = 0 V,
VO = 3.3 V,
I(PG) = 1 mA
V(PG) = 3.3 V
NOTE: During start-up of the converter the PG output signal is invalid for the first 500 µs.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
0.87 × VO
0.91 × VO
0.95 × VO
V
0.4
V
0.1
µA
1%
0.01
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURES
η
Efficiency
IQ
Quiescent supply current
VO
Output voltage
VO
Output voltage ripple
vs Output current (TPS60204, TPS60205)
3
vs Input voltage
4
vs Input voltage
5
vs Output current
6
vs Input voltage
7
vs Time
8, 9, 10
Start-up timing
11
Load transient response
12, 13
IO
Peak output current
vs Input voltage
NOTE: All typical characteristics were measured using the typical application circuit of Figure 14 (unless otherwise noted).
14
TPS60204, TPS60205
EFFICIENCY
vs
INPUT VOLTAGE
100
100
90
90
80
80
70
70
Efficiency − %
Efficiency − %
EFFICIENCY
vs
OUTPUT CURRENT
60
VI = 1.8 V
50
VI = 2.4 V
40
VI = 2.7 V
30
60
50
IO = 50 mA
40
30
20
20
10
10
0
0.1
1
10
100
1000
0
1.6
2.0
IO − Output Current − mA
Figure 3
2.4
2.8
VI − Input Voltage − V
3.2
3.6
Figure 4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
TYPICAL CHARACTERISTICS
QUIESCENT SUPPLY CURRENT
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
40
IO = 0 mA
3.4
36
VI = 3.6 V
34
VO − Output Voltage − V
I (Q) − Quiescent Supply Current − µ A
38
3.5
32
30
28
26
24
3.3
3.2
VI = 1.8 V
VI = 2.7 V
3.1
VI = 2.4 V
3.0
22
20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
2.9
1
10
VI − Input Voltage − V
Figure 5
OUTPUT VOLTAGE RIPPLE
vs
TIME
3.38
3.4
VO − Output Voltage Ripple − V
VO − Output Voltage − V
VI = 2.4 V
IO = 1 mA
3.36
3.3
1 mA
3.2
3.1
100 mA
50 mA
3.0
2.9
2.8
3.34
3.32
3.30
3.28
3.26
3.24
3.22
2.0
2.4
2.8
3.2
3.6
0
5
VI − Input Voltage − V
10
15
20 25 30
t − Time − µs
Figure 8
Figure 7
10
1000
Figure 6
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
2.7
1.6
100
IO − Output Current − mA
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
40
45
50
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RIPPLE
vs
TIME
OUTPUT VOLTAGE RIPPLE
vs
TIME
3.38
3.38
VI = 2.4 V
IO = 10 mA
VI = 2.4 V
IO = 100 mA
3.36
VO − Output Voltage Ripple − V
VO − Output Voltage Ripple − V
3.36
3.34
3.32
3.30
3.28
3.26
3.34
3.32
3.30
3.28
3.26
3.24
3.24
3.22
3.22
0
1
2
3
4
5
6
t − Time − µs
7
8
9
0
10
1
2
START-UP TIMING
1000
II
2
800
1.5
600
1
400
EN
0.5
200
0
0
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
VO − Output Voltage − V
1200
I I − Input Current − mA
VO − Output Voltage − V
VI = 2.4 V
I O− Output Current − mA
1400
2.5
7
8
9
10
LOAD TRANSIENT RESPONSE
3.5
VO
4
5
6
t − Time − µs
Figure 10
Figure 9
3
3
VI = 2.4 V
3.30
3.28
3.26
3.24
100 mA
10 mA
0
50
100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 12
Figure 11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
TYPICAL CHARACTERISTICS
PEAK OUTPUT CURRENT
vs
INPUT VOLTAGE
350
IO = 50 mA
300
I O − Peak Output Current − mA
VO − Output Voltage − V
LINE TRANSIENT RESPONSE
3.32
3.30
VI − Input Voltage − V
3.28
3.26
2.8 V
250
200
150
100
50
2.2 V
0
1
2
3
4
5
6
7
8
9
10
0
1.6
t − Time − ms
Figure 13
12
2.0
2.4
2.8
3.2
VI − Input Voltage − V
Figure 14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3.6
SLVS354A − FEBRUARY 2001 − REVISED SEPTEMBER 2001
APPLICATION INFORMATION
capacitor selection
The TPS6020x devices require only four external capacitors to achieve a very low output voltage ripple. The
capacitor values are closely linked to the required output current. Low ESR (