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TPS61021A
SLVSDM0 – JUNE 2016
TPS61021A 3-A Boost Converter with 0.5-V Ultra Low Input Voltage
1 Features
3 Description
•
•
•
•
The TPS61021A provides a power supply solution for
portable or smart devices powered by alkaline, NiMH,
Li-Mn, or Li-ion batteries. The TPS61021A is capable
of outputting 3.3-V voltage and 1.5-A current from a
battery discharged to as low as 1.8 V. Capable of
operating with 0.5-V input voltage enables the
TPS61021A to extend the battery run time.
1
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 0.5 V to 4.4 V
0.9 V Minimum Input Voltage for Startup
Output Voltage Setting Range: 1.8 V to 4.0 V
91% Efficiency at VIN = 2.4 V, VOUT = 3.3 V and
IOUT = 1.5 A
2.0-MHz Switching Frequency
IOUT > 1.5 A at VOUT = 3.3 V when VIN > 1.8 V
17-µA Typical Quiescent Current
±2.5% Reference Voltage Accuracy over -40°C to
125°C
PFM Operation Mode at Light Load
True Disconnection Between Input and Output
During Shutdown
Output Over Voltage Protection
Output Short Circuit Protection
Thermal Shutdown Protection
2-mm x 2-mm WSON Package
The TPS61021A offers a very small solution size due
to low count of external components. It allows the use
of small inductors and output capacitors with the 2MHz switching frequency.
The TPS61021A is available in 2.0-mm x 2.0-mm
WSON package.
2 Applications
•
•
•
•
•
The TPS61021A operates at 2-MHz switching
frequency at heavy load and enters power-save mode
at light load to maintain high efficiency over the entire
load current range. The device only consumes a 17μA quiescent current from VOUT in light load condition.
During shutdown, the load is completely disconnected
from the input. In addition, The TPS61021A provides
4.35-V output overvoltage protection, output short
circuit protection, and thermal shutdown protection.
Battery Powered IoT Devices
Gaming Control
Thermostat
Portable Medical Equipment
Supercap Backup System
Device Information(1)
PART NUMBER
TPS61021A
PACKAGE
WSON (8)
BODY SIZE (NOM)
2.00-mm x 2.00-mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Circuit
L1
VIN
C1
VIN
SW
VOUT
VOUT
PGND
R1
C3
C2
TPS61021A FB
ON
OFF
R2
EN
AGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61021A
SLVSDM0 – JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
9 Power Supply Recommendations...................... 17
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
10.3 Thermal Considerations ........................................ 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4
11.5
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Application and Implementation ........................ 12
Overview ................................................................... 8
Functional Block Diagram ......................................... 8
Feature Description................................................... 8
Device Functional Modes........................................ 10
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
12.1 Package Option Addendum .................................. 20
4 Revision History
2
DATE
REVISION
NOTES
June 2016
*
Initial release.
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5 Pin Configuration and Functions
DSG Package
8-Pin WSON with Thermal Pad
Top View
AGND
VIN
FB
SW
PGND
VOUT
SW
VOUT
EN
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
1
I
Signal ground of the IC
FB
2
I
Voltage feedback of adjustable output voltage
3,4
PWR
EN
5
I
SW
6,7
PWR
VIN
8
I
PGND
9
PWR
VOUT
Boost converter output
Enable logic input. Logic high voltage enables the device. Logic low voltage disables the
device and turns it into shutdown mode.
The switch pin of the converter. It is connected to the drains of the internal power MOSFETs.
IC power supply input
Power ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
DC
–0.3
3.6
V
DC
–0.3
4.6
V
10% duty cycle
–0.3
4.8
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
EN, FB
Voltage range at terminals
(1)
(2)
(2)
VIN, SW, VOUT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
4.4
UNIT
VIN
Input voltage range
0.5
VOUT
Output voltage setting range
1.8
L
Effective inductance range
0.2
0.47
CIN
Effective input capacitance range
1.0
4.7
COUT
Effective output capacitance range
IOUT ≤ 0.3 A
3.0
10
200
µF
IOUT > 0.3 A
10
20
200
µF
TJ
Operating junction temperature
125
°C
–40
V
4.0
V
1.3
µH
µF
6.4 Thermal Information
TPS61021A
THERMAL METRIC (1)
DSG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
71.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
95.2
°C/W
RθJB
Junction-to-board thermal resistance
41.6
°C/W
ψJT
Junction-to-top characterization parameter
3.1
°C/W
ψJB
Junction-to-board characterization parameter
42.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
13.0
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ = –40°C to 125°C, VIN = 2.4 V and VOUT = 3.3 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VIN
VIN_UVLO
Input voltage range
Under-voltage lockout threshold
VIN falling
0.28
4.4
V
0.8
0.9
V
0.4
0.5
V
3.0
µA
Quiescent current into VIN pin
IC enabled, No load, No switching
VIN = 1.8 V to 3.6 V, VFB = VREF +
0.1 V, TJ up to 85°C
Quiescent current into VOUT pin
IC enabled, No load, No switching
VOUT = 1.8 V to 4.0 V, VFB = VREF +
0.1 V, TJ up to 85°C
17
30
µA
Shutdown current into VIN and SW
pin
IC disabled, VIN = 1.8 V to 3.6 V, TJ
up to 85°C
0.5
3.0
µA
4.0
V
795
815
mV
IQ
ISD
0.5
VIN rising
OUTPUT
VOUT
Output voltage setting range
1.8
PWM mode
VREF
Reference voltage at the FB pin
VOVP
Output over-voltage protection
threshold
VOVP_HYS
Over-voltage protection hysteresis
IFB_LKG
Leakage current at FB pin
ISW_LKG
Leakage current into SW pin
IC disabled, TJ up to 85°C
IVOUT_LKG
Leakage current into VOUT pin
IC disabled, VOUT = 4.0 V, TJ up to
85°C
775
PFM mode
VOUT rising
801
4.15
4.35
mV
4.60
V
20
nA
3.0
µA
2
µA
0.1
1
V
POWER SWITCH
High-side MOSFET on resistance
VOUT = 3.3 V
51
mΩ
Low-side MOSFET on resistance
VOUT = 3.3 V
58
mΩ
fSW
Switching frequency
VIN = 2.4 V, VOUT = 3.3 V, PWM
mode
2.0
MHZ
tOFF_min
Minimum off time
ILIM_SW
Valley current limit
RDS(on)
80
VIN = 2.4 V, VOUT = 3.3 V
3.0
120
4.3
ns
A
LOGIC INTERFACE
VEN_H
EN Logic high threshold
VEN_L
EN Logic Low threshold
VIN > 1.2 V
0.84
VIN ≤ 1.2 V
0.7 x VIN
VIN > 1.2 V
0.36
VIN ≤ 1.2 V
0.3 x VIN
V
V
PROTECTION
TSD
Thermal shutdown threshold
TJ rising
TSD_HYS
Thermal shutdown hysteresis
TJ falling below TSD
150
°C
20
°C
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6.6 Typical Characteristics
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
VIN = 2.4 V, VOUT = 3.3 V, TJ = 25°C, unless otherwise noted
60
50
40
30
10
0
0.0001
0.001
0.01
0.1
Output Current (A)
1
50
40
30
Vin = 0.9 V
Vin = 1.2 V
Vin = 1.8 V
Vin = 2.4 V
Vin = 3.0 V
20
60
20
Vout = 2.5 V
Vout = 3.3 V
Vout = 4.0 V
10
0
0.0001
10
0.001
D001
VIN = 0.9 V, 1.2 V, 1.8 V, 2.4 V, 3.0 V, and VOUT = 3.3 V
0.01
0.1
Output Current (A)
1
10
D001
VIN = 2.4 V, and VOUT = 2.5 V, 3.3 V, 4.0 V
Figure 1. Load Efficiency with Different Input
Figure 2. Load Efficiency with Different Output
5
3.4
4
Output Voltage (V)
Output Current (A)
3.35
3
2
3.3
3.25
1
Vin = 0.9 V
Vin = 1.6 V
Vin = 2.4 V
Vin = 3.0 V
Vout = 2.5 V
Vout = 3.3 V
Vout = 4.0 V
0
0.6
3.2
1.2
1.8
2.4
Input Voltage (V)
3
3.6
0
0.5
1
D001
VIN = 0.7 V to 3.6 V, VOUT = 2.5 V, 3.3 V, 4.0 V
1.5
2
2.5
Output Current (A)
3
3.5
4
D001
VIN = 0.9 V, 1.6 V, 2.4 V, 3.0 V, and VOUT = 3.3 V
Figure 3. Maximum Output Current vs Input Voltage
Figure 4. Load Regulation
0.82
0.3
Quiescent Current (PA)
Reference Voltage (V)
0.81
0.8
0.79
0.78
0.25
0.2
0.15
0.77
0.76
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
0.1
0.9
1.2
D001
VIN = 2.4 V, VOUT = 3.3 V, T = –40°C to 125°C
1.5
1.8
2.1
2.4
2.7
Input Voltage (V)
3
3.3
3.6
D001
VIN = 0.9 V to 3.6 V, VOUT = 4.0 V, No switching
Figure 5. Reference Voltage vs Temperature
6
140
Figure 6. Quiescent Current into VIN vs Input Voltage
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Typical Characteristics (continued)
VIN = 2.4 V, VOUT = 3.3 V, TJ = 25°C, unless otherwise noted
20
22
21
Quiescent Current (PA)
Quiescent Current (PA)
19
18
17
16
15
14
1.8
20
19
18
17
16
15
2.2
2.6
3
3.4
Output Voltage (V)
3.8
14
-40
4.2
-20
0
20
40
Temperature (°C)
D001
VIN = 1.2 V, VOUT = 1.8 V to 4.0 V, No switching
60
80 90
D001
VIN = 2.4 V, VOUT = 3.3 V, No switching, T = –40°C to 85°C
Figure 7. Quiescent Current into VOUT vs Output Voltage
Figure 8. Quiescent Current into VOUT vs Temperature
Shutdown Current (PA)
2
1.5
1
0.5
0
-40
-20
0
20
40
Temperature (°C)
60
80 90
D001
VIN = 2.4 V, Into VIN and SW, T = –40°C to 85°C
Figure 9. Shutdown Current vs Temperature
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7 Detailed Description
7.1 Overview
The TPS61021A synchronous step-up converter is designed to operate from an input voltage supply range
between 0.5 V and 4.4 V with 3-A valley switch current limit. The TPS61021A typically operates at a quasiconstant frequency pulse width modulation (PWM) at moderate to heavy load currents. The switching frequency
is 2 MHz when the input voltage is above 1.5 V. The switching frequency reduces down to 1 MHz when the input
voltage goes down from 1.5 V to 1 V. At light load currents, the TPS61021A converter operates in power-save
mode with pulse frequency modulation (PFM). During PWM operation, the converter uses adaptive constant ontime valley current mode control scheme to achieve excellent line/load regulation and allows the use of a small
inductor and ceramic capacitors. Internal loop compensation simplifies the design process while minimizing the
number of external components.
7.2 Functional Block Diagram
VIN
8
Undervoltage
Lockout
VIN
SW
SW
7
6
VOUT
3 VOUT
4 VOUT
EN
5
Logic
Valley Current
Sense
Gate Driver
9 PGND
Thermal
Shutdown
PWM Control
AGND
1
VOUT
Over Voltage
Protection &
Short Circuit
Protection
2 FB
Soft Startup
EA
VREF
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7.3 Feature Description
7.3.1 Under-Voltage Lockout
The TPS61021A has a built-in under-voltage lockout (UVLO) circuit to ensure the device working properly. When
the input voltage is above the UVLO rising threshold of 0.9 V, the TPS61021A can be enabled to boost the
output voltage. After the TPS61021A starts up and the output voltage is above 1.6 V, the TPS61021A can work
with the input voltage as low as 0.5 V.
8
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Feature Description (continued)
7.3.2 Enable and Soft Start
When the input voltage is above the under-voltage lockout (UVLO) rising threshold and the EN pin is pulled to
logic high voltage, the TPS61021A is enabled and starts up. At the beginning, the switching frequency and
current limit are internally controlled. The load capability is limited. After the output voltage is above 1.6 V, the
peak current limit is determined by the output of an internal error amplifier which compares the feedback of the
output voltage and the internal reference voltage. Because the output voltage is below the setting target, the
peak current limit rises and thus the output voltage ramps quickly. The soft startup time varies with the different
output capacitance and load condition. The typical startup time is around 200 μs for a 44-μF output capacitor with
no load.
7.3.3 Switching Frequency
The TPS61021A switches at a quasi-constant 2-MHz frequency when the input voltage is above 1.5 V. When the
input voltage declines from 1.5 V to 1 V, the switching frequency will be reduced gradually to 1-MHz to improve
the efficiency and get higher boost ratio. When the input voltage is below 1 V, the switching frequency is fixed at
a quasi-constant 1 MHz.
7.3.4 Current Limit Operation
The TPS61021A employs a valley current limit sensing scheme. Current limit detection occurs during the off-time
by sensing of the voltage drop across the synchronous rectifier switch.
When the load current is increased such that the inductor current is above the current limit within the whole
switching cycle time, the off-time is increased to allow the inductor current to decrease to this threshold before
the next on-time begins (so called frequency fold-back mechanism). When the current limit is reached, the output
voltage decreases during further load increase.
The maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by
Equation 1.
1
§
·
IOUT(CL) 1 D u ¨ ILIM
'IL P P ¸
2
©
¹
(1)
Where:
D is the duty cycle
ΔIL(P-P) is the inductor ripple current
The duty cycle can be estimated by Equation 2.
V uK
D 1 IN
VOUT
(2)
Where:
VOUT is the output voltage of the boost converter
VIN is the input voltage of the boost converter
η is the efficiency of the converter, use 90% for most applications
And the peak-to-peak inductor ripple current is calculated by Equation 3.
VIN u D
'IL P P
L u fSW
(3)
Where:
L is the inductance value of the inductor
fSW is the switching frequency
D is the duty cycle
VIN is the input voltage of the boost converter
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Feature Description (continued)
7.3.5 Pass-Through Operation
When the input voltage is higher than the setting output voltage, the output voltage is higher than the target
regulation voltage. When the output voltage is 101% of the setting target voltage, the TPS61021A stops
switching and turns on the high side PMOS FET. The device works in pass-through mode. The output voltage is
the input voltage minus the voltage drop across the dc resistance (DCR) of the inductor and the on-resistance
(RDS(on)) of the PMOS FET. When the output voltage drops below the 98% of the setting target voltage as the
input voltage declines or the load current increases, the TPS61021A resumes switching again to regulate the
output voltage.
7.3.6 Over-Voltage Protection
The TPS61021A has an output over-voltage protection (OVP) to protect the device in case that the external
feedback resistor divider is wrongly populated. When the output voltage is above 4.35 V typically, the device
stops switching. Once the output voltage falls 0.1 V below the OVP threshold, the device resumes operating
again. To prevent the high overshoot voltage during OVP when the FB pin voltage is too much lower than the
internal reference voltage, the TPS61021A limits the valley swtich current to approximate 100 mA when the FB
pin voltage is below 0.2 V and the output voltage is above 2.9V.
7.3.7 Output Short-to-Ground Protection
The TPS61021A starts to limit the output current when the output voltage is below 1.6 V. The lower the output
voltage reaches, the smaller the output current is. When the output voltage is below 1 V, the output current is
limited to approximate 100 mA. Once the short circuit is released, the TPS61021A goes through the soft startup
again to output the regulated voltage.
7.3.8 Thermal Shutdown
The TPS61021A goes into thermal shutdown once the junction temperature exceeds 150°C. When the junction
temperature drops below the thermal shutdown temperature threshold less the hysteresis, typically 130°C, the
device starts operating again.
7.4 Device Functional Modes
The TPS61021A has two switching operation modes, PWM mode in moderate to heavy load conditions and
power save mode with pulse frequency modulation (PFM) in light load conditions.
7.4.1 PWM Mode
The TPS61021A uses a quasi-constant 2.0-MHz frequency pulse width modulation (PWM) at moderate to heavy
load current. Based on the input voltage to output voltage ratio, a circuit predicts the required on-time. At the
beginning of the switching cycle, the NMOS switching FET, shown in the functional block diagram, is turned on.
The input voltage is applied across the inductor and the inductor current ramps up. In this phase, the output
capacitor is discharged by the load current. When the on-time expires, the main switch NMOS FET is turned off,
and the rectifier PMOS FET is turned on. The inductor transfers its stored energy to replenish the output
capacitor and supply the load. The inductor current declines because the output voltage is higher than the input
voltage. When the inductor current hits a value which the error amplifier outputs, the next switching cycle starts
again.
The TPS61021A has a built-in compensation circuit that can accommodate a wide range of input voltage, output
voltage, inductor value and output capacitor value for stable operation.
10
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Device Functional Modes (continued)
7.4.2 Power Save Mode
The TPS61021A integrates a power save mode with pulse frequency modulation (PFM) to improve efficiency at
light load. When the load current decreases, the inductor valley current set by the output of the error amplifier
declines to regulate the output voltage. When the inductor valley current hits the low limit of approximate 100
mA, the output voltage will exceed the setting voltage as the load current decreases further. When the FB
voltage hits the PFM reference voltage, the TPS61021A goes into the power save mode. In the power save
mode, when the FB voltage rises and hits the PFM reference voltage, the device continuous switching for several
cycles because of the delay time of the internal comparator. Then it stops switching. The load is supplied by the
output capacitor and the output voltage declines. When the FB voltage falls below the PFM reference voltage,
after the delay time of the comparator, the device starts switching again to ramp up the output voltage.
Output
Voltage
PFM mode at light load
1.008 x VOUT_NOM
VOUT_NOM
PWM mode at heavy load
Figure 10. Output Voltage in PWM Mode and PFM Mode
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61021A is a synchronous boost converter designed to operate from an input voltage supply range
between 0.5 V and 4.4 V with 3-A valley switch current limit. The TPS61021A typically operates at a quasiconstant 2-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents when the input
voltage is above 1.5 V. The switching frequency changes to 1-MHz gradually with the input voltage changing
from 1.5 V to 1 V to get better efficiency and high step-up ratio. At light load currents, the TPS61021A converter
operates in power-save mode with pulse frequency modulation (PFM) to achieve high efficiency over the entire
load current range.
8.2 Typical Application
The TPS61021A provides a power supply solution for portable or smart devices powered by batteries or supercapacitors. With 3-A switch current capability, the TPS61021A can output 3.3 V and 1.5 A from two alkaline
batteries in series even if the battery voltage is down to 1.8 V.
L1
1.8 V ~ 3.2 V
C1
0.47 µH
10 µF
VIN
SW
3.3 V
VOUT
C3
PGND
TPS61021A
ON
R1
316 k
2 x 22 µF
FB
OFF
EN
10 pF
C2
R2
100 k
AGND
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Figure 11. 2-Cell Alkaline Battery to 3.3-V Boost Converter
8.2.1 Design Requirements
The design parameters are listed in Table 1.
Table 1. Design Parameters
12
PARAMETERS
VALUES
Input voltage
1.8 V to 3.2 V
Output voltage
3.3 V
Output current
1.5 A
Output voltage ripple
±50 mV
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8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider (R1, R2 in Figure 11). When the output voltage is
regulated, the typical voltage at the FB pin is VREF. Thus the resistor divider is determined by Equation 4.
§V
R1 ¨ OUT
© VREF
·
1¸ u R2
¹
(4)
Where:
VOUT is the regulated output voltage
VREF is the internal reference voltage at the FB pin
For best accuracy, R2 should be kept smaller than 400 kΩ to ensure the current flowing through R2 is at least
100 times larger than the FB pin leakage current. Changing R2 towards a lower value increases the immunity
against noise injection. Changing the R2 towards a higher value reduces the quiescent current for achieving
highest efficiency at low load currents.
8.2.2.2 Inductor Selection
Because the selection of the inductor affects steady state operation, transient behavior, and loop stability, the
inductor is the most important component in power regulator design. There are three important inductor
specifications, inductor value, saturation current, and dc resistance (DCR).
The TPS61021A is designed to work with inductor values between 0.33 µH and 1.0 µH. Follow Equation 5 to
Equation 7 to calculate the inductor’s peak current for the application. To calculate the current in the worst case,
use the minimum input voltage, maximum output voltage, and maximum load current of the application. To have
enough design margins, choose the inductor value with -30% tolerances, and low power-conversion efficiency for
the calculation.
In a boost regulator, the inductor dc current can be calculated by Equation 5.
VOUT u IOUT
IL DC
VIN u K
(5)
Where:
VOUT is the output voltage of the boost converter
IOUT is the output current of the boost converter
VIN is the input voltage of the boost converter
η is the power conversion efficiency, use 90% for most applications
The inductor ripple current is calculated by Equation 6.
VIN u D
'IL P P
L u fSW
(6)
Where:
D is the duty cycle, which can be calculated by Equation 2
L is the inductance value of the inductor
fSW is the switching frequency
VIN is the input voltage of the boost converter
Therefore, the inductor peak current is calculated by Equation 7.
'IL P P
IL P IL DC
2
(7)
Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor
current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic
hysteresis losses in the inductor and EMI. But in the same way, load transient response time is increased. The
inductor’s saturation current must be higher than the calculated peak inductor current. Table 2 lists the
recommended inductors for the TPS61021A.
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Table 2. Recommended Inductors for the TPS61021A
(1)
PART NUMBER
L(µH)
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
SIZE (LxWxH)
VENDOR (1)
XFL4015-471ME
0.47
8.36
6.6
4.0×4.0×1.5
Coilcraft
Wurth Elecktronik
744383360047
0.47
22
8.0
3.0x3.0x2.0
DFE252012P-R47M
0.47
27
5.7
2.5×2.0×1.2
Toko
XFL4020-102ME
1.0
11.9
5.4
4.0×4.0×2.1
Coilcraft
See Third-party Products disclaimer
8.2.2.3 Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for output ripple and loop stability. The ripple
voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a ceramic
capacitor with zero ESR, the minimum capacitance needed for a given ripple voltage can be calculated by
Equation 8.
IOUT u DMAX
COUT
fSW u VRIPPLE
(8)
Where:
DMAX is the maximum switching duty cycle
VRIPPLE is the peak to peak output ripple voltage
IOUT is the maximum output current
fSW is the switching frequency
The ESR impact on the output ripple must be considered if tantalum or aluminum electrolytic capacitors are
used. The output peak to peak ripple voltage caused by the ESR of the output capacitors can be calculated by
Equation 9.
VRIPPLE(ESR) IL(P) u RESR
(9)
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias voltage, aging, and ac signal.
For example, the dc bias voltage can significantly reduce capacitance. A ceramic capacitor can lose more than
50% of its capacitance at its rated voltage. Therefore, always leave margin on the voltage rating to ensure
adequate capacitance at the required output voltage. Increasing the output capacitor makes the output ripple
voltage smaller in PWM mode.
It is recommended to use the X5R or X7R ceramic output capacitor in the range of 10 μF to 200 μF effective
capacitance. For output current less than 300 mA, the effective output capacitance could be reduced to 3.0 μF.
The output capacitor affects the small signal control loop stability of the boost regulator. If the output capacitor is
below the range, the boost regulator can potentially become unstable.
8.2.2.4 Feedforward Capacitor Selection
A feedforward capacitor between the VOUT pin and FB pin induces a pair of zero and pole in the loop transfer
function. Setting the proper zero frequency can increase the phase margin to improve the loop stability. The
TPS61021A needs a feedforward capacitor (C3 in Figure 11) in most applications. It is recommended to set the
zero frequency (fFFZ) to 50 kHz when the effective output capacitance is less than 40 μF. For large output
capacitance more than 40 μF, it is recommended to set the zero frequency (fFFZ) to 5 kHz. The value of the
feedforward capacitor can be calculated by Equation 10.
1
C3
2S u fFFZ u R1
(10)
Where:
R1 is the resistor between the VOUT pin and FB pin
fFFZ is the zero frequency created by the feedforward capacitor
14
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8.2.2.5 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are excellent choices for input decoupling of the step-up converter as
they have extremely low ESR and are available in small footprints. Input capacitors should be located as close
as possible to the device. While a 10-μF input capacitor is sufficient for most applications, larger values may be
used to reduce input current ripple without limitations. Take care when using only ceramic input capacitors. When
a ceramic capacitor is used at the input and the power is being supplied through long wires, a load step at the
output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability
or could even damage the part. Additional bulk capacitance (tantalum or aluminum electrolytic capacitor) should
in this circumstance be placed between ceramic input capacitor and the power source to reduce ringing that can
occur between the inductance of the power source leads and ceramic input capacitor.
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8.2.3 Application Curves
VIN = 2.4 V, VOUT = 3.3 V, IOUT = 2 A
VIN = 2.4 V, VOUT = 3.3 V, IOUT = 100 mA
Figure 12. Switching Waveform at Heavy Load
VIN = 2.4 V, VOUT = 3.3 V, 12 Ω resistance load
Figure 13. Switching Waveform at Light Load
VIN = 2.4 V, VOUT = 3.3 V, 12 Ω resistance load
Figure 15. Shutdown Waveform
Figure 14. Startup Waveform
VIN = 2.4 V, VOUT = 3.3 V, IOUT = 1 A to 2 A
VIN = 1.6 V to 2.4 V, VOUT = 3.3 V, IOUT = 1 A
Figure 16. Load Transient
16
Figure 17. Line Transient
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9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 0.5 V to 4.4 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. A typical choice is a tantalum or
aluminum electrolytic capacitor with a value of 100 µF. The input power supply’s output current needs to be rated
according to the supply voltage, output voltage and output current of the TPS61021A.
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10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those running at high switching frequency and high currents,
layout is an important design step. If the layout is not carefully done, the regulator could suffer from instability
and noise problems. To maximize efficiency, switch rise and fall time are very fast. To prevent radiation of high
frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin, and always use a ground plane under the switching
regulator to minimize interplane coupling. The input capacitor needs not only to be close to the VIN pin, but also
to the PGND pin in order to reduce input supply ripple.
The most critical current path for all boost converters is from the switching FET, through the rectifier FET, then
the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise
and fall time and should be kept as short as possible. Therefore, the output capacitor needs not only to be close
to the VOUT pin, but also to the PGND pin to reduce the overshoot at the SW pin and VOUT pin.
10.2 Layout Example
GND
AGND
VIN
FB
VOUT
VOUT
VOUT
SW
PGND
SW
VIN
EN
GND
Figure 18. Layout Example
10.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions.
Calculate the maximum allowable dissipation, PD(max), and keep the actual power dissipation less than or equal to
PD(max). The maximum-power-dissipation limit is determined using Equation 11.
125 TA
PD max
RTJA
(11)
Where:
TA is the maximum ambient temperature for the application
RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
The TPS61021A comes in a thermally-enhanced WSON package. This package includes a thermal pad that
improves the thermal capabilities of the package. The real junction-to-ambient thermal resistance of the package
greatly depends on the PCB type, layout, and thermal pad connection. Using thick PCB copper and soldering the
thermal pad to a large ground plate to enhance the thermal performance. Using more vias connects the ground
plate on the top layer and bottom layer around the IC without solder mask also improves the thermal capability.
18
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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12.1 Package Option Addendum
12.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
Op Temp (°C)
Device Marking (4) (5)
TPS61021ADSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1
YEAR
–40 to 125
11G
TPS61021ADSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1
YEAR
–40 to 125
11G
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
20
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12.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TPS61021ADSGR
WSON
DSG
8
3000
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
TPS61021ADSGT
WSON
DSG
8
250
180.0
8.4
2.3
2.3
1.15
4.0
8.0
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
22
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS61021ADSGR
WSON
DSG
8
3000
210.0
185.0
35.0
TPS61021ADSGT
WSON
DSG
8
250
210.0
185.0
35.0
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61021ADSGR
ACTIVE
WSON
DSG
8
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
11G
TPS61021ADSGT
ACTIVE
WSON
DSG
8
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
11G
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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