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TPS61130, TPS61131, TPS61132
SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
TPS6113x Synchronous SEPIC and Flyback Converter
With 1.1-A Switch and Integrated LDO
1 Features
3 Description
•
The TPS6113x devices provide a complete power
supply solution for products powered by either a onecell Li-Ion or Li-Polymer, or two- to four-cell Alkaline,
NiCd, or NiMH batteries. The devices can generate
two regulated output voltages. It provides a simple
and efficient buck-boost solution for generating 3.3 V
out of an input voltage that can be both higher and
lower than the output voltage. The converter provides
a maximum output current of at least 300 mA with
supply voltages down to 1.8 V. The implemented
SEPIC converter is based on a fixed frequency,
pulse-width-modulation (PWM) controller using a
synchronous rectifier to obtain maximum efficiency.
The maximum peak current in the SEPIC switch is
limited to a value of 1600 mA.
1
•
•
•
•
•
•
•
•
•
•
•
Synchronous, Up to 90% Efficient, SEPIC
Converter With 300-mA Output Current From
2.5-V Input
Integrated 200-mA Reverse Voltage Protected
LDO for DC-DC Output Voltage Post Regulation
or Second Output Voltage
40-μA (Typical) Quiescent Current
Input Voltage Range: 1.8 V to 5.5 V
Fixed and Adjustable Output Voltage Options up
to 5.5 V
Power Save Mode for Improved Efficiency at LowOutput Power
Low Battery Comparator
Power Good Output
Low EMI-Converter (Integrated Antiringing Switch)
Load Disconnect During Shutdown
Overtemperature Protection
Available in a Small 4-mm × 4-mm VQFN-16 or in
a TSSOP-16 Package
2 Applications
•
•
•
All Single Cell Li, Dual or Triple Cell Battery or
USB Powered Products as MP-3 Player, PDAs,
and Other Portable Equipment
Dual Input or Dual Output Mode
High Efficient Li-Ion to 3.3-V Conversion
Typical Application Schematic
The converter can be disabled to minimize battery
drain. During shutdown, the load is completely
disconnected from the battery. A low-EMI mode is
implemented to reduce ringing, and in effect, lower
radiated electromagnetic energy when the converter
enters the discontinuous conduction mode. A power
good output at the SEPIC stage provides additional
control of any connected circuits like cascaded power
supply stages, or microprocessors.
The built-in LDO can be used for a second output
voltage derived either from the SEPIC output or
directly from the battery. The output voltage of this
LDO can be programmed by an external resistor
divider or is fixed internally on the chip. The LDO can
be enabled separately, that is, using the power good
of the SEPIC stage. The device is packaged in a 16pin VQFN package measuring 4 mm × 4 mm (RSA)
or in a 16-pin TSSOP (PW) package.
22 µH
1.8 V up to 6 V
Input
10 µF
Device Information(1)
SWN
VBAT
SWP
VOUT
LBI
TPS61130
FB
10 µF
22 µH
PART NUMBER
VOut1
e.g. 3.3 V
up to 300 mA
TPS61130
100 µF
TPS61131
Control
Inputs
OFF
ON
OFF
ON
SKIPEN
PGOOD
LBO
EN
Control
Outputs
LDOIN
OFF
ON
LDOEN
GND
LDOOUT
PGND
LDOSENSE
VOut2
e.g. 1.5 V
up to 300 mA
TPS61132
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
VQFN (16)
4.00 mm × 4.00 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2.2 µF
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61130, TPS61131, TPS61132
SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Available Output Voltage Options........................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9.1 Overview ................................................................. 10
9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 11
9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Applications .............................................. 13
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
12.3 Thermal Consideration.......................................... 22
13 Device and Documentation Support ................. 23
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
14 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2008) to Revision C
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS61130 TPS61131 TPS61132
TPS61130, TPS61131, TPS61132
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SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
5 Available Output Voltage Options (1)
PART NUMBER (1)
OUTPUT VOLTAGE DC-DC
OUTPUT VOLTAGE LDO
TPS61130PW
Adjustable
Adjustable
TPS61131PW
3.3 V
3.3 V
TPS61132PW
3.3 V
1.5 V
TPS61130RSA
Adjustable
Adjustable
TPS61132RSA
3.3 V
1.5 V
(1)
(1)
Contact the factory to check availability of other fixed output voltage versions.
The packages are available taped and reeled. Add R suffix to device type (for example, TPS61130PWR or TPS61130RSAR) to order
quantities of 2000 devices per reel for the TSSOP (PW) package and 3000 devices per reel for the QFN (RSA) package.
6 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
SWN
SWP
VOUT
FB
VOUT
FB
PGOOD
LBO
GND
LDOSENSE
LDOOUT
LDOIN
PGND
VBAT
LBI
SKIPEN
Thermal
Pad
PGOOD
LBO
GND
LDOSENSE
EN
LDOEN
LDOIN
LDOOUT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SWP
SWN
PGND
VBAT
LBI
SKIPEN
EN
LDOEN
RSA Package
16-Pin VQFN With Thermal Pad
Top View
Pin Functions
PIN
NAME
NO.
I/O
TSSOP
VQFN
EN
7
5
FB
15
GND
12
LBI
DESCRIPTION
I
DC-DC-enable input. (1/VBAT enabled, 0/GND disabled)
13
I
DC-DC voltage feedback of adjustable versions
10
—
5
3
I
Low battery comparator input (comparator enabled with EN)
LBO
13
11
O
Low battery comparator output (open drain)
LDOEN
8
6
I
LDO-enable input (1/LDOIN enabled, 0/GND disabled)
LDOOUT
10
8
O
LDO output
LDOIN
9
7
I
LDO input
LDOSENSE
11
9
I
LDO feedback for voltage adjustment, must be connected to LDOOUT at fixed output voltage
versions.
PGND
3
1
—
Power ground
PGOOD
14
12
O
DC-DC output power good (1:good, 0:failure) (open drain)
SKIPEN
6
4
I
Enable/disable power save mode (1/VBAT enabled, 0/GND disabled)
SWN
2
16
I
DC-DC switch input
SWP
1
15
I
DC-DC rectifying switch input
VBAT
4
2
I
Supply pin
VOUT
16
14
O
DC-DC output
—
Must be soldered to achieve appropriate power dissipation. Should be connected to PGND.
Thermal Pad
Control/logic ground
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SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Input voltage on FB
–0.3
3.6
V
Input voltage on SWN
–0.3
12
V
Input voltage on SWP
–7
7
V
–12
V
Maximum voltage between SWP and VOUT
Input voltage on VOUT, LDOIN, LDOOUT, LDOEN, LDOSENSE, PGOOD, LBO, VBAT, LBI,
SKIPEN, EN
–0.3
7
V
Operating virtual junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Supply voltage at VBAT
1.8
6.5
V
Operating free air temperature range, TA
–40
85
°C
Operating virtual junction temperature, TJ
–40
125
°C
7.4 Thermal Information
THERMAL METRIC (1)
TPS61130,
TPS61131,
TPS61132
TPS61130
PW (TSSOP)
RSA (VQFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
100.5
33.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
35.9
36.3
°C/W
RθJB
Junction-to-board thermal resistance
45.4
11
°C/W
ψJT
Junction-to-top characterization parameter
2.6
0.5
°C/W
ψJB
Junction-to-board characterization parameter
44.8
11
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
2.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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TPS61130, TPS61131, TPS61132
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SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
7.5 Electrical Characteristics
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC-DC STAGE
VI
Input voltage range
1.8
6.5
V
VO
Adjustable output voltage range
(TPS61130)
2.5
5.5
V
Vref
Reference voltage
485
515
mV
f
Oscillator frequency
ISW
Switch current limit
VOUT = 3.3 V
500
400
500
600
kHz
1100
1300
1600
mA
Start-up current limit
0.4 x ISW
mA
SWN switch on resistance
VOUT = 3.3 V
200
350
mΩ
SWP switch on resistance
VOUT = 3.3 V
250
500
mΩ
Total accuracy (including line and
load regulation)
DC-DC
quiescent current
±3%
into
VBAT
IO = 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0 V
10
25
μA
into
VOUT
IO = 0 mA, VEN = VBAT = 1.8 V,
VOUT = 3.3 V, ENLDO = 0 V
10
25
μA
VEN= 0 V
0.2
1
μA
DC-DC shutdown current
LDO STAGE
VI(LDO)
Input voltage range
1.8
7
V
VO(LDO)
Adjustable output voltage range
(TPS61130)
0.9
5.5
V
IO(max)
Output current
200
320
LDO short circuit current limit
mA
500
mA
300
mV
Minimum voltage drop
IO = 200 mA
Total accuracy (including
line and load regulation)
IO ≥ 1 mA
±3%
Line regulation
LDOIN change from 1.8 V to
2.6 V at 100 mA,
LDOOUT = 1.5 V
0.6%
Load regulation
Load change from 10% to 90%,
LDOIN = 3.3 V
0.6%
LDO quiescent current
LDOIN = 7 V, VBAT = 1.8 V,
EN = VBAT
20
30
μA
LDO shutdown current
LDOEN = 0 V, LDOIN = 7 V
0.1
1
μA
500
510
mV
CONTROL STAGE
VIL
LBI voltage threshold
VLBI voltage decreasing
490
LBI input hysteresis
10
mV
LBI input current
EN = VBAT or GND
0.01
0.1
LBO output low voltage
VO = 3.3 V, IOI = 100 μA
0.04
0.4
LBO output low current
LBO output leakage current
VIL
EN, SKIPEN input low
voltage
VIH
EN, SKIPEN input high
voltage
VIL
LDOEN input low voltage
VIH
LDOEN input high voltage
0.01
0.1
0.2 × VBAT
0.8 × VBAT
0.2 × VLDOIN
Clamped on GND or VBAT
Power-Good threshold
VO = 3.3 V
0.9 × Vo
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS61130 TPS61131 TPS61132
μA
V
V
0.8 × VLDOIN
EN, SKIPEN input current
V
μA
100
VLBO = 7 V
μA
V
V
0.01
0.1
μA
0.92 × Vo
0.95 × Vo
V
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Electrical Characteristics (continued)
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Power-Good delay
MAX
UNIT
μs
30
Power-Good output low voltage
VO = 3.3 V, IOI = 100 μA
0.04
Power-Good output low current
Power-Good output leakage
current
0.4
VPG = 7 V
0.01
V
μA
100
0.1
μA
Overtemperature protection
140
°C
Overtemperature hysteresis
20
°C
7.6 Typical Characteristics
Table 1. Table of Graphs
SEPIC CONVERTER
FIGURE
Maximum output current
vs Input voltage (TPS61130) (VO = 3.3 V, 5 V, 2.5 V)
Efficiency
Figure 1 Figure 2
vs Output current (TPS61130) (VO = 2.5 V, VI = 1.8 V)
Figure 3
vs Output current (TPS61132) (VO = 3.3 V, VI = 1.8 V, 3.8 V)
Figure 4
vs Output current (TPS61130) (VO = 5 V, VI = 3.6 V, 6 V)
Figure 2
vs Input voltage (TPS61132)
Figure 5
Output voltage
vs Output current (TPS61132)
Figure 6
No-load supply current into VBAT
vs Input voltage (TPS61132)
Figure 7
No-load supply current into VOUT
vs Input voltage (TPS61132)
Figure 8
LDO
vs Input voltage (VO = 2.5 V, 3.3 V)
Figure 9
vs Input voltage (VO = 1.5 V, 1.8 V)
Figure 10
Output voltage
vs Output current (TPS61131)
Figure 11
Dropout voltage
vs Output current (TPS61131, TPS61132)
Figure 12
Supply current into LDOIN
vs LDOIN input voltage (TPS61132)
Figure 13
PSRR
vs Frequency (TPS61132)
Figure 14
Maximum output current
0.7
0.70
0.65
0.5
0.60
Maximum Output Current − A
Maximum Output urrent − A
0.6
VO = 3.3 V
VO = 5 V
0.4
0.3
0.2
0.1
0
1.8 2
VO = 2.5 V
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
3
4
5
VI − Input Voltage − V
6
7
Figure 1. TPS61130 Maximum SEPIC Converter Output
Current vs Input Voltage
6
0.55
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0.05
0
1.8 2.2 2.6 3
3.4 3.8 4.2 4.6 5 5.4 5.8 6.2 6.6 7
VI − Input Voltage − V
Figure 2. TPS61130 Maximum SEPIC Converter Output
Current vs Input Voltage
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SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
100
100
TPS61132
TPS61130
VBAT = 3.8 V
90
VBAT = 6 V
90
80
80
VBAT = 3.6 V
VBAT = 1.8 V
70
Efficiency − %
Efficiency − %
70
60
50
40
60
50
40
30
30
20
20
10
10
0
0
0.1
1
10
100
IO − Output Current − mA
0.1
1000
Figure 3. TPS61132 SEPIC Converter Efficiency vs Output
Current
1
10
100
IO − Output Current − mA
1000
Figure 4. TPS61130 SEPIC Converter Efficiency vs Output
Current
100
3.40
95
3.38
VI = 2.4 V
IO = 100 mA
3.36
IO = 200 mA
VO − Output Voltage − V
Efficiency − %
90
85
IO = 10 mA
80
75
3.34
3.32
3.30
3.28
3.26
70
3.24
65
3.22
60
3.20
3
5
VI − Input Voltage − V
1.8
0
7
Figure 5. TPS61132 SEPIC Converter Efficiency vs Input
Voltage
12
No-Load Supply Current Into VOUT − m A
No-Load Supply Current Into VBAT − µ A
14
85°C
25°C
10
−40°C
8
6
4
2
1.8
2
2.2
2.4
2.6
2.8
VI − Input Voltage − V
3
3.2
Figure 7. TPS61132 No-Load Supply Current Into VBAT vs
Input Voltage
400
Figure 6. TPS61132 SEPIC Converter Output Voltage vs
Output Current
14
0
100
200
300
IO − Output Current − mA
85°C
12
25°C
−40°C
10
8
6
4
2
0
1.8
2
2.2
2.4
2.6
2.8
VI − Input Voltage − V
3
3.2
Figure 8. TPS61132 No-Load Supply Current Into VOUT vs
Input Voltage
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400
400
VO = 1.5 V
350
Maximum LDO Output Current − mA
Maximum LDO Output Current − mA
VO = 3.3 V
300
250
VO = 2.5 V
200
150
100
50
350
300
250
VO = 1.8 V
200
150
100
50
0
0
2.5
3
3.5
4
4.5
5
5.5
LDO Input Voltage − V
6
6.5
7
Figure 9. Maximum LDO Output Current vs LDO Input
Voltage
1.5 2
2.5
3 3.5 4 4.5 5 5.5 6
LDO Input Voltage − V
6.5 7
Figure 10. TPS61130 Maximum LDO Output Current vs LDO
Input Voltage
3.4
3.5
3.38
3
LDO Dropout Voltage − V
LDO Output Voltage − V
3.36
3.34
3.32
3.3
3.28
3.26
TPS61131
(LDO OUTPUT
VOLTAGE 1.5 V)
2.5
2
TPS61132
(LDO OUTPUT
VOLTAGE 3.3 V)
1.5
1
3.24
0.5
3.22
3.2
0
0
50
100 150 200 250 300
LDO Output Current − mA
350
10
400
Figure 11. TPS61131 LDO Output Voltage vs LDO Output
Current
60
110
160
210
260
LDO Output Current − mA
310
Figure 12. LDO Dropout Voltage vs LDO Output Current
LDOIN = 3.3 V
70
25°C
60
LDO Output Current 10 mA
15
PSRR − dB
Supply Current Into LDOIN − m A
80
85°C
20
−40°C
10
50
40
30
LDO Output Current 200 mA
20
5
10
0
1.8
2
2.2
2.4
2.6
2.8
LDOIN Input Voltage − V
3
3.2
Figure 13. TPS61132 Supply Current Into LDOIN vs LDOIN
Input Voltage
8
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0
1k
10k
100k
f − Frequency − Hz
1M
10M
Figure 14. TPS61132 PSRR vs Frequency
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SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
8 Parameter Measurement Information
C7
10 µF
U1
L1−A
L1−B
22 µH
Power
Supply
C3
10 µF
SWN
SWP
VBAT
VOUT
22 µH
R3
R1
C6
2.2 µF
FB
VCC1
SEPIC Output
C4
100 µF
LBI
R2
LDOIN
SKIPEN
R6
VCC2
LDO Output
LDOOUT
R5
R4
List of Components:
U1 = TPS6113xPW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
C5
2.2 µF
LDOSENSE
EN
LDOEN
GND
R7
R9
LBO
PGOOD
PGND
Control
Outputs
TPS6113xPW
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9 Detailed Description
9.1 Overview
The TPS6113x synchronous step-up converter typically operates at a 500-kHz frequency pulse width modulation
(PWM) at moderate to heavy load currents. The converter enters Power Save mode at low load currents to
maintain a high efficiency over a wide load. The Power Save mode can also be disabled, forcing the converter to
operate at a fixed switching frequency. The device includes an additional built-in LDO which can be used to
generate a second output voltage derived from the output of the TPS6113x or an external power supply.
Additionally, TPS6113x integrated the low-battery detector circuit is used to supervise the battery voltage and to
generate an error flag when the battery voltage drops below a user-set threshold voltage.
9.2 Functional Block Diagram
SWN
SWP
Backgate
Control
AntiRinging
VBAT
VOUT
100 kΩ
VOUT
Vmax
Control
20 pF
Gate
Control
PGND
PGND
Regulator
PGND
Error
Amplifier _
FB
+
Vref = 0.5 V
Control Logic
+
_
GND
Oscillator
Temperature
Control
EN
PGOOD
ENLDO
SKIPEN
LDOIN
Backgate
Control
GND
Error
Amplifier
LBO
Low Battery
Comparator
_
LBI
_
LDOSENSE
+
Vref = 0.5 V
+
+
_
LDOOUT
+
_
GND
Vref = 0.5 V
GND
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9.3 Feature Description
9.3.1 Controller Circuit
The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input
voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So
changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect
and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,
only must handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output
voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to
generate an accurate and stable output voltage.
The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and
the inductor. The typical peak current limit is set to 1300 mA. An internal temperature sensor prevents the device
from getting overheated in case of excessive power dissipation.
9.3.2 Synchronous Rectifier
The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.
Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power
conversion efficiency reaches 90%. To avoid ground shift due to the high currents in the NMOS switch, two
separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS
switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND
pin. Due to the nature of the SEPIC topology, there is no DC path from the battery to the output. No additional
components must be added in a SEPIC or Flyback topology to make sure the battery is disconnected from the
output of the converter.
Nevertheless, the backgate diode of the high-side PMOS which is forward biased in standard operation, is turned
off in shutdown. This is done by a special circuit which takes the cathode of the backgate diode of the high-side
PMOS and disconnects it from the source when the regulator is not enabled (EN = low).
9.3.3 Device Enable
The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In
shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is
switched off, and the backgate diode of the rectifying switch is turned off (as described in the Synchronous
Rectifier Section). This also means that the output voltage can drop below the input voltage during shutdown.
During start-up of the converter, the duty cycle and the peak current are limited to avoid high peak currents
drawn from the battery.
9.3.4 Undervoltage Lockout
An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than
approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the
shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is
implemented to prevent the malfunctioning of the converter.
9.3.5 Soft-Start
When the SEPIC section is enabled, the internal start-up cycle starts with switching at a duty cycle of 50%. After
the output voltage has reached approximately 1.4 V the device continues switching with a variable duty cycle.
Until the programmed output voltage is reached, the main switch current limit is set to 40% of its nominal value to
avoid high peak inrush currents at the battery during start-up. Also the maximum output power during output
short circuit conditions is reduced. When the programmed output voltage is reached, the regulator takes control
and the switch current limit is set back to 100%.
9.3.6 Power Good
The PGOOD pin stays high impedance when the DC-DC converter delivers an output voltage within a defined
voltage window. So it can be used to enable any connected circuitry such as cascaded converters (LDO) or
microprocessor circuits.
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Feature Description (continued)
9.3.7 Low Battery Detector Circuit—LBI/LBO
The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag
when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is
enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI.
During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold.
It is active low when the voltage at LBI goes below 500 mV.
The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider
connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV,
which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See
Application and Implementation for more details about the programming of the LBI threshold. If the low-battery
detection circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left
unconnected. Do not let the LBI pin float.
9.3.8 Low-EMI Switch
The device integrates a circuit that removes the ringing that typically appears on the SW node when the
converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the
rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the
battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the
inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and
therefore dampens ringing.
9.4 Device Functional Modes
9.4.1 Power Save Mode
The SKIPEN pin can be used to select different operation modes. To enable the power save mode, SKIPEN
must be set high. Power save mode is used to improve efficiency at light loads. In power save mode, the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses, and goes again into power save mode once the output voltage exceeds the set
threshold voltage. The power save mode can be disabled by setting the SKIPEN to GND.
9.4.2 LDO
The built-in LDO can be used to generate a second output voltage derived from the DC-DC converter output,
from the battery, or from another power source like an AC adapter or a USB power rail. The LDO is capable of
being back biased. This allows the user just to connect the outputs of DC-DC converter and LDO. So the device
is able to supply the load through DC-DC converter when the energy comes from the battery and efficiency is
most important and from another external power source through the LDO when lower efficiency is not critical.
The LDO must be disabled if the LDOIN voltage drops below LDOOUT to block reverse current flowing. The
status of the DC-DC stage (enabled or disabled) does not matter.
9.4.3 LDO Enable
The LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at the
DC-DC converter stage described above. This is completely independent of the status of the EN pin. The voltage
levels of the logic signals which must be applied at LDOEN are related to LDOIN.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPS6113x DC-DC converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery
with a typical terminal voltage from 1.8 V to 5.5 V. They can also be used in systems powered by one-cell Li-Ion
with a typical stack voltage from 2.5 V to 4.2 V. Additionally, two or three primary and secondary alkaline battery
cells can be the power source in systems where the TPS6113x is used. The built-in LDO can be used to
generate a second output voltage derived from the DC-DC converter output, from the battery, or from another
power source like an AC adapter or a USB power rail. The maximum programmable output voltage at the LDO is
5.5 V.
10.2 Typical Applications
10.2.1 Typical Application Circuit for Adjustable Output Voltage Option
C7
22 µH
Power
Supply
C3
10 µF
10 µF
U1
L1−A
L1−B
SWN
SWP
VBAT
VOUT
22 µH
R3
R1
VCC1
SEPIC Output
C4
100 µF
C6
2.2 µF
FB
LBI
LDOIN
R2
SKIPEN
R6
LDOOUT
C5
2.2 µF
R5
LDOSENSE
EN
R7
R4
LDOEN
GND
VCC2
LDO Output
R9
LBO
Control
Outputs
PGOOD
PGND
TPS6113xPW
Figure 15. Typical Application Circuit for Adjustable Output Voltage Option
10.2.1.1 Design Requirements
Table 2 shows the design parameters for Figure 15.
Table 2. TPS6113x 3.3-V Output Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input voltage range
1.8 V to 5.5 V
Output voltage boost
3.3 V
Output voltage LDO
1.5 V
Output voltage ripple
±3% VOUT
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10.2.1.2 Detailed Design Procedure
The TPS6113x DC-DC converters are intended for systems powered by a dual up to 4 cell NiCd or NiMH battery
with a typical terminal voltage from 1.8 V to 6.5 V. They can also be used in systems powered by one-cell Li-Ion
with a typical stack voltage from 2.5 V to 4.2 V. Additionally, two up to four primary alkaline battery cells can be
the power source in systems where the TPS6113x is used.
10.2.1.2.1 Programming the Output Voltage
10.2.1.2.1.1
DC-DC Converter
The output voltage of the TPS61130 DC-DC converter section can be adjusted with an external resistor divider.
The typical value of the voltage on the FB pin is 500 mV. The maximum recommended value for the output
voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into
the FB pin. The typical current into the FB pin is 0.01 μA and the voltage across R6 is typically 500 mV. Based
on those two values, the recommended value for R6 should be lower than 500 kΩ, to set the divider current at 1
μA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200
kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using
Equation 1:
æ V
ö
æ VO
ö
R3 = R6 ´ ç O - 1÷ = 180 kW ´ ç
- 1÷
è 500 mV
ø
è VFB
ø
(1)
If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any
reason the value for R6 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is
recommended. The required capacitance value can be easily calculated using Equation 2.
æ 200 kW ö
- 1÷
CparR3 = 20 pF ´ ç
è R6
ø
(2)
10.2.1.2.2
LDO
Programming the output voltage of the LDO follows almost the same rules as at the dc/dc converter section. The
maximum recommended output voltage of the LDO is 5.5 V. Because reference and internal feedback circuitry
are similar, as they are at the DC-DC converter section, R4 also should be in the 200-kΩ range. The calculation
of the value of R5 can be done using the following Equation 3:
æ V
ö
æ VO
ö
R5 = R4 ´ ç O - 1÷ = 180 kW ´ ç
- 1÷
è 500 mV
ø
è VFB
ø
(3)
If as an example, an output voltage of 1.5 V is needed, a 360-kΩ resistor should be chosen for R5.
10.2.1.2.3 Programming the LBI/LBO Threshold Voltage
The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The
typical current into the LBI pin is 0.01 μA, and the voltage across R2 is equal to the LBI voltage threshold that is
generated on-chip, which has a value of 500 mV. The recommended value for R2 is therefore in the range of 500
kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be
calculated using Equation 4.
æ
ö
æ V
ö
VBAT
- 1÷ = 390 kW ´ ç BAT - 1÷
R1 = R2 ´ ç
è 500 mV
ø
è VLBI- threshold
ø
(4)
The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated
battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with
a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not
exceed the output voltage of the DC-DC converter. If not used, the LBO pin can be left floating or tied to GND.
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10.2.1.2.4 Inductor Selection
A SEPIC converter normally requires three main passive components for storing energy during the conversion.
Two inductors, a flying capacitor, and a storage capacitor at the output are required. To select the two inductors,
TI recommends keeping the possible peak inductor current below the current limit threshold of the power switch
in the chosen configuration. For example, the typical current limit threshold of the TPS6113x's switch is 1300 mA
at an output voltage of 3.3 V. The highest peak current through the switch is the sum of the two inductor currents
and depends on the output load, the input (VBAT), and the output voltage (VOUT). Estimation of the maximum
average inductor current of each inductor can be done using Equation 5:
VOUT
IL1- A = IL1-B = IOUT ´
VBAT ´ 0.8
(5)
For example, for an output current of 300 mA at 3.3 V, at least 680 mA of average current flows through each of
the inductors at a minimum input voltage of 1.8 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of around ±20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those
parameters, it is possible to calculate the value for the inductor by using Equation 6:
VBAT ´ VOUT
L1 - A = L1 - B =
DIL ´ ƒ ´ (VOUT + VBAT )
(6)
Parameter f is the switching frequency andΔ IL is the ripple current in the inductor, that is, 40% Δ IL. In this
example, the desired inductance is in the range of 20 μH. With this calculated value and the calculated currents,
it is possible to choose a suitable inductor. In typical applications, TI recommends an inductance of 22 μH. The
device has been optimized to operate with inductance values from 10 μH to 47 μH. Nevertheless operation with
higher inductance values may be possible in some applications. TI recommends a detailed stability analysis.
Take care so that load transients and losses in the circuit can lead to higher currents as estimated in Equation 6.
Also, the losses in the inductor caused by magnetic hysteresis losses and copper losses are a major parameter
for total circuit efficiency.
The following inductor series from different suppliers have been used with the TPS6113X converters:
Table 3. List of Inductors
VENDOR
RECOMMENDED INDUCTOR SERIES
COUPLED INDUCTOR SERIES
LPS4012
LPD4012
LPS3015
—
DR73
DRQ73
DR74
DRQ74
EPCOS
B82462G
—
Sumida
CDRH5D18
—
7447789___
744878220
7447779___
744877220
Coilcraft
Cooper Electronics Technologies
Wurth Electronik
10.2.1.2.5 Capacitor Selection
10.2.1.2.5.1
Input Capacitor
TI recommends at least a 10-μF input capacitor to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.
10.2.1.2.5.2
Flying Capacitor DC-DC Converter
In the normal operating mode, the flying capacitor (C7) must be large enough so that the voltage across the
capacitor is small. This means the resonance frequency formed by the flying capacitor and the inductors must be
at least ten times lower than the switching frequency (see Equation 7).
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Cmin =
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100
4 p2 ƒ 2 L
(7)
Where L is the inductance of L1-A or L1-B.
To optimize efficiency, TI recommends capacitors with very low ESR such as ceramic capacitors. The voltage
rating of the flying capacitor must be higher than the input voltage VBAT.
10.2.1.2.5.3
Output Capacitor DC-DC Converter
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 8:
IOUT ´ VOUT
Cmin =
ƒ ´ DV ´ (VOUT + VBAT )
(8)
Parameter f is the switching frequency and ΔV is the maximum allowed ripple.
With a chosen ripple voltage of 15 mV, a minimum capacitance of 26 μF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 9:
DVESR = IOUT ´ RESR
(9)
An additional ripple of 24 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple
is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this
example, the total ripple is 39 mV. Additional ripple is caused by load transients. This means that the output
capacitance must be larger than calculated above to meet the total ripple requirements. The output capacitor
must completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. With the
calculated minimum value of 26 μF and load transient considerations, the recommended output capacitance
value is in a 100-μF range. For economical reasons this usually is a tantalum capacitor. Because of this the
control loop has been optimized for using output capacitors with an ESR of greater than 30 mΩ. The minimum
value for the output capacitor is 22 μF.
10.2.1.2.5.4 Small Signal Stability
When using output capacitors with lower ESR, like ceramics, TI recommends using the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors.
For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in
Equation 10, can be used.
d
10 ´ (R3 + R6)
AREG =
=
VFB R6 ´ (1 + i ´ w´ 1.6 ms)
(10)
10.2.1.2.5.5
Output Capacitor LDO
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. TI recommends
using ceramic capacitors in the range from 1 μF up to 4.7 μF. At 4.7 μF and above, TI recommends using
standard ESR tantalum. There is no maximum capacitance value.
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10.2.1.3 Application Curves
VI = 3.3 V, RL = 33 W
VI = 3.3 V
IL = 60 mA to 140 mA
Output Voltage
20 mV/Div, AC
Current
100 mA/Div, DC
Output Voltage
20 mV/Div, AC
Inductor Current
100 mA/Div, DC
VO = 3.3 V
VO = 3.3 V
Timebase − 1 µs/Div
Figure 16. TPS61132 SEPIC Converter Output Voltage in
Continuous Mode
Timebase − 500 µs/Div
Figure 17. TPS61132 SEPIC Converter Load Transient
Response
VI = 1.8 V to 2.6 V
RL = 15 W
Enable
5 V/Div, DC
Input Voltage
1 V/Div, DC
Output Voltage
2 V/Div, DC
Voltage at SW
5 V/Div, DC
Output Voltage
10 mV/Div, AC
Input Current
200 mA/Div, DC
VI = 3.6 V, RL = 66 W
VO = 3.3 V
VO = 1.5 V
Timebase − 400 µs/Div
Timebase − 2 ms/Div
Figure 18. TPS61132 SEPIC Converter Start-Up After
Enable
Figure 19. TPS61132 LDO Line Transient Response
VI = 3.3 V
IL = 20 mA to 180 mA
VI = 3.3 V
RL = 15
Output Current
100 mA/Div, DC
LDO-Enable
5 V/Div, DC
LDO-Output Voltage
1 V/Div, DC
Output Voltage
20 mV/Div, AC
Input Current
200 mA/Div, DC
VO = 1.5 V
VO = 1.5 V
Timebase − 500 µs/Div
Figure 20. TPS61132 LDO Load Transient Response
Timebase − 20 µs/Div
Figure 21. TPS61132 LDO Start-Up After Enable
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VI = 3.3 V, RL = 330
VI = 3.0 V to 4.2 V
RL = 33
Input Voltage
1 V/Div, DC
Output Voltage
50 mV/Div, AC
Output Voltage
50 mV/Div, AC
Inductor Current
100 mA/Div, DC
VO = 3.3 V
VO = 3.3 V
Timebase − 200 µs/Div
Timebase − 200 µs/Div
Figure 22. TPS61132 SEPIC Converter Output Voltage in
Power Save Mode
Figure 23. TPS61132 SEPIC Converter Line Transient
Response
10.2.2 Solution for Maximum Output Power
The TPS6113x boost converter with LDO features two independent output voltages. An efficient synchronous
boost converter provides a 3.3-V VOUT1 with output currents more than 250 mA. A >120-mA LDO regulator
generates a 1.5-V VOUT2. The two outputs can be used independently from each other.
C7
10 µF
U1
L1−B
L1−A
22 µH
SWN
SWP
VBAT
VOUT
22 µH
C6
2.2 µF
R1
C3
10 µF
C4
100 µF
3.3 V,
>250 mA
LBI
LDOIN
R2
SKIPEN
LDOOUT
C5
2.2 µF
LDOSENSE
EN
R7
List of Components:
U1 = TPS61132PW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
LDOEN
GND
LBO
1.5 V,
>120 mA
R9
LBO
PGOOD
PGND
PGOOD
TPS61132PW
Figure 24. Solution for Maximum Output Power
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10.2.3 Low Profile Solution, Maximum Height 1.8 mm
The TPS6113x boost converter with LDO features two independent output voltages. An efficient synchronous
boost converter provides a 3.3-V VOUT1 and followed by a post-LDO generates a 1.5-V VOUT2.
TPS6113x could support low profile inductor with a height of 1.8 mm.
C7
10 µF
U1
L1
L2
22 µH
SWN
SWP
VBAT
VOUT
22 µH
3.3 V
C6
2.2 µF
R1
C3
10 µF
C4
100 µF
LBI
R2
LDOIN
SKIPEN
1.5 V
LDOOUT
C5
2.2 µF
LDOSENSE
EN
R7
List of Components:
U1 = TPS61132PW
L1 , L2 = Sumida 5D18−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR, Low Profile Tantalum
LDOEN
GND
R9
LBO
LBO
PGOOD
PGOOD
PGND
TPS61132PW
Figure 25. Low Profile Solution, Maximum Height 1.8 mm
10.2.4 Single Output Using LDO as Filter
The TPS6113x could provide a linear output of 3.3 V with the input from the output of the boost converter to
enable lower noise output.
C7
10 µF
U1
L1−A
22 µH
C3
10 µF
L1−B
SWN
SWP
VBAT
VOUT
22 µH
R3
R1
C6
22 µF
FB
LBI
R6
R2
SKIPEN
LDOIN
LDOOUT
3.3 V
R5
C5
2.2 µF
LDOSENSE
EN
R7
R4
LDOEN
List of Components:
U1 = TPS61130PW
L1 = Coiltronics DRQ74−220
C3, C5, C7 = X7R/X5R Ceramic
C6 = X7R/X5R Ceramic or Low
ESR Tantalum
GND
LBO
R9
LBO
PGOOD
PGND
PGOOD
TPS61130PW
Figure 26. Single Output Using LDO as Filter
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10.2.5 Dual Input Power Supply Solution
The TPS6113x boost converter can support dual input power supply, one input for boost converter to generate a
3.3 Vout, while the other input for LDO to generate the second 3.3 Vout independently.
USB Input
4.2 V...5.5 V
D1
C7
10 µF
U1
L1−B
L1−A
SWN
22 µH
VBAT
C3
10 µF
SWP
22 µH
VOUT
R3
1 MΩ
R1
FB
LBI
LDOIN
R2
SYNC
EN
List of Components:
U1 = TPS61130PW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
D1 = On-Semiconductor MBR0520
LDOOUT
LDOSENSE
R5
1.022 MΩ
R7
LBO
GND
C4
100 mF
R6
180 kΩ
R4
180 kΩ
LDOEN
C6
2.2 µF
VCC
3.3 V System Supply
R8
Control
Outputs
PGOOD
PGND
TPS61130PW
Figure 27. Dual Input Power Supply Solution
20
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Product Folder Links: TPS61130 TPS61131 TPS61132
TPS61130, TPS61131, TPS61132
www.ti.com
SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
11 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 1.8 V to 5.5 V. This input supply must
be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
12 Layout
12.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor must be placed as close as possible to the device.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the device.
The feedback divider must be placed as close as possible to the control ground pin of the device. To lay out the
control ground, TI recommends using short traces as well, separated from the power ground traces. This avoids
ground shift problems, which can occur due to superimposition of power ground current and control ground
current.
12.2 Layout Example
GND
GND
VOUT
VIN
GND
SWP
1
16
VOUT
SWN
2
15
FB
PGND
3
14
VBAT
4
13
PGOOD
LBO
LBI
5
12
GND
SKIPEN
6
11
LDOSENSE
EN
7
10
LDOOUT
LDOEN
8
GND
9
LDOIN
LDO
OUT
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS61130 TPS61131 TPS61132
GND
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TPS61130, TPS61131, TPS61132
SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
www.ti.com
12.3 Thermal Consideration
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Follow these three basic approaches for enhancing thermal performance.
• Improving the power dissipation capability of the PCB design.
• Improving the thermal coupling of the component to the PCB.
• Introducing airflow in the system.
The maximum recommended junction temperature (TJ) of the TPS6113x devices is 150°C. The thermal
resistance of the 16-pin TSSOP package (PW) is RΘJA = 100.5 °C/W. The 16-pin VQFN package (RSA) with
exposed thermal pad has a thermal resistance of RΘJA = 33.9°C/W, if the thermal pad is soldered and the board
layout is optimized. Specified regulator operation is assured to a maximum ambient temperature TA of 85°C.
Therefore, the maximum power dissipation is about 647 mW for the TSSOP (PW) package and 1917 mW for the
VQFN (RSA) package. More power can be dissipated if the maximum ambient temperature of the application is
lower (see Equation 11).
TJ(MAX) - TA
PD(MAX) =
RqJA
(11)
If designing for a lower junction temperature of 125°C, which TI recommends, maximum heat dissipation is lower.
Using the above Equation 11 results in 1917-mW power dissipation for the RSA package and 647 mW for the
PW package.
22
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Product Folder Links: TPS61130 TPS61131 TPS61132
TPS61130, TPS61131, TPS61132
www.ti.com
SLVS431C – JUNE 2002 – REVISED SEPTEMBER 2015
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS61130
Click here
Click here
Click here
Click here
Click here
TPS61131
Click here
Click here
Click here
Click here
Click here
TPS61132
Click here
Click here
Click here
Click here
Click here
13.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2002–2015, Texas Instruments Incorporated
Product Folder Links: TPS61130 TPS61131 TPS61132
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS61130PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS61130
Samples
TPS61130PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS61130
Samples
TPS61130RSAR
ACTIVE
QFN
RSA
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS6
1130
Samples
TPS61131PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PS61131
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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