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TPS61165-Q1
SLVSB73B – DECEMBER 2011 – REVISED MAY 2015
TPS61165-Q1 High-Brightness White LED Driver in SOT-23 Package
1 Features
3 Description
•
•
With a 40-V rated integrated switch FET, the
TPS61165-Q1 device is a boost converter that drives
LEDs in series. The boost converter runs at a 1.2MHz fixed switching frequency with 1.2-A switch
current limit, and allows for the use of a high
brightness LED in general lighting.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
40-V Maximum Breakdown Voltage of Internal
MOSFET
38-V Open LED Protection
200-mV Reference Voltage With 2% Accuracy
1.2-A Switch FET With 1.2-MHz Switching
Frequency
Flexible 1-Wire Digital and PWM Brightness
Control
Built-in Soft Start
Up to 90% Efficiency
SOT-23 Package
The default white LED current is set with the external
sensor resistor Rset, and the feedback voltage is
regulated to 200 mV, as shown in the Typical
Application section. During the operation, the LED
current can be controlled using the 1-wire digital
interface (EasyScale™ protocol) through the CTRL
pin. Alternatively, a pulse width modulation (PWM)
signal can be applied to the CTRL pin through which
the duty cycle determines the feedback reference
voltage. In either digital or PWM mode, the
TPS61165-Q1 device does not burst the LED current;
therefore, the device does not generate audible
noises on the output capacitor. For maximum
protection, the TPS61165-Q1 device features
integrated open LED protection that disables it to
prevent the output from exceeding its absolute
maximum voltage ratings during open LED
conditions.
2 Applications
•
•
•
High-Brightness LED Lighting
White LED Backlighting for Media Form Factor
Display
Automotive Cluster Backlighting
The TPS61165-Q1 device is available in a SOT-23
package.
Device Information(1)
PART NUMBER
PACKAGE
TPS61165-Q1
SOT-23 (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
L1
10 mH
Vbat
D1
C1
4.7 mF
R1
1 kW
C4
1 mF
D2
12 V
TPS61165-Q1
ON/OFF
DIMMING
CONTROL
C3
220 nF
VIN
SW
CTRL
FB
COMP
GND
L1: TOKO #A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM188R61E105K
C4: Murata GRM188R61E105K
D1: ONsemi MBR0540T1
D2: ONsemi 1SMB5927BT3G
R1: Vishay CRCW08051K00FKEA
LED: OSRAM LW-W5SM
C2
1 mF
350 mA
Rset
0.57 W
Or Equivalent
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61165-Q1
SLVSB73B – DECEMBER 2011 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
3
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
9
7.5 Programming............................................................. 9
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application .................................................. 15
8.3 Do's and Don'ts ....................................................... 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 19
10.3 Thermal Considerations ........................................ 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support .......................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision A (September 2013) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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SLVSB73B – DECEMBER 2011 – REVISED MAY 2015
5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
TOP VIEW
VIN 1
6 FB
CTRL 2
5 COMP
SW 3
4 GND
6-PIN SOT-23
Pin Functions
PIN
I/O
DESCRIPTION
5
O
Output of the transconductance error amplifier. Connect an external capacitor to this pin to compensate the
converter.
CTRL
2
I
Control pin of the boost converter. It is a multi-functional pin which can be used for enable control, PWM,
and digital dimming.
FB
6
I
Feedback pin for current. Connect the sense resistor from FB to GND.
GND
4
O
Ground
SW
3
I
This is the switching node of the IC. Connect the switched side of the inductor to SW. This pin is also used
to sense the output voltage for open LED protection.
VIN
1
I
The input supply pin for the IC. Connect VIN to a supply voltage between 3 V and 18 V.
NAME
NO.
COMP
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply Voltages on VIN
(1)
(2)
MIN
MAX
UNIT
–0.3
20
Voltages on CTRL (2)
–0.3
20
Voltage on FB and COMP (2)
–0.3
3
Voltage on SW (2)
–0.3
40
PD
Continuous Power Dissipation
See Thermal Information
TJ
Operating Junction Temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
VI
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
(1)
±1000
Corner pins (1, 3, 6, and 4)
±1000
Other pins
±1000
Machine model
(1)
UNIT
V
±100
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
MIN
VI
Input voltage range, VIN
VO
Output voltage range
L
Inductor (1)
fdim
CIN
NOM
MAX
UNIT
3
18
VIN
38
V
10
22
μH
PWM dimming frequency
5
100
kHz
Input capacitor
1
CO
Output capacitor
1
10
μF
TA
Operating ambient temperature
–40
105
°C
TJ
Operating junction temperature
–40
125
°C
(1)
V
μF
These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in
other applications but should be fully tested by the user.
6.4 Thermal Information
TPS61165-Q1
THERMAL METRIC
(1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
210.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.8
°C/W
RθJB
Junction-to-board thermal resistance
56.7
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
50.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 105°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range, VIN
IQ
Operating quiescent current into VIN
Device PWM switching no load
3
ISD
Shutdown current
CRTL=GND, VIN = 4.2 V
UVLO
Undervoltage lockout threshold
VIN falling
Vhys
Undervoltage lockout hysterisis
2.2
18
V
2.3
mA
2
μA
2.5
70
V
mV
ENABLE AND REFERENCE CONTROL
V(CTRLh)
CTRL logic high voltage
VIN = 3 V to 18 V
V(CTRLl)
CTRL logic low voltage
VIN = 3 V to 18 V
1.2
V
R(CTRL)
CTRL pulldown resistor
toff
CTRL pulse width to shutdown
CTRL high to low
2.5
ms
tes_det
EasyScale detection time (1)
CTRL pin low
260
μs
tes_delay
EasyScale detection delay
100
μs
tes_win
EasyScale detection window time
1
ms
0.4
400
Measured from CTRL high
800
1600
V
kΩ
VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation voltage
V(REF_PWM)
Voltage feedback regulation voltage under
brightness control
IFB
Voltage feedback input bias current
VFB = 200 mV
fS
Oscillator frequency
Dmax
Maximum duty cycle
(1)
4
196
200
204
VFB = 50 mV
47
50
53
VFB = 20 mV
17
20
23
2
VFB = 100 mV
1
1.2
90%
93%
1.5
mV
mV
μA
MHz
To select EasyScale mode, the CTRL pin must be low for more than tes_det during tes_win.
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Electrical Characteristics (continued)
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 105°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tmin_on
Minimum on pulse width
40
ns
Isink
Comp pin sink current
100
μA
Isource
Comp pin source current
100
μA
Gea
Error amplifier transconductance
Rea
Error amplifier output resistance
fea
Error amplifier crossover frequency
240
320
400
umho
6
MΩ
5 pF connected to COMP
500
kHz
VIN = 3.6 V
0.3
POWER SWITCH
RDS(ON)
ILN_NFET
N-channel MOSFET on-resistance
VIN = 3 V
N-channel leakage current
VSW = 35 V, TA = 25°C
ILIM
N-Channel MOSFET current limit
D = Dmax
ILIM_Start
Start-up current limit
D = Dmax
tHalf_LIM
Time step for half current limit
Vovp
Open LED protection threshold
Measured on the SW pin
Open LED protection threshold on FB
Measured on the FB pin, percentage of
Vref, Vref = 200 mV and 20 mV
0.6
Ω
0.7
1
μA
1.44
A
OC and OLP
V(FB_OVP)
tREF
0.96
0.7
A
5
37
Each step measured as number of
cycles of the 1.2-MHz clock
VREF ramp up time
38
ms
39
V
50%
VREF filter time constant
tstep
1.2
180
μs
213
μs
160
°C
15
°C
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
Thysteresis
Thermal shutdown threshold hysteresis
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
EasyScale TIMING
μs
tstart
Start time of program stream
2
tEOS
End time of program stream
2
360
μs
tH_LB
High time low bit
Logic 0
2
180
μs
tL_LB
Low time low bit
Logic 0
2 × tH_LB
360
μs
tH_HB
High time high bit
Logic 1
2 × tL_HB
360
μs
tL_HB
Low time high bit
Logic 1
2
180
μs
VACKNL
Acknowledge output voltage low
Open drain, Rpullup =15 kΩ to VIN
0.4
V
2
μs
512
μs
tvalACKN
Acknowledge valid time
See
(1)
tACKN
Duration of acknowledge condition
See
(1)
(1)
Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open-drain output, line must be pulled high
by the host with resistor load.
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6.7 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Efficiency
3 LEDs (VOUT = 12 V); VIN = 3, 5, 8.5 V; L = 10 μH
Figure 1
Efficiency
6 LEDs (VOUT = 24 V); VIN = 5, 8.5, 12V; L = 10 μH
Figure 2
Current limit
TA = 25°C
Figure 3
Current limit
Figure 4
EasyScale step
Figure 5
PWM dimming linearity
VIN = 3.6 V; PWM Freq = 10 kHz and 32 kHz
Figure 6
Output ripple at PWM dimming
3 LEDs; VIN = 5 V; ILOAD = 350 mA; PWM = 32 kHz
Figure 7
Switching waveform
3 LEDs; VIN = 5 V; ILOAD = 3500 mA; L = 10 μH
Figure 8
Start-up
3 LEDs; VIN = 5 V; ILOAD = 350 mA; L = 10 μH
Figure 9
Open LED protection
8 LEDs; VIN = 3.6 V; ILOAD = 20 mA
Figure 10
100
100
VIN = 8.5 V
3 LEDs ( VOUT = 12 V )
VIN = 12 V
6 LEDs ( VOUT = 24 V )
90
90
VIN = 8.5 V
VIN = 5 V
VIN = 5 V
VIN = 3 V
Efficiency - %
Efficiency - %
80
70
80
70
60
60
50
50
40
40
0
50
100
150
200
Output Current - mA
250
0
300
1500
1500
1400
1400
Switch Current Limit - mA
Switch Current Limit - A
1600
1300
1200
1100
1000
900
250
300
1300
1200
1100
1000
900
30
40
50
60
Duty Cycle - %
70
80
Figure 3. Switch Current Limit vs Duty Cycle
6
100
150
200
Output Current - mA
Figure 2. Efficiency vs Output Current
Figure 1. Efficiency vs Output Current
1600
800
20
50
90
800
-40
-20
0
20
40
60
80
Temperature - °C
100
120
140
Figure 4. Switch Current Limit vs Temperature
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200
200
PWM 10 kHz, 32 kHz
180
160
160
FB Voltage - mV
FB Voltage - mV
140
120
100
80
120
80
60
40
40
20
0
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Easy Scale Step
Figure 5. FB Voltage vs EasyScale Step
PWM 5 V/div
0
20
40
60
PWM Duty Cycle - %
80
100
Figure 6. FB Voltage vs PWM Duty Cycle
SW 5 V/div
VOUT 50 mV/div AC
VOUT 200 mV/div AC
IL 500 mA/div
ILED 200 mA/div
t - 20 ms/div
t - 400 ns/div
Figure 7. Output Ripple at PWM Dimming
CTRL 5 V/div
Figure 8. Switching Waveform
OPEN LED 5 V/div
FB 200 mV/div
VOUT 5 V/div
VOUT 10 V/div
IL 200 mA/div
COMP 500 mV/div
IL 500 mA/div
t - 100 ms/div
t - 2 ms/div
Figure 9. Start-Up
Figure 10. Open LED Protection
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7 Detailed Description
7.1 Overview
The TPS61165-Q1 device is a high-efficiency, high-output voltage boost converter in small package size. The
device is ideal for driving white LEDs in series. The serial LED connection provides even illumination by sourcing
the same output current through all LEDs, eliminating the need for expensive factory calibration. The device
integrates 40-V and 1.2-A switch FET and operates in pulse width modulation (PWM) with 1.2-MHz fixed
switching frequency. For operation see Functional Block Diagram. The duty cycle of the converter is set by the
error amplifier output and the current signal applied to the PWM control comparator. The control architecture is
based on traditional current-mode control; therefore, slope compensation is added to the current signal to allow
stable operation for duty cycles larger than 40%. The feedback loop regulates the FB pin to a low reference
voltage (200 mV typical), reducing the power dissipation in the current sense resistor.
7.2 Functional Block Diagram
D1
6
Rset
C2
3
FB
L1
SW
Reference
Control
Error
Amplifer
OLP
Vin
1
COMP
5
C1
PWM Control
C3
2
CTRL
Soft
Start-up
Ramp
Generator
+
Current
Sensor
Oscillator
GND
4
7.3 Feature Description
7.3.1 Soft Start-Up
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled, the voltage at FB pin ramps up to the reference voltage in 32 steps; each step takes 213 μs. This
ensures that the output voltage rises slowly to reduce the input current. Additionally, for the first 5 ms after the
COMP voltage ramps, the current limit of the switch is set to half of the normal current limit specification. During
this period, the input current is kept below 700 mA (typical). These two features ensure smooth start-up and
minimize the inrush current. See the start-up waveform of a typical example (Figure 9).
8
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Feature Description (continued)
7.3.2 Open LED Protection
Open LED protection circuitry prevents IC damage as the result of white LED disconnection. The TPS61165-Q1
device monitors the voltage at the SW pin and FB pin during each switching cycle. The circuitry turns off the
switch FET and shuts down the IC when both of the following conditions persist for 8 switching clock cycles: (1)
the SW voltage exceeds the VOVP threshold and (2) the FB voltage is less than half of regulation voltage. As a
result, the output voltage falls to the level of the input supply. The device remains in shutdown mode until it is
enabled by toggling the CTRL pin. The product of the number of external series LEDs and each LED's maximum
forward voltage plus the 200-mV reference voltage does not exceed the 38-V minimum OVP threshold or (NLEDS
X VLED(MAX) + 200 mV ≤ 38 V.
7.3.3 Undervoltage Lockout
An undervoltage lockout prevents operation of the device at input voltages below 2.2 V (typical). When the input
voltage is below the undervoltage threshold, the device shuts down and the internal switch FET is turned off. If
the input voltage rises by undervoltage lockout hysteresis, the IC restarts.
7.3.4 Thermal Shutdown
An internal thermal shutdown turns off the device when the typical junction temperature exceeds 160°C. The
device is released from shutdown automatically when the junction temperature decreases by 15°C.
7.4 Device Functional Modes
7.4.1 Shutdown
The TPS61165-Q1 enters shutdown mode when the CTRL voltage is logic low for more than 2.5 ms. During
shutdown, the input supply current for the device is less than 1 μA (maximum). Although the internal FET does
not switch in shutdown, there is still a DC current path between the input and the LEDs through the inductor and
Schottky diode. The minimum forward voltage of the LED array must exceed the maximum input voltage to
ensure that the LEDs remain off in shutdown.
7.5 Programming
7.5.1 Current Program
The FB voltage is regulated by a low 0.2-V reference voltage. The LED current is programmed externally using a
current-sense resistor in series with the LED string. The value of the RSET is calculated using Equation 1.
V
ILED = FB
RSET
where
•
•
•
ILED = output current of LEDs
VFB = regulated voltage of FB
RSET = current sense resistor
(1)
The output current tolerance depends on the FB accuracy and the current sensor resistor accuracy.
7.5.2 LED Brightness Dimming Mode Selection
The CTRL pin is used for the control input for both dimming modes, PWM dimming and the 1 wire dimming. The
dimming mode for the TPS61165-Q1 device is selected each time the device is enabled. The default dimming
mode is PWM dimming. To enter 1-wire mode, the following digital pattern on the CTRL pin must be recognized
by the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61165-Q1 device, and to start the 1-wire detection window.
2. After the EasyScale detection delay (tes_delay, 100 μs) expires, drive CTRL low for more than the EasyScale
detection time (tes_detect, 260 μs).
3. The CTRL pin must be low for more than EasyScale detection time before the EasyScale detection window
(tes_win, 1 ms) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
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Programming (continued)
The IC immediately enters the 1-wire mode once the above three conditions are met. the EasyScale
communication can start before the detection window expires. Once the dimming mode is programmed, it cannot
be changed without another start-up. This means the IC needs to be shut down by pulling the CTRL low for 2.5
ms and restarts. See the Dimming Mode Detection and Soft Start (see Figure 11) for a graphical explanation.
Insert battery
PWM signal
high
CTRL
low
PWM
mode
Startup
delay
FB ramp
Shutdown delay
200mV x duty cycle
FB
t
Insert battery
Enter ES mode
Enter ES mode
Timing window
Programming
code
Programming code
high
CTRL
low
ES detect time
ES
mode
ES detect delay
Shutdown
delay
IC
Shutdown
Programmed value
(if not programmed, 200mV default )
50mV
Startup delay
FB
FB ramp
FB ramp
Startup delay
50mV
Figure 11. Dimming Mode Detection and Soft Start PWM Brightness Dimming
7.5.3 PWM Brightness Dimming
When the CTRL pin is constantly high, the FB voltage is regulated to 200 mV typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage; therefore, it achieves LED brightness dimming. The
relationship between the duty cycle and FB voltage is given by Equation 2:
VFB = Duty ´ 200 mV
where
•
•
Duty = duty cycle of the PWM signal
200 mV = internal reference voltage
(2)
As shown in Figure 12, the IC chops up the internal 200-mV reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for
brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This
eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and
duty cycle of PWM control. Unlike other methods which filters the PWM signal for analog dimming, TPS61165Q1 device's regulation voltage is independent of the PWM logic voltage level which often has large variations.
For optimum performance, use the PWM dimming frequency in the range of 5 kHz to 100 kHz. The requirement
of minimum dimming frequency comes from the EasyScale detection delay and detection time specification in the
dimming mode selection. Because the CTRL pin is logic only pin, adding an external RC filter applied to the pin
does not work.
To use lower PWM dimming, add external RC network connected to the FB pin as shown in the additional typical
application, .
10
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Programming (continued)
VBG
200 mV
CTRL
Error
Amplifier
COMP
FB
Figure 12. Block Diagram of Programmable FB Voltage Using PWM Signal
7.5.4 Digital 1 Wire Brightness Dimming
The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can save
the processor power and battery life as it does not require a PWM signal all the time, and the processor can
enter idle mode if available.
The TPS61165-Q1 device adopts the EasyScale protocol for the digital dimming, which can program the FB
voltage to any of the 32 steps with single command. The step increment increases with the voltage to produce
pseudo logarithmic curve for the brightness step. See Table 2 for the FB pin voltage steps. The default step is
full scale when the device is first enabled (VFB = 200 mV). The programmed reference voltage is stored in an
internal register and will not be changed by pulling CTRL low for 2.5 ms and then re-enabling the IC by taking
CTRL high. A power reset clears the register value and reset it to default.
7.5.5 EasyScale: 1 Wire Digital Dimming
EasyScale is a simple but flexible 1-pin interface to configure the FB voltage. The interface is based on a masterslave structure, where the master is typically a microcontroller or application processor. Figure 13 and Table 3
give an overview of the protocol. The protocol consists of a device specific address byte and a data byte. The
device specific address byte is fixed to 72 hex. The data byte consists of 5 bits for information, 2 address bits,
and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The Acknowledge
condition is applied only if the protocol was received correctly. The advantage of EasyScale compared with other
1-pin interfaces is that its bit detection is in a large extent independent from the bit transmission rate. It can
automatically detect bit rates between 1.7 kbps and up to 160 kbps.
Table 2. Selectable FB Voltage
FB voltage
(mV)
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
5
0
0
0
0
1
2
8
0
0
0
1
0
3
11
0
0
0
1
1
4
14
0
0
1
0
0
5
17
0
0
1
0
1
6
20
0
0
1
1
0
7
23
0
0
1
1
1
8
26
0
1
0
0
0
9
29
0
1
0
0
1
10
32
0
1
0
1
0
11
35
0
1
0
1
1
12
38
0
1
1
0
0
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Table 2. Selectable FB Voltage (continued)
FB voltage
(mV)
D4
D3
D2
D1
D0
13
44
0
1
1
0
1
14
50
0
1
1
1
0
15
56
0
1
1
1
1
16
62
1
0
0
0
0
17
68
1
0
0
0
1
18
74
1
0
0
1
0
19
80
1
0
0
1
1
20
86
1
0
1
0
0
21
92
1
0
1
0
1
22
98
1
0
1
1
0
23
104
1
0
1
1
1
24
116
1
1
0
0
0
25
128
1
1
0
0
1
26
140
1
1
0
1
0
27
152
1
1
0
1
1
28
164
1
1
1
0
0
29
176
1
1
1
0
1
30
188
1
1
1
1
0
31
200
1
1
1
1
1
DATA IN
DATABYTE
Device Address
Start
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1
0
1
1
1
0
0
1
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 13. EasyScale Protocol Overview
Table 3. EasyScale Bit Description
BYTE
Device
Address
Byte
72 hex
12
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
7
DA7
0 MSB device address
6
DA6
1
5
DA5
1
4
DA4
3
DA3
2
DA2
0
1
DA1
1
0
DA0
0 LSB device address
IN
DESCRIPTION
1
0
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Table 3. EasyScale Bit Description (continued)
BYTE
Data byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
7 (MSB)
RFA
6
A1
0 Address bit 1
5
A0
0 Address bit 0
4
D4
3
D3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
DESCRIPTION
Request for acknowledge. If high, acknowledge is applied by device
Data bit 4
IN
ACK
Data bit 3
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open-drain output, Line needs to be pulled high by the host with a pullup
resistor. This feature can only be used if the master has an open-drain output
stage. In case of a push-pull output stage Acknowledge condition may not be
requested!
OUT
EasyScale Timing, without acknowledge RFA = 0
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
D0
1
RFA
0
TEOS
TEOS
EasyScale Timing, with acknowledge RFA = 1
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
TEOS
RFA
1
D0
1
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
tLow
Low Bit
(Logic 0)
t High
tLOW
t valACK
ACKN
t ACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
tHigh
High Bit
(Logic 1)
Figure 14. EasyScale— Bit Coding
All bits are transmitted MSB first and LSB last. Figure 14 shows the protocol without acknowledge request (Bit
RFA = 0), Figure 14 with acknowledge (Bit RFA = 1) request. Before both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 μs) before
the bit transmission starts with the falling edge. If the CTRL pin is already at a high level, no start condition is
needed before the device address byte. The transmission of each byte is closed with an End of Stream condition
for at least tEOS (2 μs).
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The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH. It can be simplified to:
High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 14.
Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 14.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 μs
maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal
ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
The acknowledge condition may only be requested if the master device has an open-drain output. For a pushpull output stage, the use a series resistor in the CRTL line to limit the current to 500 μA is recommended to for
such cases as:
• Accidentally requested acknowledge.
• Protect the internal ACKN-MOSFET.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS61165-Q1 device drives 6 high-brightness LEDs; the LED current is set at 350 mA. A 12-V Zener diode
is used to clamp the input voltage, which makes the TPS61165-Q1 device suitable for car battery supply
applications.
8.2 Typical Application
L1
10 mH
Vbat
C1
4.7 mF
C4
1 mF
R1
1 kW
D2
12 V
ON/OFF
DIMMING
CONTROL
D1
C2
1 mF
TPS61165-Q1
VIN
SW
CTRL
FB
COMP
GND
350 mA
C3
220 nF
Rset
0.57 W
L1: TOKO #A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM188R61E105K
C4: Murata GRM188R61E105K
D1: ONsemi MBR0540T1
D2: Onsemi 1SMB5927BT3G
R1: Vishay CRCW08051K00FKEA
LED: OSRAM LW-W5SM
Or Equivalent
Figure 15. Drive Six High-Brightness LEDs
For assistance in selecting the proper values, the detailed external PWM dimming network for the specific
application, see SLVA471 and/or SLVC366.
8.2.1 Design Requirements
Table 4 lists the input parameters for this design example.
Table 4. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Brightness control
PWM Dimming
Input voltage
12 V
Output current
350 mA
LED loads
6 LEDs
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8.2.2 Detailed Design Procedures
8.2.2.1 Maximum Output Current
The overcurrent limit in a boost converter limits the maximum input current and thus maximum input power for a
given input voltage. Maximum output power is less than maximum input power due to power conversion losses.
Therefore, the current limit setting, input voltage, output voltage and efficiency can all change maximum current
output. The current limit clamps the peak inductor current; therefore, the ripple must be subtracted to derive
maximum DC current. The ripple current is a function of switching frequency, inductor value and duty cycle. Use
Equation 3 and Equation 4 consider of all the above factors for maximum output current calculation.
1
IP =
é
1
1 ù
+
)ú
êL ´ Fs ´ (
Vout + Vf - Vin Vin û
ë
where
•
•
•
•
•
Ip = inductor peak to peak ripple
L = inductor value
Vf = Schottky diode forward voltage
Fs = switching frequency
Vout = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across
LEDs.
I out _ max =
(3)
Vin ´ (I lim - I p / 2) ´h
Vout
where
•
•
•
Iout_max = Maximum output current of the boost converter
Ilim = over current limit
η = efficiency
(4)
For instance, when VIN is 3 V, 8 LEDs output equivalent to VOUT of 26 V, the inductor is 22 μH, the Schottky
forward voltage is 0.2 V; and then the maximum output current is 110 mA in typical condition. When VIN is 5 V,
10 LEDs output equivalent to VOUT of 32 V, the inductor is 22 μH, the Schottky forward voltage is 0.2 V; and
then the maximum output current is 150 mA in typical condition.
8.2.2.2 Inductor Selection
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not
enough.
The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary
peak current without saturating, according to half of the peak-to-peak ripple current given by Equation 3, pause
the inductor DC current given by:
Vout ´ I out
I in _ DC =
Vin ´ h
(5)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0 A value depending on how the inductor vendor defines
saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM when the
inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s
maximum output current, causes large input voltage ripple and reduces efficiency. Large inductance value
provides much more output current and higher conversion efficiency. For these reasons, a 10 μH to 22 μH
inductor value range is recommended. A 22 μH inductor optimized the efficiency for most application while
maintaining low inductor peak to peak ripple. Table 5 lists the recommended inductor for the TPS61165-Q1
device. When recommending inductor value, the factory has considered –40% and +20% tolerance from its
nominal value.
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TPS61165-Q1 device has built-in slope compensation to avoid subharmonic oscillation associated with current
mode control. If the inductor value is lower than 10 μH, the slope compensation may not be adequate, and the
loop can be unstable. Therefore, customers need to verify the inductor in their application if it is different from the
recommended values.
Table 5. Recommended Inductors for TPS61165-Q1
PART NUMBER
L
(μH)
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
SIZE
(L × W × H mm)
VENDOR
TOKO
A915_Y-100M
10
90
1.3
5.2 × 5.2 × 3
VLCF5020T-100M1R1-1
10
237
1.1
5×5×2
TDK
CDRH4D22/HP
10
144
1.2
5 × 5 × 2.4
Sumida
LQH43PN100MR0
10
247
0.84
4.5 × 3.2 × 2
Murata
8.2.2.3 Schottky Diode Selection
The high switching frequency of the TPS61165-Q1 device demands a high-speed rectification for optimum
efficiency. Ensure that the diode’s average and peak current rating exceeds the average output current and peak
inductor current. In addition, the reverse breakdown voltage of the diode must exceed the open LED protection
voltage. The ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for the TPS61165-Q1 device.
8.2.2.4 Compensation Capacitor Selection
The compensation capacitor C3 (see Functional Block Diagram), connected from COMP pin to GND, is used to
stabilize the feedback loop of the TPS61165-Q1 device. A 220-nF ceramic capacitor is suitable for most
applications.
8.2.2.5 Input and Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This
ripple voltage is related to the capacitance of the capacitor and its equivalent series resistance (ESR). Assuming
a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated using
Equation 6.
(Vout - Vin ) Iout
Cout =
Vout ´ Fs ´ Vripple
where
•
Vripple = peak-to-peak output ripple
(6)
The additional output ripple component caused by ESR is calculated using Equation 7
Vripple _ ESR = Iout ´ RESR
(7)
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
Care must be taken when evaluating a ceramic capacitors derating under DC bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have a self resonant frequencies in the range of the
switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore,
leave the margin on the voltage rating to ensure adequate capacitance at the required output voltage.
The capacitor in the range of 1 μF to 4.7 μF is recommended for input side. The output requires a capacitor in
the range of 1 μF to 10 μF. The output capacitor affects the loop stability of the boost regulator. If the output
capacitor is below the range, the boost regulator can potentially become unstable.
The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
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8.2.3 Application Curves
Figure 16. Start-Up Waveform
Figure 17. 100 kHz PWM Dimming Waveform Under 50%
Duty Cycle
8.3 Do's and Don'ts
There is a known issue with the TPS61165-Q1 device when using the EasyScale interface to increase the
feedback voltage. When VFB is increased from 0 mV to any value more than 0 mV, some ICs do not properly
soft-start during this transition and the voltage on their SW pin overshoots. If the overshoot exceeds the absolute
maximum voltage rating on the SW pin, the IC is damaged.
With VFB set below 10 mV through EasyScale, the parasitic offsets on the input pins of the internal
transconductance amplifier determine the value of output of the amplifier. IC process variations are causing the
offset to be larger and in the opposite polarity than expected. If the amplifier’s output is already high before a
transition from VFB = 0 mV to any other voltage, then the modulator turns on full, bypassing soft start, and
causes the SW pin and output voltage to overshoot.
To avoid this issue do not use EasyScale to change the feedback voltage from 0 mV, effectively disabling the
device, to any other voltage. One alternative is to start with VFB = 10 mV and go to a higher voltage. Another
alternative is to disable the IC by taking the CTRL pin low for 2.5 ms and then re-enter EasyScale to force a soft
start from VFB = 0 mV to the default 200 mV.
9 Power Supply Recommendations
The TPS61165-Q1 device requires a single supply input voltage. This voltage can range from 3 V to 18 V and be
able to supply enough current for a given application.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, especially those high frequency and high current ones, layout is an important
design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems.
To reduce switching losses, the SW pin rise and fall times are made as short as possible. To prevent radiation of
high frequency resonance problems, proper layout of the high frequency switching path is essential. Minimize the
length and area of all traces connected to the SW pin and always use a ground plane under the switching
regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky diode, and output
capacitor, contains high current rising and falling in nanosecond and should be kept as short as possible. The
input capacitor needs not only to be close to the VIN pin, but also to the GND pin to reduce the IC supply ripple.
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10.2 Layout Example
D1
C1
VIN
Rsense
1 VIN
CTRL
2 CRTL
FB 6
COMP 5
C3
L1
Minimize
the area of
this trace
LED-
3 SW
D2
GND 4
C2
LED+
Figure 18. Recommended Layout Example
10.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61165-Q1 device. Calculate the maximum allowable dissipation,
PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is
determined using Equation 8:
125°C - TA
PD(max) =
RqJA
where
•
•
TA is the maximum ambient temperature for the application
RθJA is the thermal resistance junction-to-ambient given in Thermal Information Table
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• How to Use Analog Dimming With the TPS6116x, SLVA471
• Design Tool for Analog Dimming using a PWM Signal, SLVC366
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
EasyScale, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61165TDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 105
SBM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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