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TPS61170
SLVS789D – NOVEMBER 2007 – REVISED DECEMBER 2014
TPS61170 1.2-A High-Voltage Boost Converter in 2-mm x 2-mm2 QFN Package
1 Features
3 Description
•
•
•
•
•
The TPS61170 is a monolithic, high-voltage switching
regulator with integrated 1.2-A, 40-V power MOSFET.
The device can be configured in several standard
switching-regulator topologies, including boost and
SEPIC. The device has a wide input-voltage range to
support applications with input voltage from multicell
batteries or regulated 5-V, 12-V power rails.
1
•
•
•
•
•
3-V to 18-V Input Voltage Range
High Output Voltage: Up to 38 V
1.2-A Integrated Switch
1.2-MHz Fixed Switching Frequency
12 V at 300 mA and 24 V at 150 mA From 5-V
Input (Typical)
Up to 93% Efficiency
On-The-Fly Output Voltage Reprogramming
Skip-Switching Cycle for Output Regulation at
Light Load
Built-in Soft Start
6-Pin, 2-mm × 2-mm QFN Package
The TPS61170 operates at a 1.2-MHz switching
frequency, allowing the use of low-profile inductors
and low-value ceramic input and output capacitors.
External loop compensation components give the
user flexibility to optimize loop compensation and
transient response. The device has built-in protection
features, such as pulse-by-pulse overcurrent limit,
soft start, and thermal shutdown.
The FB pin regulates to a reference voltage of 1.229
V. The reference voltage can be lowered using a 1wire digital interface (Easyscale™ protocol) through
the CTRL pin. Alternatively, a pulse width-modulation
(PWM) signal can be applied to the CTRL pin. The
duty cycle of the signal reduces the feedback
reference voltage proportionally.
2 Applications
•
•
•
5-V to 12-V and 24-V, 12-V to 24-V Boost
Converter
Buck Boost Regulation Using SEPIC Topology
ADSL Modems
The TPS61170 is available in a 6-pin 2-mm × 2-mm
QFN package, allowing a compact power-supply
solution.
Device Information(1)
PART NUMBER
TPS61170
PACKAGE
VSON (6)
BODY SIZE (NOM)
2.00 mm x 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Typical Application Schematic
L1
10 mH
VIN 5 V
C1
4.7 mF
D1
C2
4.7 mF
TPS 61170
VIN
R3
4.99 kW
VOUT 12 V/ 300 mA
SW
CTRL
FB
COMP
GND
C3
10 nF
R1
87.6 kW
R2
10 kW
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
*R3, C3: Compensation RC network
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61170
SLVS789D – NOVEMBER 2007 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Application Schematic.............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
7.1
7.2
7.3
7.4
7.5
7.6
3
3
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 9
8.1
8.2
8.3
8.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
8.5 Programming........................................................... 12
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
9.3 System Examples ................................................... 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
11.3 Thermal Considerations ........................................ 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
5 Revision History
Changes from Revision C (April 2011) to Revision D
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision B (November 2009) to Revision C
•
2
Page
Page
Changed C1 part number in Figure 18, Figure 19, and Figure 20 from "GRM188RA475K " to "GRM21BR61E475K" ...... 21
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SLVS789D – NOVEMBER 2007 – REVISED DECEMBER 2014
6 Pin Configuration and Functions
QFN Package
6 Pins
Top View
FB
COMP
VIN
Thermal
Pad
CTRL
GND
SW
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COMP
2
O
Output of the transconductance error amplifier. Connect an external RC network to this pin to compensate
the regulator.
CTRL
5
I
Control pin of the boost regulator. CTRL is a multifunctional pin which can be used to enable the device
and control the feedback voltage with a PWM signal or for digital communications.
FB
1
I
Feedback pin for current. Connect to the center tap of a resistor divider to program the output voltage.
GND
3
O
Ground
SW
4
I
This is the switching node of the IC. Connect SW to the switched side of the inductor.
The thermal pad should be soldered to the analog ground plane to avoid thermal issue. If possible, use
thermal vias to connect to ground plane for ideal power dissipation.
Thermal Pad
VIN
6
I
The input supply pin for the IC. Connect VIN to a supply voltage from 3 V to 18 V.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
–0.3
20
V
Voltages on CTRL (2)
–0.3
20
V
Voltage on FB and COMP (2)
–0.3
3
V
Supply Voltages on VIN
VI
(1)
(2)
(2)
–0.3
40
V
TJ
Operating Junction Temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
Voltage on SW
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±750
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.
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7.3 Recommended Operating Conditions
MIN
TYP
MAX
UNIT
VI
Input voltage range, VIN
VO
Output voltage range
L
Inductor (1)
CI
Input capacitor
1
CO
Output capacitor (1)
1
10
μF
TA
Operating ambient temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
3
18
VIN
38
V
V
10
22
μH
μF
These values are recommended values that have been successfully tested in several applications. Other values may be acceptable in
other applications but should be fully tested by the user.
7.4 Thermal Information
TPS61170
THERMAL METRIC (1)
DRV
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
66.5
RθJC(top)
Junction-to-case (top) thermal resistance
85.6
RθJB
Junction-to-board thermal resistance
36.0
ψJT
Junction-to-top characterization parameter
1.7
ψJB
Junction-to-board characterization parameter
36.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
7.1
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range, VIN
IQ
Operating quiescent current into VIN
Device PWM switching no load
3.0
ISD
Shutdown current
CRTL=GND, VIN = 4.2 V
UVLO
Under-voltage lockout threshold
VIN falling
Vhys
Under-voltage lockout Hysteresis
2.2
18
V
2.3
mA
1
μA
2.5
V
70
mV
ENABLE AND REFERENCE CONTROL
V(CTRLh)
CTRL logic high voltage
VIN = 3 V to 18 V
V(CTRL)
CTRL logic low voltage
VIN = 3 V to 18 V
1.2
V
R(CTRL)
CTRL pulldown resistor
toff
CTRL pulse width to shutdown
CTRL high to low
2.5
ms
tes_det
Easy Scale detection time (1)
CTRL pin low
260
μs
tes_delay
Easy Scale detection delay
tes_win
Easy Scale detection window time
0.4
400
800
V
1600
kΩ
100
μs
1
ms
VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation voltage
V(REF_PWM)
Voltage feedback regulation voltage under
reprogram
VFB = 492 mV
IFB
Voltage feedback input bias current
VFB = 1.229 V
fS
Oscillator frequency
Dmax
Maximum duty cycle
tmin_on
Minimum on pulse width
40
ns
Isink
Comp pin sink current
100
μA
Isource
Comp pin source current
100
μA
Gea
Error amplifier transconductance
Rea
Error amplifier output resistance
5 pF connected to COMP
6
MΩ
fea
Error amplifier crossover frequency
5 pF connected to COMP
500
kHz
VIN = 3.6 V
0.3
VFB = 100 mV
1.204
1.229
1.254
477
492
507
1.0
1.2
90%
93%
240
320
V
mV
200
nA
1.5
MHz
400
μmho
POWER SWITCH
0.6
Ω
RDS(on)
N-channel MOSFET on-resistance
ILN_NFET
N-channel leakage current
VSW = 35 V, TA = 25°C
ILIM
N-Channel MOSFET current limit
D = Dmax
ILIM_Start
Start up current limit
D = Dmax
tHalf_LIM
Time step for half current limit
5
ms
tREF
Vref filter time constant
180
μs
tstep
VREF ramp up time
213
μs
VIN = 3.0 V
0.7
1
μA
1.44
A
OC and SS
(1)
0.96
1.2
0.7
A
EasyScale communication is allowed immediately after the CTRL pin has been low for more than tes_det. To select EasyScale mode, the
CTRL pin must be low for more than tes_det the end of tes_win.
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Electrical Characteristics (continued)
VIN = 3.6 V, CTRL = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EasyScale TIMING
μs
tstart
Start time of program stream
2
tEOS
End time of program stream
2
360
μs
tH_LB
High time low bit
Logic 0
2
180
μs
tL_LB
Low time low bit
Logic 0
2 × tH_LB
360
μs
tH_HB
High time high bit
Logic 1
2 × tL_HB
360
μs
tL_HB
Low time high bit
Logic 1
2
180
μs
VACKNL
Acknowledge output voltage low
Open drain, Rpullup =15 kΩ to Vin
0.4
V
tvalACKN
Acknowledge valid time
See
(2)
2
μs
tACKN
Duration of acknowledge condition
See
(2)
512
μs
THERMAL SHUTDOWN
Tshutdown
Thermal shutdown threshold
Thysteresis
Thermal shutdown threshold hysteresis
(2)
160
°C
15
°C
Acknowledge condition active 0, this condition will only be applied if the RFA bit is set. Open drain output, line needs to be pulled high
by the host with resistor load.
7.6 Typical Characteristics
Table 1. Table Of Graphs
Circuit of Figure 1, L = TOKO A915_Y-100M, D1 = ONsemi MBR0540T1, unless otherwise noted.
FIGURE
Efficiency
VIN = 5 V; VOUT = 12 V, 18 V, 24 V, 30 V
Figure 1
Efficiency
VIN = 5 V, 8.5 V, 12 V; VOUT = 24 V
Figure 2
Output voltage accuracy
ILOAD= 100 mA
Figure 3
Switch current limit
TA = 25°C
Figure 4
Switch current limit
Figure 5
Error amplifier transconductance
Figure 6
EasyScale step
Figure 7
PWM switching operation
VIN = 5 V; VOUT = 12 V; ILOAD= 250 mA
Figure 14
Load transient response
VIN = 5 V; VOUT = 12 V; ILOAD= 50 mA to 150 mA
Figure 15
Start-up
VIN = 5 V; VOUT = 12 V; ILOAD= 250 mA
Figure 16
Skip-cycle switching
VIN = 9 V ; VOUT = 12 V, ILOAD= 100 μA
Figure 17
6
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100
100
VIN = 5 V
VIN = 12 V
VOUT = 24 V
VOUT = 12 V
90
90
VOUT = 30 V
VOUT = 24 V
VOUT = 18 V
VIN = 5 V
80
Efficiency - %
80
Efficiency - %
VIN = 8.5 V
70
70
60
60
50
50
40
40
0
50
100
150
200
Output Current - mA
250
0
300
50
250
300
Figure 2. Efficiency vs Output Current
Figure 1. Efficiency vs Output Current
1600
11.96
ILOAD = 100 mA
1500
1400
Switch Current Limit - A
11.94
VO - Output Voltage - V
100
150
200
Output Current - mA
TA = 25°C
TA = 85°C
11.92
TA = -40°C
11.90
1300
1200
1100
1000
900
800
20
11.88
3
4
5
6
7
8
VI - Input Voltage - V
9
10
11
Switch Current Limit - mA
1500
1400
1300
1200
1100
1000
900
800
-40
-20
0
20
40
60
80
Temperature - °C
100
120
Figure 5. Switch Current Limit vs Temperature
40
50
60
Duty Cycle - %
70
80
90
Figure 4. Switch Current Limit vs Duty Cycle
1600
140
Error Amplifier Transconductance - mhos
Figure 3. Output Voltage vs Input Voltage
30
500
400
300
200
100
0
-40
-20
0
20
40
60
80
Temperature - °C
100
120
140
Figure 6. Error Amplifier Transconductance vs Temperature
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1.4
1.2
FB Voltage - V
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Easy Scale Step
Figure 7. FB Voltage vs EasyScale Step
8
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8 Detailed Description
8.1 Overview
The TPS61170 integrates a 40-V low side FET for providing output voltages up to 38 V. The device regulates the
output with current mode PWM (pulse width modulation) control. The switching frequency of the PWM is fixed at
1.2 MHz (typical). The PWM control circuitry turns on the switch at the beginning of each switching cycle. The
input voltage is applied across the inductor and stores the energy as the inductor current ramps up. During this
portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current
rises to the threshold set by the error amplifier output, the power switch turns off and the external Schottky diode
is forward biased. The inductor transfers stored energy to replenish the output capacitor and supply the load
current. This operation repeats each switching cycle. As shown in the block diagram, the duty cycle of the
converter is determined by the PWM control comparator which compares the error amplifier output and the
current signal.
A ramp signal from the oscillator is added to the current ramp. This slope compensation ramp is necessary to
avoid subharmonic oscillations that are intrinsic to current mode control at duty cycles higher than 50%. The
feedback loop regulates the FB pin to a reference voltage through an error amplifier. The output of the error
amplifier must be connected to the COMP pin. An external RC compensation network must be connected to the
COMP pin to optimize the feedback loop for stability and transient response.
8.2 Functional Block Diagram
C2
D1
R1
1
R2
4
L1
FB
SW
Band Gap
Error
Amplifer
Vin
6
COMP
2
C1
PWM Control
R3
C3
5
CTRL
Soft
Start-up
Ramp
Generator
+
Current
Sensor
Oscillator
GND
3
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8.3 Feature Description
8.3.1 Soft Start-Up
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled by a logic high signal on the CTRL pin, the FB pin reference voltage ramps up in 32 steps, with each
step taking 213 μs. This ensures that the output voltage rises slowly to reduce inrush current. Additionally, for the
first 5 msec after the COMP voltage ramps, the current limit of the PWM switch is set to half of the normal
current limit specification or below 700 mA (typical). See the start-up waveform for a typical example, Figure 16.
8.3.2 Overcurrent Protection
TPS61170 has a cycle-by-cycle overcurrent limit feature that turns off the power switch once the inductor current
reaches the overcurrent limit. The PWM circuitry resets itself at the beginning of the next switch cycle. During an
over-current event, this results in a decrease of output voltage that is directly proportional to load current. The
current limit threshold as well as input voltage, output voltage, switching frequency and inductor value determine
the maximum available output current. Larger inductance values typically increase the current output capability
because of the reduced current ripple. See Maximum Output Current for the output current calculation.
8.3.3 Undervoltage Lockout (UVLO)
An undervoltage lockout prevents mis-operation of the device at input voltages below 2.2 V (typical). When the
input voltage is below the undervoltage threshold, the device remains off and the internal switch FET is turned
off. The undervoltage lockout threshold is set below minimum operating voltage of 3V to avoid any transient VIN
dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 3
V, the device attempts operation, but the specifications are not ensured.
8.3.4 Thermal Shutdown
An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded.
The IC restarts when the junction temperature drops by 15°C.
8.3.5 Enable and Shutdown
The TPS61170 enters shutdown when the CTRL voltage is less than 0.4 V for more than 2.5 ms. In shutdown,
the input supply current for the device is less than 1 μA (maximum). The CTRL pin has an internal 800-kΩ
(typical) pulldown resistor to disable the device when the pin is left unconnected.
8.4 Device Functional Modes
8.4.1 Feedback Reference Program Mode Selection
The CTRL pin is used for changing the FB pin reference voltage on-the-fly. There are two methods to program
the reference voltage, PWM signal and 1-wire interface (EasyScale). The programming mode is selected each
time the device is enabled. The default mode is to use the duty cycle of the PWM signal on the CTRL pin to
modulate the reference voltage. To enter the 1-wire interface mode, the following digital pattern on the CTRL pin
must be recognized by the IC every time the IC starts from the shutdown mode.
1. Pull CTRL pin high to enable the TPS61170 and to start the 1 wire mode detection window.
2. After the EasyScale detection delay (tes_delay, 100 μsec) expires, drive CTRL low for more than the EasyScale
detection time (tes_detect, 260 μsec).
3. The CTRL pin has to be low for more than EasyScale detection time before the EasyScale detection window
(tes_win, 1msec) expires. EasyScale detection window starts from the first CTRL pin low to high transition.
The IC immediately enters the 1-wire mode once the previous three conditions are met. The EasyScale
communication can start before the detection window expires. Once the mode is programmed, it can not be
changed without another start up. In other words, the IC must be shutdown by pulling the CTRL low for 2.5 ms
and restarted in order to exit EasyScale Mode. See Figure 8 for a graphical explanation.
10
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Device Functional Modes (continued)
Insert battery
PWM signal
high
CTRL
low
PWM
mode
Startup
delay
FB ramp
Shutdown delay
200mV x duty cycle
FB
t
Insert battery
Enter ES mode
Enter ES mode
Timing window
Programming
code
Programming code
high
CTRL
low
ES detect time
ES
mode
ES detect delay
Shutdown
delay
IC
Shutdown
Programmed value
(if not programmed, 200mV default )
FB
FB ramp
FB ramp
50mV
Startup delay
Startup delay
50mV
Figure 8. Mode Detection of Feedback Reference Program
8.4.2 PWM Program Mode
When the CTRL pin is constantly high, the FB voltage is regulated to 1.229V typically. However, the CTRL pin
allows a PWM signal to lower this regulation voltage. The relationship between the duty cycle and FB voltage is
given in Equation 1:
VFB = Duty × 1.229 V
where
•
•
Duty = duty cycle of the PWM signal
1.229 V = internal reference voltage
(1)
As shown in Figure 9, the IC chops up the internal 1.229 V reference voltage at the duty cycle of the PWM
signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the
error amplifier as the reference voltage for the FB pin regulation. The regulation voltage is independent of the
PWM logic voltage level which often has large variations.
For optimum performance, use the PWM mode in the range of 5 kHz to 100 kHz. The requirement of minimum
frequency comes from the EasyScale detection delay and detection time specification for the mode selection.
The device can mistakenly enter 1 wire mode if the PWM signal frequency is less than 5 kHz. Because there is
an internal fixed ON-time error of 40 nS, the FB voltage absolute value will be different than expected when the
PWM frequency is above 100 kHz. For example, the additional duty cycle of 3.2% due to the ON-time error
increases the FB voltage when using an 800 kHz PWM signal. A compromise between PWM frequency and FB
voltage accuracy extends the frequency range. Adding an external RC filter to the pin serves no purpose.
VBG
1.229 V
CTRL
Error
Amplifier
FB
Figure 9. Block Diagram of Programmable FB Voltage Using PWM Signal
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Device Functional Modes (continued)
8.4.3 1-Wire Program Mode
The CTRL pin features a simple digital interface to control the feedback reference voltage. The 1-wire mode can
save the processor power and battery life as it does not require a PWM signal all the time, and the processor can
enter idle mode if available.
The TPS61170 adopts the EasyScale protocol, which can program the FB voltage to any of the 32 steps with
single command. See Table 2 for the FB pin voltage steps. The programmed reference voltage is stored in an
internal register. The default value is full scale when the device is first enabled (VFB = 1.229 V). A power reset
clears the register value and reset it to default.
8.5 Programming
8.5.1 EasyScale
EasyScale is a simple but very flexible one pin interface to configure the FB voltage. The interface is based on a
master-slave structure, where the master is typically a microcontroller or application processor. Figure 10 and
Table 2 give an overview of the protocol. The protocol consists of a device specific address byte and a data byte.
The device specific address byte is fixed to 72 hex. The data byte consists of five bits for information, two
address bits, and the RFA bit. The RFA bit set to high indicates the Request for Acknowledge condition. The
Acknowledge condition is only applied if the protocol was received correctly. The advantage of EasyScale
compared with other on pin interfaces is that its bit detection is in a large extent independent from the bit
transmission rate. It can automatically detect bit rates between 1.7 kBit/sec and up to 160 kBit/sec.
Table 2. Selectable FB Voltage
12
FB
VOLTAGE
(mV)
D4
D3
D2
D1
D0
0
0.000
0
0
0
0
0
1
0.031
0
0
0
0
1
2
0.049
0
0
0
1
0
3
0.068
0
0
0
1
1
4
0.086
0
0
1
0
0
5
0.104
0
0
1
0
1
6
0.123
0
0
1
1
0
7
0.141
0
0
1
1
1
8
0.160
0
1
0
0
0
9
0.178
0
1
0
0
1
10
0.197
0
1
0
1
0
11
0.215
0
1
0
1
1
12
0.234
0
1
1
0
0
13
0.270
0
1
1
0
1
14
0.307
0
1
1
1
0
15
0.344
0
1
1
1
1
16
0.381
1
0
0
0
0
17
0.418
1
0
0
0
1
18
0.455
1
0
0
1
0
19
0.492
1
0
0
1
1
20
0.528
1
0
1
0
0
21
0.565
1
0
1
0
1
22
0.602
1
0
1
1
0
23
0.639
1
0
1
1
1
24
0.713
1
1
0
0
0
25
0.787
1
1
0
0
1
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Table 2. Selectable FB Voltage (continued)
FB
VOLTAGE
(mV)
D4
D3
D2
D1
D0
26
0.860
1
1
0
1
0
27
0.934
1
1
0
1
1
28
1.008
1
1
1
0
0
29
1.082
1
1
1
0
1
30
1.155
1
1
1
1
0
31
1.229
1
1
1
1
1
DATA IN
DATABYTE
Device Address
Start
Start DA7 DA6 DA5 DA4 DA3 DA2 DA1
0
1
1
1
0
0
1
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 10. EasyScale Protocol Overview
Table 3. EasyScale Bit Description
BYTE
Device
Address
Byte
72 hex
Data byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
7
DA7
0 MSB device address
6
DA6
1
5
DA5
1
4
DA4
3
DA3
2
DA2
0
1
DA1
1
IN
DESCRIPTION
1
0
0
DA0
0 LSB device address
7 (MSB)
RFA
Request for acknowledge. If high, acknowledge is applied by device
6
A1
0 Address bit 1
5
A0
0 Address bit 0
4
D4
3
D3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
IN
OUT
Data bit 4
Data bit 3
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open-drain output, Line must be pulled high by the host with a pullup resistor.
This feature can only be used if the master has an open-drain output stage. In case
of a push pull output stage Acknowledge condition may not be requested!
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Easy Scale Timing, without acknowledge RFA = 0
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
D0
1
RFA
0
TEOS
TEOS
Easy Scale Timing, with acknowledge RFA = 1
t Start
DATA IN
t Start
Address Byte
DATA Byte
Static High
Static High
DA7
0
DA0
0
TEOS
RFA
1
D0
1
t valACK
Controller needs to
Pull up Data Line via a
resistor to detect ACKN
DATA OUT
tLow
t High
Low Bit
(Logic 0)
tLOW
ACKN
t ACKN
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pulldown
tHigh
High Bit
(Logic 1)
Figure 11. EasyScale— Bit Coding
All bits are transmitted MSB first and LSB last. Figure 11 shows the protocol without acknowledge request (Bit
RFA = 0), Figure 11 with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address byte and data
byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least tstart (2 μs) before
the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no start condition is
needed prior to the device address byte. The transmission of each byte is closed with an End of Stream
condition for at least tEOS (2 μs).
The bit detection is based on a Logic Detection scheme, where the criterion is the relation between tLOW and
tHIGH. It can be simplified to:
High Bit: tHIGH > tLOW, but with tHIGH at least 2x tLOW, see Figure 11.
Low Bit: tHIGH < tLOW, but with tLOW at least 2x tHIGH, see Figure 11.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHIGH and tLOW, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit.
• The transmitted device address matches with the device address of the device.
• 16 bits is received correctly.
14
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If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is 512 μs
maximum then the Acknowledge condition is valid after an internal delay time tvalACK. This means that the internal
ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected. The master
controller keeps the line low in this period. The master device can detect the acknowledge condition with its input
by releasing the CTRL pin after tvalACK and read back a logic 0. The CTRL pin can be used again after the
acknowledge condition ends.
Note that the acknowledge condition may only be requested if the master device has an open-drain output. For
the push-pull output stage, the use a series resistor in the CRTL line to limit the current to 500 μA is
recommended for such cases as:
• an accidentally requested acknowledge, or
• to protect the internal ACKN-MOSFET.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6170 is designed for output voltages up to 38 V with a switch peak current limit of 0.96-A minimum. The
device, which operates in peak current mode PWM control, is externally compensated for maximum flexibility and
stability. The switching frequency is fixed at 1.2 MHz, and the input voltage range is 3.0 to 18 V. The following
section provides a step-by-step design approach for configuring the TPS61170 as a voltage regulating boost
converter.
9.2 Typical Application
L1
10 mH
VIN 5 V
C1
4.7 mF
D1
C2
4.7 mF
TPS 61170
VIN
VOUT 12 V/ 300 mA
SW
R1
87.6 kW
ON/ OFF
Program FB
R3
10 kW
CTRL
FB
COMP
GND
C3
680pF
R2
10 kW
L1: TOKO#A915_Y-100M
C1: Murata GRM188R61A475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
Figure 12. 5-V to 12-V DCDC Power Conversion With Programmable Feedback Reference Voltage
9.2.1 Design Requirements
Table 4. TPS61170 12-V Output Design Requirements
PARAMETERS
VALUES
Input Voltage
5.0V ± 20%
Output Voltage
12V
Output Current
300mA
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9.2.2 Detailed Design Procedure
9.2.2.1 Program Output Voltage
VOUT
R1
TPS61170
FB
R2
Figure 13. Program Output Voltage
To program the output voltage, select the values of R1 and R2 (see Figure 13) according to Equation 2.
æ R1
ö
+ 1÷
è R2
ø
Vout = 1.229 V x ç
æ Vout
ö
- 1÷
è 1.229 V
ø
R1 = R2 x ç
(2)
Considering the leakage current through the resistor divider and noise decoupling to FB pin, an optimum value
for R2 is around 10k. The output voltage tolerance depends on the accuracy of the reference voltage and the
tolerance of R1 and R2.
9.2.2.2 Maximum Output Current
The overcurrent limit in a boost converter limits the maximum input current, and thus the maximum input power
for a given input voltage. The maximum output power is less than the maximum input power due to power
conversion losses. Therefore, the current-limit setting, input voltage, output voltage and efficiency can all affect
the maximum output current. The current limit clamps the peak inductor current; therefore, the ripple must be
subtracted to derive the maximum DC current. The ripple current is a function of the switching frequency,
inductor value and duty cycle. The following equations take into account of all the above factors for maximum
output current calculation.
1
IP =
é
1
1 ù
+
)ú
êL ´ Fs ´ (
V
+
V
V
V
out
f
in
in û
ë
(3)
where:
IP = inductor peak to peak ripple current
L = inductor value
Vf = Schottky diode forward voltage
Fs = switching frequency
Vout = output voltage
I
Vin ´ (Ilim - P ) ´ h
2
Iout _ max =
Vout
(4)
where:
Iout_max = Maximum output current of the boost converter
Ilim = overcurrent limit
η = efficiency
For instance, when Vin is 5 V, Vout is 12 V, the inductor is 10 μH, the Schottky forward voltage is 0.2 V; and then
the maximum output current is 300 mA in a typical operation.
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9.2.2.3 Switch Duty Cycle
The maximum switch duty cycle (D) of the TPS61170 is 90% (min). The duty cycle of a boost converter under
continuous conduction mode (CCM) is given by:
D + Vout * Vin
Vout
(5)
For a 5 V to 12 V application, the duty cycle is 58.3%, and for a 5 V to 24 V application, the duty cycle is 79.2%.
The duty cycle must be lower than the maximum specification of 90% in the application; otherwise, the output
voltage cannot be regulated.
Once the PWM switch is turned on, the TPS61170 has minimum ON pulse width. This sets the limit of the
minimum duty cycle. When operating at low duty cycles, the TPS61170 enters pulse-skipping mode. In this
mode, the device turns the power switch off for several switching cycles to prevent the output voltage from rising
above regulation. This operation typically occurs in light load condition when the PWM operates in discontinuous
mode. See the Figure 17.
9.2.2.4 Inductor Selection
The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These
factors make it the most important component in power regulator design. There are three important inductor
specifications: inductor value, DC resistance (DCR) and saturation current. Considering inductor value alone is
not enough.
The inductance value of the inductor determines its ripple current. It is recommended that the peak-to-peak ripple
current given by Equation 3 be set to 30–40% of the DC current. Inductance values shown in Recommended
Operating Conditions are recommended for most applications. Inductor DC current can be calculated as
I in_DC + Vout Iout
Vin h
(6)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation
level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor vendor defines
saturation current. Using an inductor with a smaller inductance value forces discontinuous PWM where the
inductor current ramps down to zero before the end of each switching cycle. This reduces the boost converter’s
maximum output current, causes large input voltage ripple and reduces efficiency. In general, inductors with
large inductance and low DCR values provide much more output current and higher conversion efficiency.
Inductors with smaller inductance values can give better load transient response. For these reasons, a 10 μH to
22 μH inductance value range is recommended. Table 5 lists some recommended inductors for the TPS61170.
TPS61170 has built-in slope compensation to avoid subharmonic oscillation associated with current mode
control. If the inductor value is lower than 10 μH, the slope compensation may not be adequate, and the loop can
become unstable. Therefore, customers need to verify operation in their application if the inductor is different
from the recommended values.
Table 5. Recommended Inductors for TPS61170
PART NUMBER
L
(μH)
DCR MAX
(mΩ)
SATURATION CURRENT
(A)
SIZE
(L × W × H mm)
VENDOR
TOKO
A915_Y-100M
10
90
1.3
5.2 × 5.2 × 3.0
VLCF5020T-100M1R1-1
10
237
1.1
5 × 5×2.0
TDK
CDRH4D22/HP
10
144
1.2
5 × 5 × 2.4
Sumida
LQH43PN100MR0
10
247
0.84
4.5 × 3.2 × 2.0
Murata
9.2.2.5 Schottky Diode Selection
The high switching frequency of the TPS61170 demands a high-speed rectifying switch for optimum efficiency.
Ensure that the average and peak current rating of the diode exceeds the average output current and peak
inductor current. In addition, the reverse breakdown voltage of the diode must exceed the switch FET rating
voltage of 40 V. So, the ONSemi MBR0540 is recommended for TPS61170. However, Schottky diodes with
lower rated voltages can be used for lower output voltages to save the solution size and cost. For example, a
converter providing a 12-V output with 20-V diode is a good choice.
18
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9.2.2.6 Compensation Capacitor Selection
The TPS61170 has an external compensation, COMP pin, which allows the loop response to be optimized for
each application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic
capacitor C3 are connected to COMP pin to provide a pole and a zero. This pole and zero, along with the
inherent pole of a current mode control boost converter, determine the close loop frequency response. This is
important to a converter stability and transient response.
The following equations summarize the poles, zeros and DC gain of a TPS61170 boost converter with ceramic
output capacitor (C2), as shown in the block diagram. They include the dominant pole (fP1), the output pole (fP2)
of a boost converter, the right-half-plane zero (fRHPZ) of a boost converter, the zero (fZ) generated by R3 and C3,
and the DC gain (A).
1
fP1 =
2p x 6 MW x C3
fP2 =
2p x Rout x C2
fRHPZ =
fZ =
A=
(7)
2
Rout
2p x L
(8)
æ Vin ö
÷
è Vout ø
2
x ç
(9)
1
2p x R3 x C3
1.229
Vout
(10)
x Gea x 6 MW x
Vin
1
x Rout x
Vout x Rsense
2
(11)
where Rout is the load resistance, Gea is the error amplifier transconductance located in Electrical
Characteristics, Rsense (100mΩ typical) is a sense resistor in the current control loop. These equations helps
generate a simple bode plot for TPS61170 loop analysis.
Increasing R3 or reducing C3 increases the close loop bandwidth which improves the transient response.
Adjusting R3 and C3 in opposite directions increase the phase, and help loop stability. For many of the
applications, the recommended value of 10k and 680pF makes an ideal compromise between transient response
and loop stability. To optimize the compensation, use C3 in the range of 100pF to 10nF, and R3 of 10k. See the
TI application report SLVA319 for thorough analysis and description of the boost converter small signal model
and compensation design.
9.2.2.7 Input and Output Capacitor Selection
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. The
ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated using
Equation 12.
C out +
ǒV out * V inǓ Iout
Vout
Fs
V ripple
(12)
Where, Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is calculated
using:
Vripple_ESR = Iout × RESR
(13)
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have a resonant frequencies in the range of the switching
frequency. So, the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can lose as much as 50% of its capacitance at its rated voltage. Therefore,
choose a ceramic capacitor with a voltage rating at least 1.5X its expected dc bias voltage.
The capacitor in the range of 1 μF to 4.7 μF is recommended for input side. The output typically requires a
capacitor in the range of 1 μF to 10 μF. The output capacitor affects the loop stability of the boost regulator. If the
output capacitor is below the range, the boost regulator can potentially become unstable.
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The popular vendors for high value ceramic capacitors are:
TDK (http://www.component.tdk.com/components.php)
Murata (http://www.murata.com/cap/index.html)
9.2.3 Application Curves
SW 5 V/div
VOUT 200 mV/div AC
VOUT 100 mV/div AC
IL 500 mA/div
ILOAD 100 mA/div
t - 400 ns/div
t - 40 ms/div
Figure 14. PWM Switching Operation
CTRL 5 V/div
Figure 15. Load Transient Response
SW 5 V/div
VOUT 5 V/div
VOUT 20 mV/div AC
COMP 500 mV/div
IL 500 mA/div
IL 50 mA/div
t - 400 ns/div
t - 1 ms/div
Figure 17. Skip-Cycle Switching
Figure 16. Start-Up
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9.3 System Examples
L1
10 mH
VIN 12 V
C1
4.7 mF
D1
C2
4.7 mF
TPS 61170
R3
10 kW
VOUT 24 V/ 300 mA
VIN
SW
CTRL
FB
COMP
GND
R1
185.1 kW
R2
10 kW
C3
680 pF
L1: TOKO#A915_Y-100M
C1: Murata GRM21BR61E475K
C2: Murata GRM32ER71H475K
D1: ONsemi MBR0540T1
Figure 18. 12-V to 24-V DCDC Power Conversion
C4
1 mF
L1
10 mH
VIN 9 V to 15 V
C1
4.7 mF
L2
10 mH
TPS 61170
VIN
ON /OFF
DIMMING
CONTROL
D1
C2
4.7 mF
VOUT 12 V/ 300 mA
R1
87.6 kW
SW
CTRL
FB
COMP
GND
R2
10 kW
C3
220 nF
L1: TOKO#A915_Y-100M
C1: Murata GRM21BR61E475K
C2: Murata GRM21BR61E475K
D1: ONsemi MBR0540T1
*L1, L2 can be replaced by 1:1 transformer
Figure 19. 12-V SEPIC (Buck-Boost) Converter
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System Examples (continued)
L1
22 mH
VIN 4.5 V to 15 V
C2
1 mF
D2
C1
4.7 mF
VO
48 V/60 mA
D1
C4
4.7 mF
TPS61170
D3
VIN
SW
CTRL
FB
COMP
GND
R1
380 kW
C3
4.7 mF
10k
10 nF
R2
10 kW
L1: TOKO B1000AS-220M
C1: Murata GRM21BR61E475K
C2: Murata GRM21BR71H105K
C3, C4: Murata GRM32ER71H475K
D1 – D3: B140
Vo = 1.23 x (R1+R2)/ R2;
Figure 20. 48-V Phantom Power Application Circuit
C3
1 mF
L1
33 mH
VIN 3.3 V
D2
C2
1 mF
D3
D4
C1
4.7 mF
SW
CTRL
FB
VO1
-48 V/30 mA
C4
4.7 mF
VO2
-24 V/40 mA
R1
23.7 kW
C5
4.7 mF
TPS61170
VIN
D1
VIN
1 kW
1 kW
10 kW
COMP
GND
Q1
10 nF
L1: TOKO B992AS-330M
C1: Murata GRM188R61A475K
C2, C3: Murata GRM21BR71H105K
C4, C5: Murata GRM32ER71H475K
D1 – D4: B140
Q1: BCM62B
Q2: MMBT3904TT1
R2
1.24 kW
Q2
Vo2 = 1.23 x (R1/ R2); Vo1 = 2Vo2
Figure 21. –24-V / –48-V Buck-Boost Converter From 3.3-V Input
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System Examples (continued)
L1
15 mH pins 1-10
VIN 12 V
1
C1
4.7 mF
10 2
9 3
8
39 pF
VO
48 V/75 mA
D1
C2
4.7 mF
TPS61170
5.6 W
VIN
SW
CTRL
FB
R1
100 kW
Vo = 1.23 x (R1+R2)/ R2;
60 kW
COMP
R2
2.61 kW
GND
10 nF
L1: EPCOS N97
C1: Murata GRM21BR61E475K
C2: Murata GRM32ER71H475K
D1: MURA160
Figure 22. 12-V to 48-V Flyback Topology
10 Power Supply Recommendations
The TPS61170 is designed to operate from an input voltage supply range from 3.0 V to 18 V. The power supply
to the TPS61170 needs to have a current rating according to the supply voltage, output voltage, and output
current of the TPS61170 device.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, especially those switching at high frequencies and/or providing high currents,
layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well
as noise problems. To maximize efficiency, switch rise and fall times should be as short as possible. To reduce
radiation of high frequency switching noise and harmonics, proper layout of the high frequency switching path is
essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane
under the switching regulator to minimize interplane coupling. The high current path including the switch,
Schottky diode, and output capacitor, contains nanosecond rise and fall times and should be kept as short as
possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to
reduce the IC supply ripple. Figure 23 shows a sample layout
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11.2 Layout Example
C1
R2
Vin
R1
Vin
FB
L1
R3
CTRL
COMP
CTRL
GND
SW
C3
GND
Place enough
VIAs around
thermal pad to
enhance thermal
performance
C2
Minimize the
area of this
trace
Vout
Note: minimize the trace
area at FB pin and
COMP pin
Figure 23. PCB Layout Recommendation
11.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the TPS61170. Calculate the maximum allowable dissipation, PD(max),
and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined
using Equation 14:
P D(max) +
125°C * T A
RqJA
(14)
where, TA is the maximum ambient temperature for the application. RθJA is the thermal resistance junction-toambient given in the Thermal Information table.
The TPS61170 comes in a thermally enhanced QFN package. This package includes a thermal pad that
improves the thermal capabilities of the package. The RθJA of the QFN package greatly depends on the PCB
layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using
thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB
Attachment application report (SLUA271).
24
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Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TPS61170
TPS61170
www.ti.com
SLVS789D – NOVEMBER 2007 – REVISED DECEMBER 2014
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• QFN/SON PCB Attachment Application Report, SLUA271
• Ultralow Power 100-mA Low-Dropout Linear Regulator, SLVS319
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2007–2014, Texas Instruments Incorporated
Product Folder Links: TPS61170
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61170DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BZS
TPS61170DRVRG4
ACTIVE
WSON
DRV
6
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BZS
TPS61170DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BZS
TPS61170DRVTG4
ACTIVE
WSON
DRV
6
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BZS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
