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TPS61178
SLVSDA7E – FEBRUARY 2017 – REVISED AUGUST 2019
TPS61178x 20-V, 10-A Fully-Integrated Synchronous Boost with Load Disconnect Control
1 Features
3 Description
•
•
•
•
•
The TPS61178x family is a 20-V synchronous Boost
converter with the gate driver built-in for load
disconnect. The TPS61178x integrates two low onresistance power FETs: A 16-mΩ switching FET and
a 16-mΩ rectifier FET.
1
•
•
•
•
•
•
•
•
•
Input Voltage Range: 2.7 V to 20 V
Output Voltage Range: 4.5 V to 20 V
Programmable Switch Peak Current: up to 10 A
Two 16-mΩ FETs Integrated
Efficiency up to 96%: VIN = 7.2 V, VOUT = 16 V,
IOUT = 2 A
Adjustable Switching Frequency: up to 2.2 MHz
External Clock Synchronization:
200 kHz to 2.2 MHz
Gate Driver for Load Disconnect
Hiccup Short Protection
Over Voltage Protection
Auto PFM Operation - TPS61178
Forced PWM Mode - TPS611781
3.0-mm x 3.5-mm 13-pin VQFN Hotrod Package
Create a Custom Design Using the TPS61178
With the WEBENCH® Power Designer
The TPS61178x uses the fixed frequency peak
current mode control with the slope compensation
integrated. At the light load, the TPS61178 enters into
the auto PFM mode while TPS611781 is in the forced
PWM mode.
The TPS61178x could isolate the output from input
side when shutdown. Once the output is shorted, it
enters into the hiccup mode to lower the thermal
stress and can recover automatically after the short
releases. Additionally, the TPS61178x also has OVP
and thermal protection to avoid the fault operation.
The TPS61178x is in a 3.0-mm x 3.5-mm 13-pin
VQFN package with enhanced thermal dissipation.
Device Information(1)
PART NUMBER
2 Applications
TPS61178
•
•
•
•
•
TPS611781
Portable Speaker
Source Driver of LCD Display
Supply for the Power Amplifier
Supply for the Motor Driver
USB Type-C Power Delivery
PACKAGE
BODY SIZE (NOM)
QFN (13)
3.00 mm × 3.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application
L
VIN
CIN
VIN
BST
VCC
CBST
CVCC
SW
VOUT
EN
OFF
VOUT2
P-FET (option)
ON
RGATE
RFreq
CGATE
RUP
COUT1
FREQ /
SYNC
COUT2
DISDRV
RDOWN
FB
ILIMIT
RLIMIT
COMP
AGND
PGND
Cc
Cp
RC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61178
SLVSDA7E – FEBRUARY 2017 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ...............................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 15
9
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
9.3 System Examples .................................................. 28
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2019) to Revision E
Page
•
Restored hyperlink cross reference at the Thermal Information table footnote. .................................................................... 4
•
Deleted right-hand column (A/B/S) in the Electrical Characteristics table. ............................................................................ 5
Changes from Revision C (March 2018) to Revision D
•
Corrected term 1–DR to 1–D in Equation 21 ....................................................................................................................... 23
Changes from Revision B (September 2017) to Revision C
•
Page
Changed graphs for Figure 1 through Figure 6 to include 3-A load ...................................................................................... 7
Changes from Original (February 2017) to Revision A
2
Page
Changed Equation 21 .......................................................................................................................................................... 23
Changes from Revision A (April 2017) to Revision B
•
Page
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SLVSDA7E – FEBRUARY 2017 – REVISED AUGUST 2019
5 Device Comparison Table
Part Number
Operation Mode at Light Load
TPS61178
Auto PFM
TPS611781
Forced PWM
6 Pin Configuration and Functions
(RNW)
(13-Pin QFN)
Top View
8
7
6
FB
VCC
10
4
COMP
EN
11
3
ILIMIT
VIN
12
2
AGND
BST
13
1
FREQ/SYNC
PGND
5
SW
9
VOUT
DISDRV
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NUMBER
FREQ / SYNC
1
I
The switching frequency is programmed by a resistor between this pin and the AGND. The
internal oscillator can be synchronized by an external clock connecting into this pin. This pin
can not be float in application.
AGND
2
-
Analog signal ground of the IC. Connect the AGND to PGND via a single point on the printed
circuit board.
ILIMIT
3
I
Programming the switching peak current limit by a resistor between this pin and AGND.
COMP
4
O
Output of the internal error amplifier. The loop compensation network should be connected
between this pin and AGND.
FB
5
I
Output voltage feedback, a resistor divider connecting to this pin sets the output voltage.
PGND
6
PWR
Power ground
SW
7
PWR
The switching node pin of the converter. It is connected to the drain of the internal low-side
power FET and the source of the internal high-side power FET.
VOUT
8
PWR
Boost converter output
DISDRV
9
O
A gate drive output for the external disconnect FET. Connect the DISDRV pin to the gate of
the external FET. Leave it floating if not using the load disconnect function.
VCC
10
O
Output of the internal regulator. A ceramic capacitor of more than 1.0 µF is required between
this pin and ground
EN
11
I
Enable logic input. Logic high level enables the device and low level shutdown the device.
VIN
12
I
IC power supply input.
BST
13
O
Power supply for high-side FET gate driver. A capacitor must be connected between this pin
and the SW pin
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SLVSDA7E – FEBRUARY 2017 – REVISED AUGUST 2019
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
BST
–0.3
SW + 7
V
VIN, SW, VOUT, DISCRG, EN
–0.3
23
V
VCC, FB, COMP, FREQ / SYNC, ILIMIT
–0.3
7
V
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
Voltage range at terminals
(1)
(2)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic discharge
(1)
(1)
(2)
(3)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (3)
±750
UNIT
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Outputvoltage
L
Effective inductance range
RFB
Feedback resistance (low side)
TJ
Operating junction temperature
NOM
2.7
20
4.5
0.47
MAX
20
3.3
–40
UNIT
V
V
µH
200
kΩ
125
°C
7.4 Thermal Information
TPS61178
THERMAL METRIC
(1)
RNR (QFN Package)
UNIT
12 PINS
RθJA
Junction-to-ambient thermal resistance
60.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
28.6
°C/W
RθJB
Junction-to-board thermal resistance
14.5
°C/W
ψJT
Junction-to-top characterization parameter
0.4
°C/W
ψJB
Junction-to-board characterization parameter
14.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report..
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SLVSDA7E – FEBRUARY 2017 – REVISED AUGUST 2019
7.5 Electrical Characteristics
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
UNIT
20
V
VIN rising
2.6
2.7
V
VIN falling
2.2
2.3
POWER SUPPLY
VIN
Input voltage range
VIN_UVLO
Input voltage under voltage lockout
(UVLO) threshold
VIN_HYS
VIN UVLO hysteresis
VCC
VCC regulation voltage
ICC = 5mA, VIN = 8V
6
V
VCC_UVLO
VCC UVLO threshold
VCC falling
2.1
V
Quiescent current into VIN pin
IC enabled, no load, no ext. FET
VIN = 6 V, VOUT = 20 V, VFB = 1.3
V, TJ up to 85 ⁰C
1.5
3
µA
Quiescent current into VIN pin
IC enabled, no load, no ext. FET
VIN = 20 V, VOUT = 20 V, VFB = 1.3
V,TJ up to 85 ⁰C
270
320
µA
Quiescent current into VOUT pin
IC enabled, no load, no ext. FET
VIN = 6 V, VFB = 1.3 V, VOUT = 20 V,
TJ up to 85 ⁰C
250
300
µA
Quiescent current into VOUT pin
IC enabled, no load, no ext. FET
VIN = 20 V, VOUT = 20 V, VFB = 1.3
V, TJ up to 85 ⁰C
5
12
µA
IC disabled, VIN = 6 V,
–40 °C ≤ TJ ≤ 85°C
1
3.5
µA
IC disabled, VIN = 20 V,
–40 °C ≤ TJ ≤ 85°C
3
6
µA
0.1
6.5
µA
20
V
21
21.5
V
IQ
(TPS61178)
ISD
Shutdown current into VIN pin
2.7
400
mV
Reverse leakage current into SW
IC disabled, VIN = VOUT = SW = 20
V
–40 °C ≤ TJ ≤ 85°C
VOUT
Output voltage range
Freq = 500kHz
VOVP
Output over-voltage protection
threshold
VIN = 8 V, VOUT rising
High-side MOSFET on resistance
VCC = 6 V
16
25
mΩ
Low-side MOSFET on resistance
VCC = 6 V
16
25
mΩ
Power stage trans-conductance
(peak current ratio with comp
voltage)
VCC = 6 V
12
ILIM_SW
TPS61178
RLIMIT = 80.6 kΩ
6.4
8
9.4
A
ILIM_SW
TPS611781
RLIMIT = 80.6 kΩ
5.7
7.4
8.7
A
ILIM_SHORT
TPS61178 short current limit
ILS_LKG
OUTPUT
VOLTAGE
4.5
20.5
POWER
SWITCHES
RDS(on)
Gm
A/V
CURRENT
LIMIT
20
A
VOLTAGE
REFERNCE
VREF
Reference Voltage at FB pin
IFB_LKG
Leakage current into FB pin
PWM mode
1.180
PFM mode
1.198
1.210
101%
10
V
VREF
60
nA
1.2
V
EN / SYNC LOGIC
VEN_H
EN Logic high threshold
VEN_L
EN Logic Low threshold
0.4
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Electrical Characteristics (continued)
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
REN
EN pulldown resistor
VSYNC_H
SYNC clock high threshold
VSYNC_L
SYNC clock low threshold
TYP
MAX
800
UNIT
kΩ
1.2
0.4
V
V
ERROR
AMPLIFIER
VCOMPH
COMP output high voltage
High threshold, VFB = VREF - 200 mV
1.9
V
VCOMPL
COMP output low voltage
Low threshold, VFB = VREF + 200
mV
1.25
V
GmEA
Error amplifier trans conductance
VCOMP = 1.5 V
195
uS
ISINK
Comp pin sink current
VFB = VREF + 200 mV, VCOMP = 1.5
V
20
uA
ISOURCE
Comp pin source current
VFB = VREF –200 mV, VCOMP = 1.5 V
20
uA
7.6 Timing Requirements
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
UNIT
CURRENT
LIMIT
tSHORT_ON
Short active time
tSHORT_OFF
Time for Auto retry protection off
time
4
ms
90
ms
SOFT
START
tSTARTUP
Startup time
tPRE_CHARG Pre charge time
VIN = 8 V, VOUT = 16 V
Pre charge time
3.2
1.8
2.6
ms
3.4
ms
PROTECTION
tSD_R
Thermal shutdown rising threshold
TJ rising
150
°C
tSD_F
Thermal shutdown falling threshold
TJ falling
130
°C
7.7 Switching Characteristics
over operating free-air temperature range, VIN = 2.7 V to 14 V and VOUT = 16 V, VCC = 6 V, RLIMIT = 80.6 kΩ. Typical values
are at TJ = 25°C, (unless otherwise noted)
MIN
TYP
MAX
Unit
RFREQ = 342 kΩ
400
500
600
kHz
RFREQ = 842 kΩ
160
200
240
kHz
1900
SWITCHING FREQUENCY / SYNC
fSW
Switching frequency
2200
2500
kHz
tON_min
Minimum on time
105
135
ns
tOFF_min
Minimum off time
140
180
ns
fSYNC_MIN
Min Frequency using external clock
190
200
210
kHz
fSYNC_MAX
Max Frequency using external clock
2090
2200
2310
kHz
RFREQ = 75 kΩ
GATE DRIVER
FOR LOAD DISCONNECT
IGH_SINK
6
External PFET drive current
55
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
7.8 Typical Characteristics
60
50
40
30
10
0.0001
0.001
VOUT = 16 V
0.01
Load (A)
0.1
1
L = 3.3 µH
50
40
30
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
20
60
10
0.0001
3
Auto PFM
Figure 1. Efficiency vs. Output Current
0.01
Load (A)
0.1
1
L = 3.3 µH
3
Auto PFM
Figure 2. Efficiency vs. Output Current
90
90
80
80
70
70
Efficiency (%)
100
Efficiency (%)
0.001
VOUT = 16 V
100
60
50
40
60
50
40
30
30
20
20
VIN = 3 V
VIN = 3.6 V
VIN = 4.2 V
10
0
0.001
0.01
VOUT = 14 V
0.1
Load (A)
0
0.0001
1
D046
L = 1.8 µH
16.4
80
16.3
70
16.2
Output Voltage (V)
16.5
90
60
50
40
30
0
0.0001
VOUT = 16 V
0.01
Load (A)
0.1
L = 3.3 µH
0.1
L = 3.3 µH
1
3
Forced PWM
1
16.1
16
15.9
15.8
15.7
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
0.001
0.01
Load (A)
Figure 4. Efficiency vs. Output Current
100
10
0.001
VOUT = 16 V
Auto PFM
20
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
10
Figure 3. Efficiency vs. Output Current
Efficiency (%)
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
20
VIN = 6 V
VIN = 7.2 V
VIN = 8.4 V
15.6
3
Forced PWM
15.5
0.0001
0.001
VOUT = 16 V
Figure 5. Efficiency vs. Output Current
0.01
Load (A)
0.1
L = 3.3 µH
1
Auto PFM
Figure 6. Output Voltage vs. Load
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Typical Characteristics (continued)
16.5
310
16.4
290
Quiescent Current (PA)
16.3
Output Voltage (V)
16.2
16.1
16
15.9
15.8
15.7
VIN = 10.8 V
VIN = 12 V
VIN = 13.2 V
15.6
15.5
0.0001
270
250
230
210
190
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
170
150
0.001
0.01
Load (A)
VOUT = 16 V
0.1
1
L = 3.3 µH
3
8
10
14
16
Input Voltage (V)
18
20
D010
Auto PFM
Figure 7. Output Voltage vs. Load
Figure 8. Quiescent Current vs VIN
16
5
Auto PFM
TJ = -40 qC
TJ = 25 qC
TJ = 85 qC
4.5
4
14
12
3.5
Current Limit (A)
Shutdown Current (uA)
12
3
2.5
2
10
8
6
1.5
4
1
2
0.5
0
40
0
2
4
6
8
10
12
14
Input Voltage (V)
16
18
60
80
100
20
VOUT = 16 V
D018
120 140 160
Resistor (k:)
180
200
220
240
D040
VIN = 7.2 V
Auto PFM
Figure 10. Switch Current Limit vs Setting Resistor
26
24
24
22
22
ON Resistance (m:)
ON Resistance (m:)
Figure 9. Shutdown Current vs VIN
20
18
16
20
18
16
14
14
12
12
10
-40
10
-40
-20
0
20
40
60
Temperature (qC)
80
100
-20
0
120
D014
20
40
60
80
Temperature (qC)
100
120
140
D013
VCC = 6 V
VCC = 6 V
Figure 12. HS Rdson vs Temperature
Figure 11. LS Rdson vs Temperature
8
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Typical Characteristics (continued)
3300
1.205
3000
2700
1.203
Refrence Voltage (V)
Frequency (kHz)
2400
2100
1800
1500
1200
900
1.201
1.199
1.197
600
300
1.195
-40
0
0
100
200
VIN = 7.2 V
300
400 500 600
Resistor (k:)
700
800
900 1000
1.2
2.6
1.1
EN Threshold Voltage (V)
2.5
VIN UVLO (V)
20
40
60
80
Temperature (qC)
100
120
140
D015
Figure 14. Reference Voltage vs Temperature
Figure 13. Frequency vs Setting Resistor
2.4
2.3
2.2
2.1
2
0
20
40
60
Temperature (qC)
80
100
1
0.9
0.8
0.7
0.6
0.5
Rising
Falling
1.9
-20
0
VOUT = 16 V
2.7
1.8
-40
-20
120130
0.4
-40
Rising
Falling
-20
D023
Figure 15. VIN UVLO Rising / Falling vs Temperature
0
20
40
60
80
Temperature (qC)
100
120
140
D024
Figure 16. EN Threshold Rising / Falling vs Temperature
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8 Detailed Description
8.1 Overview
The TPS61178x family is a synchronous boost converter designed for delivering the switch peak current up to 10
A and output voltage reaching to 20 V. The TPS61178x family operates at a fixed frequency pulse-width
modulation (PWM) at the moderate to heavy load currents. At the light load current, the TPS61178 operates in
the PFM mode while the TPS611781 operates in the Forced PWM mode. The PFM mode brings the high
efficiency crossing the entire load range while the Forced PWM mode can avoid the noise interference at the
light load.
With the peak current mode control scheme, the TPS61178x provides the excellent line and load transient
response with the minimal output capacitance. The external loop compensation brings the flexibility to use a
wider range of the inductor and output capacitor combinations.
The TPS61178x supports the adjustable switching frequency up to 2.2 MHz. The device implements a cycle-bycycle current limit to protect the device from overload during the boost operation phase. Additionally, if the output
current further increases and exceeds the short current threshold or the output voltage drops below the short
threshold. The TPS61178x triggers the hiccup short protection and recovers automatically once the short
condition releases.
Additionally, the TPS61178x provides the gate driver for the external FET to isolate the output from input end
during shutdown.
8.2 Functional Block Diagram
L
VIN
CBST
CIN
BST
VIN
CVCC
VIN VOUT
LS HS
DRV DRV
VOUT
VCC
LS
DRV
CTL
CRT
REG
ON
SW
VCC
VCC
EN
BST
P-FET
COUT1
RGATE
HS
DRV
CGATE
VOUT2
COUT2
SW
DISDRV
Q
VCC
CR LIM
Comp
S
FREQ /
SYNC
ISENSE
VOUT2
ILimit
REF
RUP
Slope Comp
+
RFREQ
+
R
OFF
OR
VCLK
FB
Gm
PWM
Comp
VCC
+
VREF
+
RDOWN
+
SS
ILIMIT
ILimit REF
COMP
+
+
RLIMIT
Cc
Cp
VOUT OVP TH.
AGND
Temp OTP TH.
RC
PGND
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8.3 Feature Description
8.3.1 Under-voltage Lockout
An under-voltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the UVLO threshold of 2.3 V. A hysteresis of 400 mV is added so that the device cannot be enabled again until
the input voltage exceeds 2.7 V. This function is implemented in order to prevent malfunctioning of the device
when the input voltage is between 2.3 V and 2.7 V.
8.3.2 Enable and Disable
When the input voltage is above UVLO rising threshold of 2.7 V and the EN pin is pulled high above 1.2 V, the
TPS61178X is enabled. When the EN pin is pulled below 0.4 V, the TPS61178x goes into the shutdown mode
and stops switching.
8.3.3 Startup
When the input voltage to the device exceeds the UVLO threshold and EN pin pulled to high as well, the
TPS61178x starts to ramp up the output voltage. There is a switching pre-charge phase and the output voltage is
charged up to 10% higher than the input voltage (1.1 x VIN). The switching frequency is a fixed 500 kHz at the
pre-charge phase.
After the pre-charge phase ends (typical 2.6 ms), The TPS61178x regulates the FB pin to the internal soft start
voltage and results in a gradual rise of the output voltage starting from the input voltage level to the target output
voltage. The soft start time is typical 3.2 ms, which helps the regulator to gradually reach the steady state setting
point, thus reducing the startup stresses and surges. The switching frequency follows the oscillator setting by the
resistor connecting with the FREQ / SYNC pin.
If the device is synchronized by the external clock, the switching frequency is fixed 500 kHz at the soft start
phase and changes to the external clock when the soft start phase ends.
8.3.4 Load Disconnect Gate Driver
The TPS61178 device provides a DISDRV pin to drive the external FET at the output side, which completely
disconnects the output from the input end during shutdown or output short happens. During the device’s start-up
phase, the disconnect FET is controlled by the gate driver voltage of the external disconnect FET, there is an
internal 55 µA (typical) sink current. The load disconnect FET connection is shown as Figure 17
The driver voltage and turn on / off timing can be set via the resistor and capacitor connecting between with the
DISDRV pin and the source of the external FET. See the Application and Implementation section for the details
of how to select the gate resistor and capacitor
P-MOS
VOUT2
VOUT
COUT1
RGATE
CGATE
COUT2
VGS
DISDRV
Figure 17. The Load Disconnect FET Connected
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Feature Description (continued)
8.3.5 Adjustable Peak Current Limit
When the TPS61178x is in the normal boost switching phase, the device is prevented from the over current
condition via the cycle by cycle current limit by sensing the current through the internal low-side FET. When the
peak switch current triggers the current limit threshold, the low-side switch turns off to prevent the switching
current further increasing.
The peak switch current limit can be set by a resistor connecting with the ILIMIT pin. The relationship between the
current limit and the resistor is determined by Equation 1
745
RLIMIT =
ILIMIT
(1)
Where RLIMIT is the resistor for setting the current limit, with the unit of kΩ, ILIMIT is switching peak current limit,
the unit is A. For instance, when the resistor value is 50 kΩ, the switch peak current limit is 15 A.
Figure 18 shows the current limit versus the setting resistor for both TPS61178 ( Auto PFM ) and TPS611781 (
Forced PWM ) with 7.2-V input to 16-V output.
16
Auto PFM
14
Current Limit (A)
12
10
8
6
4
2
0
40
60
80
100
120 140 160
Resistor (k:)
180
200
220
240
D040
Figure 18. Switch Current Limit vs. Setting Resistor
The current limit value varies with the duty cycle, Figure 30 shows the bench measurement current limit at
different duty cycles at RLIMIT = 80.6 kΩ.
9.9
Auto PFM
Current Limit (A)
9.4
8.9
8.4
7.9
7.4
0.4
0.45
0.5
0.55
0.6 0.65 0.7
Duty Cycle
0.75
0.8
0.85
0.9
D041
Figure 19. Switch Current Limit vs. Duty Cycle
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Feature Description (continued)
For the TPS611781, which works in the Forced PWM mode at the light load, the current limit is typically 0.8 A
lower than TPS61178 (Auto PFM) with the same setting resistor.
8.3.6 Output Short Protection (with load disconnected FET)
In addition to the cycle-by-cycle current limiting, the TPS61178x also has the output short protection. If the
inductor current reaches the short protection limit threshold (typical 20A ) or the output voltage drops below 30%
(typical) of the normal output voltage, the device enters into the hiccup protection mode. In the hiccup mode, the
device shuts down itself and restarts after 90ms (typical) waiting time which helps to reduce the total thermal
dissipation. After the short condition releases, the device can recover automatically and restart the start-up
phase. The hiccup protection scheme is illustrated in Figure 20.
VOUT2
SW
P_MOS gate disabled
(Ilimit_short trigger or VOUT < 30%
x VOUT_Normal )
-VGS
Ishort_limit
(typical 20A )
P-MOS date gate turn off time:
2 = Rgate x Cgate
IL
Hiccup off time
Retry after hiccup off
time terminate
Figure 20. Output Short Protection
8.3.7 Adjustable Switching Frequency
The TPS61178x features of a wide adjustable switching frequency ranging up to 2.2 MHz. The switching
frequency is set by a resistor connecting with the FREQ / SYNC pin. This pin cannot be left floating in the
application. Use Equation 2 and Equation 3 to calculate the resistor value for a desired frequency.
1
T=
= k ´ CFREQ ´ RFREQ + TDELAY
Freq
(2)
RFREQ
1
- TDELAY
Freq
=
k ´ CFREQ
where
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Feature Description (continued)
•
TDELAY = 50 nS, k = 3, CFREQ = 1.8 pF
(3)
For instance, if the RFREQ is 342 kΩ, the frequency is 500 kHz.
Figure 21 shows the switching frequency versus the setting resistor, which is measured with VOUT = 16 V from
VIN = 7.2 V .
3300
3000
2700
Frequency (kHz)
2400
2100
1800
1500
1200
900
600
300
0
0
100
200
300
400 500 600
Resistor (k:)
700
800
900 1000
Figure 21. Switching Frequency vs Setting Resistor
8.3.8 External Clock Synchronization (TPS611781)
The FREQ/ SYNC pin can be used to synchronize the internal oscillator by an external clock. A positive voltage
at the FREQ / SYNC pin must exceed the rising threshold (1.2 V) while must be lower than the falling threshold
(0.4 V) to trip the internal synchronization pulse detector. The recommended frequency for the external clock is
between 200 kHz and 2.2 MHz.
8.3.9 Error Amplifier
The TPS61178x has a trans-conductance amplifier and compares the feedback voltage with the internal voltage
reference (or the internal soft start voltage during startup phase). The trans-conductance of the error amplifier is
195 µA / V typically. The loop compensation components are required to be placed between the COMP terminal
and ground to balance the loop stability and the transient response time.
8.3.10 Slope Compensation
The TPS61178x adopts the peak current mode control and adds a compensating ramp to the switch current
signal. This slope compensation prevents the sub-harmonic oscillations when the duty cycle is larger than 50%.
The available peak inductor current varies a little bit with operating duty cycles shown in Figure 19.
8.3.11 Start-up with the Output Pre-Biased
The TPS61178x has been designed to prevent the low-side FET from discharging a pre-biased output. During
the pre-biased startup, both high-side and low-side FETs are not allowed to be turned on until the internal soft
start voltage is higher than the sensed output voltage at FB pin.
8.3.12 Bootstrap Voltage (BST)
The TPS61178x has an integrated bootstrap regulator, and requires a small ceramic capacitor between the BST
pin and SW pin to provide the gate drive voltage for the high-side FET. The bootstrap capacitor is charged when
the BST-SW voltage is below regulation. The value of this ceramic capacitor should be above 0.1 µF. A ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of
the stable characteristics over temperature and DC biased voltage.
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Feature Description (continued)
8.3.13 Over-voltage Protection
If the output voltage at the VOUT pin is detected above over-voltage protection threshold, typically 21 V, the
TPS61178x stops switching immediately until the voltage at the VOUT pin drops lower than the output overvoltage protection threshold (with 500mV hysteresis). This function prevents the devices against the over-voltage
and secures the circuits connected to the output from excessive over voltage.
8.3.14 Thermal Shutdown
A thermal shutdown is implemented to prevent the damage due to the excessive heat and power dissipation.
Typically, the thermal shutdown occurs at the junction temperature exceeding 150°C. When the thermal
shutdown is triggered, the device stops switching and recover when the junction temperature falls below 130°C
(typical).
8.4 Device Functional Modes
8.4.1 Operation
TPS61178x operates at the peak current-mode pulse-width-modulation (PWM). At the beginning of each
switching cycle, the low-side FET switch turns on, and the inductor current ramps up to a peak current that is
determined by the output of the internal error amplifier. The PWM controller turns off the low-side FET when the
peak inductor current reaches a threshold level set by the error amplifier output. After the low-side FET turns off,
the high-side synchronous FET is turned on after a short dead time until the beginning of the next oscillator clock
cycle or until the inductor current reaches the reverse current sense threshold.
During the portion of the switching cycle when the low-side FET is on, the input voltage is applied across the
inductor and stores the energy as the inductor current ramps up. Meanwhile only the output capacitor supplies
the load current. When it turns off the low-side FET, the inductor transfers the stored energy via the high-side
synchronous FET to replenish the output capacitor and also supply the load current. This operation repeats every
switching cycle.
The device features the internal slope compensation to avoid sub-harmonic oscillation that is intrinsic to peakcurrent mode control at duty cycle larger than 50%. The internal slope compensation may not be adequate to
maintain stability for a very low inductance in application.
At the light load condition, the TPS61178x implements two options: Auto PFM mode (TPS61178) and Forced
PWM mode (TPS611781) to meet different application requirements.
8.4.2 Auto PFM Mode (TPS61178)
The TPS61178 integrates a Power Save Mode with pulse frequency modulation ( PFM ) at the light load. When a
light load condition occurs, the COMP pin voltage naturally decreases and reduces the peak current. When the
COMP pin voltage further goes down with the load lowered and reaches the pre-set low threshold, the output of
the error amplifier is clamped at this threshold and does not go down any more. If the load is further lowered, the
output voltage of TPS61178 exceeds the nominal voltage and the device skips the switching cycles and regulate
the output voltage at a higher threshold (typical 101%*VOUT_NORMAL).
The Auto PFM mode reduces the switching losses and improves efficiency at the light load condition by reducing
the average switching frequency.
8.4.3 Forced PWM Mode (TPS611781)
In the Forced PWM mode, the TPS611781 keeps the switching frequency being constant for the whole load
range. When the load current decreases, the output of the internal error amplifier decreases as well to lower the
inductor peak current and delivers less power from input to output. The high-side FET is not turned off even if the
current through the FET goes negative to keep the switching frequency being the same as that of the heavy load.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS61178x family is the step up DC / DC converter. The following design procedure can be used to select
component values for the TPS61178x. Alternately, the WEBENCH® software may be used to generate a
complete design. The WEBENCH® software uses an interactive design procedure and accesses a
comprehensive database of components when generating a design. This section presents a simplified discussion
of the design process.
9.2 Typical Application
The application described is for 6-V to 14-V input, 16-V output converter.
L
VIN
1.8 uH
CIN1
22 uF
VIN
BST
VCC
CVCC
SW
4.7 uF
CBST
0.1 uH
VOUT2
M1
VOUT
EN
COUT1_1 COUT1_2
10 uF
10 uF
FREQ /
SYNC
RFreq
RGATE
CGATE
150 kŸ 22 nF
RUP
860 kŸ
COUT2_1
22 uF
COUT2_2
22 uF
COUT2_3
22 uF
DISDRV
348 kŸ
RDOWN
80.6 kŸ
FB
ILIMIT
RLIMIT
COMP
51.1 kŸ
AGND
PGND
Cc
6.8 nF
RC
15.0 kŸ
Cp
10 pF
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Figure 22. TPS61178 16-V Output with Load Disconnect Schematic
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Typical Application (continued)
9.2.1 Design Requirements
For this design example, use Table 1 as the design parameters.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage range
6 V to 14 V
Output voltage
16 V
Output ripple voltage
±3%
Output current rating
3A
Operating frequency
500 kHz
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61178 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
To
•
•
•
•
•
•
begin the design process a few parameters must be decided upon. The designer needs to know the following:
Input voltage range
Output voltage
Output ripple voltage
Output current rating
Operating frequency
Load disconnect needed or not
9.2.2.2 Setting the Switching Frequency
The switching frequency of the TPS61178 is set at 500 kHz. Use Equation 2 to calculate the required resistor
value. The calculated value is 342 kΩ. Use the next higher standard value of 348 kΩ.
9.2.3 Setting the Current Limit
The current limit of the TPS61178 could be programmed by an external resistor. For a target current limit of 13
A, the calculated resistor value is 57 kΩ. However, the minimum current limit is around 1.6 A lower than the
typical one. Here, selecting the 51.1 kΩ resistor to deliver 13-A peak current at the worst case.
9.2.4 Setting the Output Voltage
The output voltage of the TPS61178 is externally adjustable using a resistor divider network. The relationship
between the output voltage and the resistor divider is given by Equation 4.
RUP
VOUT = VFB ´ (1 +
)
RDOWN
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where
•
•
•
VOUT is the output voltage
RUP the top divider resistor
RDOWN is the bottom divider resistor
(4)
Choose RDOWN to be approximately 80.6 kΩ. Slightly increasing or decreasing RDOWN can result in closer output
voltage matching when using standard value resistors. In this design, RDOWN = 80.6 kΩ and RUP = 1000 kΩ,
resulting in an output voltage of 16 V.
For the best accuracy, RDOWN is recommended to be smaller than 100 kΩ to ensure that the current following
through RDOWN is at least 100 times larger than FB pin leakage current. Changing RDOWN towards the lower value
increases the robustness against noise injection. Changing the RDOWN towards the higher values reduces the
quiescent current for achieving higher efficiency at the light load currents.
9.2.4.1 Selecting the Inductor
A boost converter normally requires two main passive components for storing the energy during the power
conversion: an inductor and an output capacitor. The inductor affects the steady state efficiency ( including the
ripple and efficiency ) as well as the transient behavior and loop stability, which makes the inductor to be the
most critical component in application.
When selecting the inductor, as well as the inductance, the other parameters of importance are:
• The maximum current rating (RMS and peak current should be considered),
• The series resistance,
• Operating temperature
Choosing the inductor ripple current with the low ripple percentage of the average inductor current results in a
larger inductance value, maximizes the converter’s potential output current and minimizes EMI. The larger ripple
results in a smaller inductance value, and a physically smaller inductor, improves transient response but results
in potentially higher EMI.
The rule of thumb to choose the inductor is that to make the inductor ripple current (ΔIL) is a certain percentage
(Ripple % = 20 – 30 %) of the average current. The inductance can be calculated by Equation 5, Equation 6, and
Equation 7:
V ´D
DIL = IN
L ´ fSW
(5)
DIL _ R = Ripple% ´
L=
VOUT ´ IOUT
h ´ VIN
(6)
h ´ VIN
V ´D
1
´
´ IN
Ripple % VOUT ´ IOUT
ƒSW
where
•
•
•
•
•
•
•
•
•
ΔIL is the peak-peak inductor current ripple
VIN is the input voltage
D is the duty cycle
L is the inductor
ƒSW is the switching frequency
Ripple % is the ripple ration versus the DC current
VOUT is the output voltage
IOUT is the output current
η is the efficiency
(7)
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power-up, load faults, or transient load conditions, the inductor current can increase above the peak inductor
current calculated.
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The TPS61178x has built-in slope compensation to avoid sub-harmonic oscillation associated with the current
mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 4 A, the
slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make
the peak-to-peak current ripple below 4 A when selecting the inductor.
Inductor values can have ± 20% or even ± 30% tolerance with no current bias. When the inductor current
approaches the saturation level, its inductance can decrease 20% to 35% from the value at 0-A bias current
depending on how the inductor vendor defines saturation. When selecting an inductor, make sure its rated
current, especially the saturation current, is larger than its peak current during the operation.
The inductor peak current varies as a function of the load, the switching frequency, the input and output voltages
and it can be calculated by Equation 8 and Equation 9.
1
IPEAK = IIN + ´ DIL
2
where
•
•
•
IPEAK is the peak current of the inductor
IIN is the input average current
ΔIL is the ripple current of the inductor
(8)
The input DC current is determined by the output voltage, the output current and efficiency can be calculated by :
V
´I
IIN = OUT OUT
VIN ´ h
where
•
•
•
•
IIN is the input current of the inductor
VOUT is the output voltage
VIN is the input voltage
η is the efficiency
(9)
While the inductor ripple current depends on the inductance, the frequency, the input voltage and duty cycle
calculated by Equation 5, replace Equation 5, Equation 9 into Equation 8 and get the inductor peak current:
IOUT
1 V ´D
+ ´ IN
IPEAK =
(1 - D) ´ h 2 L ´ fSW
where
•
•
•
•
•
•
•
IPEAK is the peak current of the inductor
IOUT is the output current
D is the duty cycle
η is the efficiency
VIN is the input voltage
L is the inductor
ƒSW is the switching frequency
(10)
The heat rating current (RMS) is as below:
IL _ RMS = IIN 2 +
1
( DIL )2
12
where
•
•
•
IL_RMS is the RMS current of the inductor
IIN is the input current of the inductor
ΔIL is the ripple current of the inductor
(11)
It is important that the peak current does not exceed the inductor saturation current and the RMS current is not
over the temperature related rating current of the inductors.
For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation
current. The total losses of the coil consists of the DC resistance ( DCR ) loss and the following frequency
dependent loss:
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•
•
•
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The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the
frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,
it is usually a tradeoff between the loss and foot print.
The following inductor series in Table 2 from the different suppliers are recommended. 74437368033 from Würth
is used for this application case with balancing the size and power loss.
Table 2. Recommended Inductors for TPS61178x (1)
PART NUMBER
L (μH)
DCR Typ (mΩ) Max
SATURATION
CURRENT / Heat
Rating Current (A)
SIZE (L × W × H
mm)
VENDOR (1)
744325180
1.8
3.5
18
5 x 10 x 4
Würth
74437368033
3.3
11.8
23 / 8
10 x 10 x 3.8
Würth
DFEH10040D3R3M#
3.3
12
10 / 10
10.9 x 10 x 4
Murata / TOKO
PIMB104T-4R7MS
4.7
20.0
15 / 8.5
10.9 x 10 x 3.8
Cyntec
74437368068
6.8
17.5
14
11 x 10 x 3.8
Würth
74437368100
10
27
12.5
11 x 10 x 3.8
Würth
(1)
See Third-party Products Disclaimer
9.2.4.2 Selecting the Output Capacitors
The output capacitor is mainly selected to meet the requirements at load transient or steady state. Then the loop
is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series
resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by Equation 12:
I
´ (VOUT - VIN )
COUT = OUT
fSW ´ DV ´ VOUT
where
•
•
•
•
•
•
COUT is the output capacitor
IOUT is the output current
VOUT is the output voltage
VIN is the input voltage
ΔV is the output voltage ripple required
ƒSW is the switching frequency
(12)
The additional output ripple component caused by ESR is calculated by Equation 13:
DVESR = IOUT ´ RESR
where
•
•
ΔVESR is the output voltage ripple caused by ESR
RESR is the resistor in series with the output capacitor
(13)
For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,
it must be considered if used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using
Equation 14:
DISTEP
COUT =
2p ´ fBW ´ DVTRAN
where
•
20
ΔISTEP is the transient load current step
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•
•
ΔVTRAN is the allowed voltage dip for the load current step
ƒBW is the control loop bandwidth (i.e., the frequency where the control loop gain crosses zero)
(14)
Care must be taken when evaluating a ceramic capacitor’s derating under the DC bias. Ceramic capacitors can
derate by as much as 70% of its capacitance at its rated voltage. Therefore, enough margins on the voltage
rating should be considered to ensure adequate capacitance at the required output voltage.
In applications of TPS61178x, it is recommended to run the converter with a reasonable amount of effective
output capacitance, for instance 3 x 22-μF X5R or X7R MLCC capacitors connected in parallel.
If the load disconnect FET is connected, the output capacitor should be split shown in Figure 23. COUT2 should
be no larger than 10 x COUT1 to avoid the inrush current when turning on the disconnect FET.
P-FET
VOUT2
VOUT
COUT1
RGATE
CGATE
VGS
COUT2
DISDRV
Figure 23. Output Capacitor Configuration with the Load Disconnect FET
9.2.4.3 Selecting the Input Capacitors
Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter as they
have extremely low ESR and are available in small footprints. Input capacitors should be located as close as
possible to the device. While a 22-µF input capacitor is sufficient for the most applications, larger values may be
used to reduce input current ripple.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, should be placed
between CIN and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CIN.
9.2.4.4 Loop Stability and Compensation
9.2.4.4.1 Small Signal Model
The TPS61178x uses the fixed frequency peak current mode control; there is an internal adaptive slope
compensation to avoid the sub-harmonic oscillation. With the inductor current information sensed, the smallsignal model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole
system, created by ROUT and COUT. The single-pole system is easily used with the loop compensation. Figure 24
shows the equivalent small signal elements of a boost converter.
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L
VIN
VOUT
CIN
Q
ROUT
RESR
RSENSE
Slope
Comp
Q
COUT
ISENSE
VOUT
RUP
S
Q
R
FB
+
GEA
Cc
Cp
+
VREF
RDOWN
REA
RC
Copyright © 2017, Texas Instruments Incorporated
Figure 24. TPS61178x Control Equivalent Circuitry Model
The small signal of power stage including the slope compensation is:
S
S
(1 +
)(1 )
R
2p ´ fESR
2p ´ fRHP
´ (1 - D)
GPS (S) = OUT
´
´ He(S)
2 ´ RSENSE
S
1+
2p ´ fP
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
RSENSE is the equivalent internal current sense resistor, which is typically 0.083 Ω of TPS61178x
(15)
The single pole of the power stage is:
2
fP =
2p ´ ROUT ´ COUT
where
•
COUT is the output capacitance, for a boost converter having multiple, identical output capacitors in parallel,
simply combine the capacitors with the equivalent capacitance
(16)
The zero created by the ESR of the output capacitor is:
1
fESR =
2p ´ RESR ´ COUT
where
•
RESR is the equivalent resistance in series of the output capacitor.
(17)
The right-hand plane zero is:
fRHP =
22
ROUT ´ (1 - D)2
2p ´ L
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where
•
•
•
D is the duty cycle
ROUT is the output load resistor
L is the inductance
(18)
Using He(s) to model the inductor current sampling effect as well as the slope compensation effect on the small
signal response, is shown in Equation 19
1
He(S) =
Se
é
ù
S ´ ê(1 +
) ´ (1 - D) - 0.5 ú
S2
Sn
ë
û+
1+
fSW
( p ´ fSW )2
(19)
Sn =
VIN
´ RSENSE
L
where
•
Sn is the slew rate of the inductor current ramping up
Se = 0.06 ´
(20)
fSW
´ R dson _ LS
1- D
where
•
•
Se is the slope compensation slew rate
Rdson_LS is the on resistance of Low-side FET
(21)
The slope compensation adaptively changes with the switching frequency and duty cycle.
He(s) models the inductor current sampling effect as well as the slope compensation effect on the small signal
response. Note that if Sn > Se, e.g., when L is too small, the converter operates as a voltage mode converter
and the above model no longer holds.
The TPS61178x COMP pin is the output of the internal trans-conductance amplifier.
Equation 22 shows the equation for feedback resistor network and the error amplifier.
S
1+
RDOWN
2 ´ p ´ fZ
HEA (S) = GEA ´ REA ´
´
RUP + RDOWN
S
S
(1 +
) ´ (1 +
)
2 ´ p ´ fP1
2 ´ p ´ fP2
where
•
•
fP1 =
kCOMP and REA are the ratio of peak current / comp voltage, for TPS61178x, the typical value is kCOMP = 12 A /
V and REA = 20 MΩ.
ƒP1, ƒP2 is the pole's frequency of the compensation, fZ is the zero’s frequency of the compensation network.
network
(22)
1
2p ´ REA ´ Cc
where
•
fP2
CC is the zero capacitor compensation
(23)
1
=
2p ´ RC ´ CP
where
•
•
CP is the pole capacitor compensation
RC is the resistor of the compensation network
(24)
1
fZ =
2p ´ RC ´ CC
(25)
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9.2.4.4.2 Loop Compensation Design Steps
With the small signal models coming out, the next step is to calculate the compensation network parameters with
the given inductor and output capacitance.
1. Set the Cross Over Frequency, ƒC
– The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the
loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either
1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop
compensation network values of RC, CC, and CP by following below equations.
2. Set the Compensation Resistor, RC
– By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~= RC and so RC × GEA sets the
compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s) =
GPS(s) × HEA(s) × He(s) being zero at ƒC.
– Therefore, to approximate a single-pole roll-off up to fP2, rearrange Equation 22 to solve for RC so that
the compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power
stage bode plot or more simply:
RDOWN
KEA (fC ) = 20 ´ log(GEA ´ RC ´
) = - KPS (fC )
RUP + RDOWN
where
•
•
•
KEA is gain of the error amplifier network
KPS is the gain of the power stage
GEA is the amplifier’s trans-conductance, the typical value of GEA = 195 µA / V
3. Set the compensation zero capacitor, CC
– Place the compensation zero at the power stage ROUT ,COUT pole’s position, so to get:
1
fZ =
2p ´ RC ´ CC
– Set ƒZ = ƒP, and get the
R
´ COUT
CC = OUT
2RC
(26)
(27)
(28)
4. Set the compensation pole capacitor, CP
– Place the compensation pole at the zero produced by the RESR and the COUT, it is useful for canceling
unhelpful effects of the ESR zero.
1
fP2 =
2p ´ RC ´ CP
(29)
fESR =
1
2p ´ RESR ´ COUT
(30)
– Set ƒP2 = ƒESR, and get the
R
´ COUT
CP = ESR
RC
(31)
– If the calculated value of CP is less than 10 pF, it can be neglected.
Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output
voltage ringing during the line and load transient. The RC = 15 kΩ , CC = 6.8 nF, Cp = 10 pF for this design
example.
9.2.4.4.3 Selecting the Disconnect FET
The TPS61178x provides a gate driver to control an external FET to disconnect the output from the input at
shutdown or output short conditions, shown in Figure 25.
24
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P-MOS
VOUT2
VOUT
COUT1
RGATE
CGATE
COUT2
VGS
DISDRV
Figure 25. Load Disconnect FET Connection
The VDS, IDS and safe operation area (SOA) should be taken into consideration when selecting the FET:
• The drain-to-source voltage rating should be higher than the output max. voltage, VDS_DIS_MAX = VOUT,
• The drain-to-source RMS current rating is the maximum output current. I DS_DIS_RMS = IOUT,
• The SOA should be considered when the output short occurs, and there is heat caused by the short
protection response time and surge current, SOA > QSHORT.
1
QSHORT =
´ VOUT ´ ISHORT ´ TSHORT
2
where
•
•
•
•
•
VDS_DIS_Max is the maximum drain-source voltage
IDS_DIS is the drain-source RMS current
ISHORT is the short current
TSHORT is the response time before the short protection triggered
QSHORT is the heat produced for the output short
(32)
For instance: VOUT = 16 V, ISHORT = 20 A , TSHORT = 30 µs.
SOA ≥ 4.8 mJ, VDS_DIS_MAX ≥ 16 V.
The CSD25404Q3 –20 V P-Channel NexFET™ Power FET is used for this design example.
An additional capacitor between the gate and source of the external FET is required to slow the turn-on speed.
VTH _ PFET ´ CGS _ PFET
TON _ PFET =
IDIS_ PFET
where
•
•
•
•
TON_PFET is the on time of external FET
VTH_PFET is the gate threshold of external FET
CGS_PFET is the total gate capacitance of connected between gate and source external FET. (including the selfgate-source capacitance of the FET)
(33)
IDIS_PFET is the discharge current inside of TPS61178x, it is 55 µA typically
Given 1.5 V threshold, CGS_PFET is 10 nF, the TON_PFET is around 300 µs.Please be aware that the maximum turnon time should not exceed 3 ms, and the maximum capacitance CGS_PFET should be < 100 nF. Otherwise, the
TPS61178x could not startup normally if the disconnect FET could not be turn on within the 3 ms.
The gate resistor depends on the gate-source voltage of the external FET,
VGATE = RGATE ´ IDIS_ PFET
(34)
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RGATE =
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VGATE
IDIS_ PFET
(35)
Given the 5-V VGATE, the RGATE = 100 kΩ
9.2.4.4.4 Selecting the Bootstrap Capacitor
The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET
device gate during each cycle’s turn-on and also supplies charge for the bootstrap capacitor. The recommended
value of the bootstrap capacitor is 0.1 µF to 1 µF. CBST should be a good quality, low ESR, ceramic capacitor
located at the pins of the device to minimize potentially damaging voltage transients caused by trace inductance.
A value of 0.1 µF was selected for this design example.
9.2.4.4.5 VCC Capacitor
The primary purpose of the VCC capacitor is to supply the peak transient currents of the driver and bootstrap
capacitor as well as provide stability for the VCC regulator. The value of CVCC should be at least 10 times greater
than the value of CBST, and should be a good quality, low ESR, ceramic capacitor. CVCC should be placed close
to the pins of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value
of 4.7 µF was selected for this design example.
9.2.5 TPS61178 Application Waveform
Typical condition VIN = 6 V to 14 V, VOUT = 16 V, RLIMIT = 51.1 kΩ, RFREQ = 348 kΩ
Application waveforms are measured with the inductor 3.3 µH, Würth 74437368033, and the output capacitance:
3 x 22 µF, GRM32ER61E226KE15L plus 2 x 10 µF, GRM188R61E106MA73D.
VOUT2_AC
50 mV / div
CH1: VOUT2_AC
10 mV / div
CH3: SW
7 V / Div
CH3: SW
7 V / Div
CH4: IL
1 A / Div
CH4: IL
2 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Load = 1000 mA
VIN = 7.2 V
L = 3.3 µH
Figure 26. Steady State 1000 mA
26
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VOUT= 16 V
COUT= 86 µF
Auto PFM
Load = 10 mA
Figure 27. Steady-state 10 mA
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CH3: EN
2 V / div
CH3: EN
2 V / div
CH1: VOUT2
5 V / div
CH1: VOUT2
5 V / div
CH4: IL
1 A / Div
CH4: IL
1 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Auto PFM
Load = 32 Ω
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Auto PFM
Load = 32 Ω
Figure 29. Shutdown by EN
Figure 28. Startup by EN
CH1: VOUT2
8 V / div
CH2: VOUT
(before dis FET)
5 V / Div
CH1: VOUT2_AC
500 mV / div
CH4: Load
1 A / Div
M1: VGS
5 V / Div
CH4: IL
6 A / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Load = 500 mA to 2 A,
0.1 A/µs slew rate
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Figure 31. Output Short (with Disconnect FET)
Figure 30. Load Transient
CH1: VOUT2
8 V / div
CH2: VOUT
(before dis FET)
5 V / Div
M1: VGS
5 V / Div
CH4: IL
900 mA / Div
VIN = 7.2 V
L = 3.3 µH
VOUT= 16 V
COUT= 86 µF
Figure 32. Output Short Release (with Disconnect FET)
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9.3 System Examples
9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
The Figure 33 is the typical application schematic for 2.7-V to 4.4-V input (single cell Li+ battery) to output 14-V
output converter. The inductor can be lower to 1.8 µH for the 14-V output.
L
VIN
1.8 uH
CIN1
22 uF
VIN
BST
VCC
CBST
0.1 uH
CVCC
SW
4.7 uF
VOUT2
M1
VOUT
EN
RFreq
COUT1_1 COUT1_2
10 uF
10 uF
FREQ /
SYNC
RGATE
CGATE
RUP
860 kŸ
150 kŸ 22 nF
COUT2_1
22 uF
COUT2_2
22 uF
COUT2_3
22 uF
DISDRV
348 kŸ
RDOWN
80.6 kŸ
FB
ILIMIT
RLIMIT
51.1 kŸ
COMP
AGND
PGND
Cc
6.8 nF
RC
15.0 kŸ
Cp
10 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 33. 14-V Output Voltage from 2.7-V to 4.4-V Input Voltage
9.3.2 TPS61178 Without Load Disconnect Function
The Figure 34 is the typical application schematic is for 6-V to 14-V input (2 / 3 cells Li+ battery or 12-V bus) to
output 14-V output converter without load disconnect. With removing the load disconnect FET, it simplifies the
design and minimizes the external components.
L
3.3 H
VIN
CIN1
22 F
VIN
BST
VCC
CBST
CVCC
0.1 H
4.7 F
SW
VOUT
VOUT
EN
COUT1_1
RFREQ
10 F
FREQ / SYNC
RUP
1 MŸ
COUT2_1
22 F
COUT2_2
22 F
COUT2_3
22 F
DISDRV
348 kŸ
RDOWN
80.6 kŸ
FB
ILIMIT
RLIMIT
51.1 kŸ
COMP
AGND
PGND
Cc
6.8 nF
RC
15.0 kŸ
Cp
10 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 34. 16-V Output Voltage Without Load Disconnect Function
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System Examples (continued)
9.3.3 TPS611781 External Clock Synchronization
The Figure 35 is the typical application schematic for synchronized by an external clock of 2.2 MHz. It is for the
Forced PWM mode operation to avoid the noise-sensitive frequency range, for instance the audible noise and
AM band.
L
1.8 uH
VIN
CIN1
22 uF
VIN
BST
VCC
CBST
0.1 uH
CVCC
SW
VOUT
VOUT
EN
COUT1_1
10 uF
FREQ /
SYNC
2.2 MHz
RUP
1 MŸ
COUT2_1
22 uF
COUT2_2
22 uF
DISDRV
RDOWN
80.6 kŸ
FB
ILIMIT
RLIMIT
51.1 kŸ
COMP
AGND
PGND
Cc
5.6 nF
RC
13 kŸ
Copyright © 2017, Texas Instruments Incorporated
Figure 35. 16-V Output Voltage Synchronized by 2.2 MHz External Clock
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply ranging from 2.7 V to 20 V. This input supply
should be well regulated. If the input supply is located more than a few inches from the TPS61178x, the bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 47 µF is a typical choice.
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11 Layout
11.1 Layout Guidelines
The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not
carefully done, the regulator could suffer from the instability or noise problems.
The checklist below is suggested that be followed to get good performance for a well-designed board:
1. Minimize the high current path including the switch FET, rectifier FET, and the output capacitor. This loop
contains high di/dt switching currents ( nano seconds per ampere ) and easy to transduce the high frequency
noise;
2. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under
the switching regulator to minimize inter plane coupling;
3. Use a combination of bulk capacitors and smaller ceramic capacitors with low series resistance for the input
and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for
decoupling the noise;
4. The ground area near the IC must provide adequate heat dissipating area. Connect the wide power bus
(e.g., VOUT, SW, GND ) to the large area of copper, or to the bottom or internal layer ground plane, using vias
for enhanced thermal dissipation;
5. Place the input capacitor being close to the VIN pin and the PGND pin in order to reduce the input supply
ripple;
6. Place the noise sensitive network like the feedback and compensation being far away from the SW trace;
7. Use a separate ground trace to connect the feedback, compensation, frequency set, and the current limit set
circuitry. Connect this ground trace to the main power ground at a single point to minimize circulating
currents.
11.2 Layout Example
RREN
EN
CVCC
CBST
VIN
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
RGATE
BST VIN
CGATE
EN VCC DISDRV
VOUT2
VOUT
VOUT
SW
L
PGND
s
G
s
D
s
D
COUT2
COUT1
P-FET
s
D
GND
FREQ/
AGND ILIMITCOMP FB
SYNC
RUP
RFREQ RLIMIT CCOMP RCOMP RDOWN
Figure 36. Recommended Layout
30
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS61178 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• TPS61178EVM Evaluation Board User's Guide, SLVUB05
•
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS61178
Click here
Click here
Click here
Click here
Click here
TPS611781
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
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12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.6 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS611781RNWR
ACTIVE
VQFN-HR
RNW
13
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1CDI
TPS611781RNWT
ACTIVE
VQFN-HR
RNW
13
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
1CDI
TPS61178RNWR
ACTIVE
VQFN-HR
RNW
13
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
15RI
TPS61178RNWT
ACTIVE
VQFN-HR
RNW
13
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
15RI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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