TPS61196PWPR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 TPS61196 6-String 400-mA WLED Driver with Independent PWM Dimming for Each String 1 Features • • • 1 • • • • • • • • • • • • 8-V to 30-V Input Voltage Up to 120-V Output Voltage 100-KHz to 800-kHz Programmable Switching Frequency Adaptive Boost Output for LED Voltages Six Current Sinks, 200-mA Continuous Output, 400-mA Pulse Output for Each String ±1.5% Current Matching Between Strings High Precision PWM Dimming Resolution up to 5000:1 Programmable Overvoltage Threshold at Output and Each Current Sink Programmable Undervoltage Threshold at Input with Adjustable Hysteresis Adjustable Soft Start Time Independent of Dimming Duty Cycle Built-in LED Open and LED Short Protection Built-in Schottky Diode Open/Short Protection Built-in ISET Short Protection Built-in IFB Short Protection Thermal Shutdown The TPS61196 supports direct PWM brightness dimming. Each string has an independent PWM control input. During the PWM dimming, the LED current is turned on or turned off at the frequency and duty cycle which are determined by the external PWM signal. The PWM frequency ranges from 90 Hz to 22 kHz. The device integrates overcurrent protection, output short-circuit protection, ISET short-to-ground protection, diode open and short protection, LED open and short protection, and overtemperature shutdown circuit. In addition, the TPS61196 can detect the IFB pin short to ground to protect the LED string. The device also provides programmable input undervoltage lockout threshold and output overvoltage protection threshold. The TPS61196 has a built-in linear regulator which steps down the input voltage to the VDD voltage for powering the internal circuitry. An soft-start circuit is implemented internally to work with an external capacitor to adjust the soft start-up time to minimize the in-rush current during boost converter start-up. The device is available in a 28-pin HTSSOP package with PowerPAD™. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) 2 Applications TPS61196 • • (1) For all available packages, see the orderable addendum at the end of the datasheet. LCD TV Backlight Scan Mode LCD TV Backlight HTSSOP (28) Simplified Schematic 3 Description The TPS61196 provides a highly integrated solution for LCD TV backlight with an independent PWM dimming function for each string. This device is a current mode boost controller driving up to six WLED strings with multiple LEDs in series. Each string has an independent current regulator providing a LED current adjustable from 50 mA to 400 mA within ±1.5% matching accuracy. The minimal voltage at the current sink is programmable in the range of 0.3 V to 1 V to fit with different LED current settings. The input voltage range for the device is from 8 V to 30 V. L1 68mH VIN = 24V D1 C1 EC1 100mF EC2 100mF 10mF R19 3 VIN R5 200k C4 10nF R1 182k ISNS UVLO PGND TPS61196 R2 24.9k VDD R3 255k Q1 GDRV C2 2.2mF R6 200 R4 10k R7 0.1 C5 470pF OVP COMP C3 1.0mF FSW REF C7 EN R9 200k C8 160pF IFB1 IFB2 PWM1 IFB3 PWM2 IFB4 PWM3 IFB5 IFB6 PWM5 IFBV PWM6 FBP ISET Thermal pad R8 150k C6 47nF 2.2mF FAULT PWM4 The device adjusts the boost controller's output voltage automatically to provide only the voltage required by the LED string with the largest forward voltage drop plus the minimum required voltage at that string's IFB pin, thereby optimizing driver efficiency. Its switching frequency is programmed by an external resistor from 100 kHz to 800 kHz. 9.70 mm x 4.40 mm AGND R11 37.4k R12 196k R10 60.4k C9 0.1mF R13 R14 R15 R16 R17 R18 10M 10M 10M 10M 10M 10M 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 12 7.4 Device Functional Modes........................................ 16 8 Application and Implementation ........................ 19 8.1 Application Information............................................ 19 8.2 Typical Application ................................................. 20 9 Power Supply Recommendations...................... 23 10 Layout................................................................... 24 10.1 Layout Guidelines ................................................. 24 10.2 Layout Example .................................................... 24 11 Device and Documentation Support ................. 25 11.1 Trademarks ........................................................... 25 11.2 Electrostatic Discharge Caution ............................ 25 11.3 Glossary ................................................................ 25 12 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D Page • Added Device Information and ESD Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; moved some curves to Application Curves section; remove Device Comparison table.................................................................................................................................................................... 1 • Changed location of several specs from EC table to Switching Char ................................................................................... 7 Changes from Revision B (January 2013) to Revision C Page • Changed VL max value from 1.0 V to 0.8 V ........................................................................................................................... 5 • Changed VIN = 7 V to VIN = 8 V in Test Conditions for VISNS(OC) ............................................................................................ 6 Changes from Revision A (November 2012) to Revision B Page • Changed RPD max value from 2.4 MΩ to 3.0 MΩ................................................................................................................... 5 • Changed VISET min value from 1.220 V to 1.217 V ................................................................................................................ 5 • Deleted IFLT_L max value ......................................................................................................................................................... 6 • Changed R7 to R9 in Table 1............................................................................................................................................... 12 Changes from Original (October 2012) to Revision A • 2 Page Changed Figure 20 .............................................................................................................................................................. 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 5 Pin Configuration and Functions 28-Pin HTSSOP PWP Package Top View UVLO 1 28 EN 2 27 FAULT PWM1 3 26 FSW VIN 4 25 VDD 5 24 GDRV PWM4 6 23 ISNS PWM5 7 PWM6 8 TPS61196 PWM2 PWM3 22 PGND 21 REF 20 COMP FBP 9 ISET 10 19 OVP IFBV 11 18 AGND IFB1 12 17 IFB6 IFB2 13 16 IFB5 IFB3 14 15 IFB4 Pin Functions PIN TYPE DESCRIPTION NUMBER NAME 1 UVLO I Low input voltage lockout. Use a resistor divider from VIN to this pin to set the UVLO threshold. 2 EN I Enable and disable pin. EN high = enable, EN low = disable. PWM1 to PWM6 I PWM signal input pins. The frequency of PWM signal is in the range of 90 Hz to 22 kHz. 9 FBP O LED cross-short protection threshold program pin. Use a resistor to GND to set the threshold. 10 ISET O Connecting a resistor to the pin programs the IFB pin current level for full brightness (that is, 100% dimming). 11 IFBV O Minimum feedback voltage setting for LED strings. IFB1 to IFB6 I Regulated current sink input pins 18 AGND G Analog ground 19 OVP I Overvoltage protection detection input. Connect a resistor divider from output to this pin to program the OVP threshold. 20 COMP O Loop compensation for the boost converter. Connect a RC network to make loop stable. 21 REF O Internal reference voltage for the boost converter. Use a capacitor at this pin to adjust the soft start time. When two chips operate in parallel, connect the master's REF pin to the slave's COMP pin. 22 PGND G External MOSFET current sense ground input. 3,4,5,6,7,8 12,13,14,15,1 6,17 23 ISNS I External MOSFET current sense positive input. 24 GDRV o External switch MOSFET gate driver output. 25 VDD O Internal regulator output for device internal power supply. Connect a 1-µF ceramic capacitor to this pin. 26 FSW O Switching frequency setting pin. Use a resistor to set the frequency between 100 kHz to 800 kHz. An external input voltage above 3.5 V or below 0.5 V disables the internal clock and makes the device as slave device. 27 FAULT O Fault indicator. Open-drain output. Output high impedance when fault conditions happens. 28 VIN I Power supply input pin Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 3 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Voltage (2) MIN MAX VIN pin –0.3 33 FAULT pin –0.3 VIN FB1 to IFB6 pins –0.3 40 FBP, ISET, ISNS, IFBV pins –0.3 3.3 EN, PWM1 to PWM6 pins –0.3 20 GDRV pins –0.3 7 –2 9 GDRV 10-ns transient pins All other pins –0.3 Continuous power dissipation UNIT V 7 See Thermal Information Operating junction temperature –40 150 °C Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) Electrostatic discharge (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 Machine model (1) (2) UNIT V 200 (max) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN VIN Input voltage VOUT Output voltage L1 NOM MAX UNIT 8 30 VIN 120 V Inductor 10 100 µH CIN Input capacitor 10 COUT Output capacitor 22 220 µF fSW Boost regulator switching frequency 100 800 kHz fDIM PWM dimming frequency 0.09 22 kHz TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C (1) 4 V µF Customers need to verify the component value in their application if the values are different from the recommended values. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 6.4 Thermal Information TPS61196 THERMAL METRIC (1) PWP UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 33.8 RθJC(top) Junction-to-case (top) thermal resistance 18.8 RθJB Junction-to-board thermal resistance 15.6 ψJT Junction-to-top characterization parameter 0.6 ψJB Junction-to-board characterization parameter 15.4 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics VIN= 24 V, minimum and maximum limits are at TA = –40°C to +85°C, typical values are at TA = 25°C, C1 = 10 μF, C2 = 2.2 μF, C3 = 1 μF, EC1 = EC2 = 100 μF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VIN Input voltage range VVIN_UVLO Undervoltage lockout threshold 8 VVIN_HYS VIN UVLO hysteresis Iq_VIN Operating quiescent current into VIN Device enabled, no switching, VIN = 30 V ISD Shutdown current VIN = 12 V, VIN = 30 V VDD Regulation voltage for internal circuit 0 mA < IDD < 15 mA 5.7 VH Logic high input on EN,PWMx VIN = 8 V to 30 V 1.8 VL Logic low input on EN, PWMx VIN = 8 V to 30 V RPD Pull-down resistance on EN, PWMx VIN falling 6.5 30 V 7 V 300 6 mV 2 mA 25 50 µA 6.3 V EN and PWMx V 0.8 V 0.8 1.6 3 MΩ 1.204 1.229 1.253 V –0.1 –4.3 a -3.9 0.1 –3.3 µA UVLO VUVLOTH IUVLO Threshold voltage at UVLO pin UVLO input bias current VUVLO = VUVLOTH – 50 mV VUVLO = VUVLOTH + 50 mV Soft start charging current PWM ON, VREF< 2 V PWM ON, VREF> 2 V SOFT START ISS 200 10 µA CURRENT REGULATION VISET ISET pin voltage 1.217 1.229 1.240 V IISET_P ISET short-to-ground protection threshold 120 150 180 µA KISET Current multiple IIFB/IISET IIFB(AVG) Current accuracy IISET = 32.56 µA, VIFB = 0.5 V 3932 3992 4052 IISET = 32.56 µA, VIFB = 0.5 V 127.4 130 132.6 KIFB(M) Current matching; (IFB(MAX)IFB(MIN))/2IFB(AVG) IISET = 32.56 µA, VIFB = 0.5 V 0.5% 1.5% IIFB_LEAK IFB pin leakage current at dimming off IFB voltage < 40 V IIFB_max Current sink max output current VIFBV = 350 mV 1 130 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 mA µA mA 5 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) VIN= 24 V, minimum and maximum limits are at TA = –40°C to +85°C, typical values are at TA = 25°C, C1 = 10 μF, C2 = 2.2 μF, C3 = 1 μF, EC1 = EC2 = 100 μF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IFB REGULATION VOLTAGE VIFB Regulation voltage at IFB Measured on VIFB(min), other IFB voltages are 0.5 V above VIFB(min). IIFB = 130 mA, VIFBV = 0.5 V IIFBV IFB Regulation voltage setting sourcing current at IFBV VIFBV = 0.5 V VIFBV IFBV voltage setting range 508 0.247 0.25 mV 0.253 IISET 0.3 1 V BOOST REFERENCE VOLTAGE VREF Reference voltage range for boost controller 0 3.1 V IREF_LEAK Leakage current at REF pin –25 25 nA OSCILLATOR VFSW FSW pin reference voltage VFSW_H Logic high input voltage VFSW_L Logic low input voltage 1.8 V 3.5 V 0.5 V ERROR AMPLIFIER ISINK Comp pin sink current VOVP = VREF + 200 mV, VCOMP = 1 V ISOURCE Comp pin source current VOVP = VREF – 200 mV, VCOMP = 1 V GmEA Error amplifier transconductance REA Error amplifier output resistance 20 µA 20 90 120 µA 150 20 µS MΩ GATE DRIVER RGDRV(SRC) Gate driver impedance when sourcing VDD = 6 V, IGDRV = –20 mA 2 3 Ω RGDRV(SNK) Gate driver impedance when sinking VDD = 6 V, IGDRV = 20 mA 1 1.5 Ω IGDRV(SRC) Gate driver source current VGDRV = 5 V 200 IGDRV(SNK) Gate driver sink current VGDRV = 1 V 400 VISNS(OC) Overcurrent detection threshold VIN = 8 V to 30 V, TJ = 25°C to 125°C 376 400 424 mA mA mV OVERVOLTAGE PROTECTION (OVP) VOVPTH Output voltage OVP threshold 2.95 3.02 3.09 V IOVP Leakage current –100 0 100 nA VIFB_OVP IFBx over voltage threshold PWM ON 38 V LED SHORT DETECTION LED short detection sourcing current IFBP VFBP = 1 V 0.247 0.25 0.253 IISET FAULT INDICATOR IFLT_H Leakage current in high impedance VFLT = 24 V IFLT_L Sink current at low output VFLT = 1 V 1 1 nA 2 mA THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold 150 °C Thys Thermal shutdown threshold hysteresis 15 °C 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT kHz ƒSW Switching frequency RFSW = 200 kΩ 187 200 213 Dmax Maximum duty cycle ƒSW = 200 kHz 90% 94% 98% ton(min) Minimum pulse width fEA Error amplifier crossover frequency 200 ns 1000 kHz Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 7 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 6.7 Typical Characteristics 16 Total LED Average Current (mA) Total LED Average Current (mA) 800 700 600 100 Hz Dimming 500 400 300 1 kHz Dimming 200 100 0 0 10 20 30 40 50 60 70 80 PWM Dimming Duty Cycle (%) 90 12 100 Hz Dimming 10 8 1 kHz Dimming 6 4 2 0 100 900 0.95 800 0.9 700 Frequency (kHz) 0.85 0.8 0.75 0.7 0.65 0.5 0 0.4 0.6 0.8 1 1.2 1.4 1.6 PWM Dimming Duty Cycle (%) 1.8 2 G004 600 500 400 300 200 VIN = 24 V, 16 LEDs VIN = 24 V, 20 LEDs VIN = 12 V, 16 LEDs 0.55 0.2 Figure 2. Dimming Linearity at Low Dimming Duty Cycle 1 0.6 0 G003 Figure 1. Dimming Linearity Efficiency (%) 14 100 200 400 600 800 1000 1200 1400 1600 1800 2000 Output Current (mA) G001 0 0 Figure 3. DC Load Efficiency 50 100 150 200 250 300 Resistance (kΩ) 350 400 450 G005 Figure 4. Switching Frequency Setting Minimum Headroom Voltage (mV) 1000 900 SW 50 V/div 800 700 600 VOUT (AC) 200 mV/div 500 400 300 Inductor Current 1 A/div 200 100 0 0 50 100 150 200 250 300 LED Current (mA) 350 400 450 G006 Figure 5. Recommended Minimum Headroom Voltage 8 Submit Documentation Feedback 4 µs/div G007 Figure 6. Boost Switching Waveform Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 Typical Characteristics (continued) EN 5 V/div EN 5 V/div IFB1 10 V/div IFB1 5 V/div VOUT 20 V/div VOUT 20 V/div IIN 1 A/div IIN 1 A/div 40 ms/div 40 ms/div G008 1% Dimming G009 100% Dimming Figure 7. Start-up Waveform Figure 8. Start-up Waveform SW 50 V/div SW 50 V/div IFB1 10 V/div IFB1 10 V/div VOUT (AC) 200 mV/div VOUT (AC) 200 mV/div ILED 100 mA/div ILED 100 mA/div 10 µs/div 20 µs/div G010 0.1% Dimming G011 2% Dimming Figure 9. Dimming Waveform Figure 10. Dimming Waveform EN 5 V/div EN 5 V/div IFB1 10 V/div IFB1 10 V/div VOUT 20 V/div VOUT 20 V/div ILED 100 mA/div ILED 100 mA/div 2 s/div 2 s/div G012 1% Dimming G013 100% Dimming Figure 11. Shutdown Waveform Figure 12. Shutdown Waveform Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 9 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com Typical Characteristics (continued) Fault 5 V/div Fault 5 V/div IFB1 10 V/div IFB1 10 V/div VOUT 20 V/div VOUT 20 V/div ILED 100 mA/div ILED 100 mA/div 10 ms/div 10 ms/div G014 1% Dimming Figure 13. LED Open Protection Figure 14. LED Open Protection Fault 5 V/div Fault 5 V/div IFB1 10 V/div IFB1 10 V/div VOUT 20 V/div VOUT 20 V/div ILED 100 mA/div ILED 100 mA/div 2 ms/div 100 µs/div G016 G017 100% Dimming 1% Dimming Figure 16. LED Short Protection Figure 15. LED Short Protection Fault 5 V/div Fault 5 V/div IFB1 10 V/div IFB1 500 mV/div VOUT 20 V/div VOUT 20 V/div ILED 100 mA/div ILED 100 mA/div 20 ms/div 20 ms/div G018 1% Dimming G019 100% Dimming Figure 17. IFB Short-to-Ground Protection 10 G015 100% Dimming Figure 18. IFB Short-to-Ground Protection Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 7 Detailed Description 7.1 Overview The TPS61196 provides a highly integrated solution for LCD TV backlight with an independent PWM dimming function for each string. This device is a current mode boost controller driving up to six WLED strings with multiple LEDs in series. Each string has an independent current regulator providing a LED current adjustable from 50 mA to 400 mA within ±1.5% matching accuracy. The minimal voltage at the current sink is programmable in the range of 0.3 V to 1 V to fit with different LED current settings. The input voltage range for the device is from 8 V to 30 V. 7.2 Functional Block Diagram L1 IN C1 VIN FAULT VDD C2 C3 LDO EN Protection Logic D1 OUT R1 VDD UVLO PWM Logic GDRV Driver R2 FSW R7 ISNS Oscillator and Slope Compensation R5 C5 COMP PGND OVP Protection R8 OC Protection VDD EA C6 400mV R3 3.0V OVP Iss REF EA 6 Min IFB Selection C7 IFB Protection R10 Current Mirror & REF FBP ISET PWM1 PWM2 PWM3 Dimming Control R9 R4 IFB1 IFBV R11 C4 R6 EA EN Current Sink AGND Current Sink IFB2 Current Sink PWM4 Current Sink PWM5 Current Sink PWM6 Current Sink IFB3 IFB4 IFB5 IFB6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 11 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 7.3 Feature Description 7.3.1 Supply Voltage The TPS61196 has a built-in linear regulator to supply the device analog and logic circuitry. The VDD pin, output of the regulator, must be connected to a 1-µF bypass capacitor. VDD only has a current sourcing capability of 15 mA. VDD voltage is ready after the EN pin is pulled high. 7.3.2 Boost Controller The TPS61196 regulates the output voltage with current mode pulse width modulation (PWM) control. The control circuitry turns on an external switch FET at the beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as the inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current rises to the threshold set by the Error Amplifier (EA) output, the switch FET is turned off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats each switching cycle. The switching frequency is programmed by an external resistor. A ramp signal from the oscillator is added to the current ramp to provide slope compensation, shown in Figure 23. The duty cycle of the converter is then determined by the PWM Logic block which compares the EA output and the slope compensated current ramp. The feedback loop regulates the OVP pin to a reference voltage generated by the minimum voltage across the IFB pins. The output of the EA is connected to the COMP pin. An external RC compensation network must be connected to the COMP pin to optimize the feedback loop for stability and transient response. The TPS61196 consistently adjusts the boost output voltage to account for any changes in LED forward voltages. In the event that the boost controller is not able to regulate the output voltage due to the minimum pulse width (ton(min), in the Electrical Characteristics), the TPS61196 enters pulse skip mode. In this mode, the device keeps the power switch off for several switching cycles to prevent the output voltage from rising above the regulated voltage. This operation typically occurs in light load condition or when the input voltage is higher than the output voltage. 7.3.3 Switching Frequency The switching frequency is programmed between 100 kHz to 800 kHz by an external resistor (R9 in Figure 23). To determine the resistance by a given frequency, use the curve in Figure 4 or calculate the resistance value by Equation 1. Table 1 shows the recommended resistance values for some switching frequencies. 40000 fSW = (kHz ) R9 (1) Table 1. Recommended Resistance Values For Switching Frequencies R9 ƒSW 400 k 100 kHz 200 k 200 kHz 100 k 400 kHz 80 k 500 kHz 48 k 800 kHz 7.3.4 Enable and Undervoltage Lockout The TPS61196 is enabled with the soft start-up when the EN pin voltage is higher than 1.8 V. A voltage of less than 1 V disables the device. An undervoltage lockout (UVLO) protection feature is provided. When the voltage at the VIN pin is less than 6.5 V, the TPS61196 is powered off. The TPS61196 resumes the operation once the voltage at the VIN pin recovers above the hysteresis (VVIN_HYS) more than the UVLO threshold of input falling voltage. If a higher UVLO voltage is required, use the UVLO pin as shown in Figure 19 to adjust the input UVLO threshold by using an external resistor divider. Once the voltage at the UVLO pin exceeds the 1.229-V threshold, the device is powered on, and 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 a hysteresis current source of 3.9 µA is added. When the voltage at the UVLO pin drops lower than 1.229 V, the current source is removed. The resistors of R1, R2, and R5 can be calculated by Equation 2 from required VSTART and VSTOP. To avoid noise coupling, the resistor divider R1 and R2 must be close to the UVLO pin. Placing a filter capacitor of more than 10 nF as shown in Figure 19 can eliminate the impact of the switching ripple and improve the noise immunity. If the UVLO function is not used, pull up the UVLO pin to the VDD pin. VIN R5 IHYS R1 C4 UVLO Enable R2 1.229V UVLO Comparator Figure 19. Undervoltage Lockout Circuit R1 + R5 = VSTART - VSTOP IHYS R2 = (R1 + R5) ´ 1.229V VSTART - 1.229V where • IHYS is 3.9 µA sourcing current from the UVLO pin. (2) When the UVLO condition happens, the FAULT pin outputs high impedance. As long as the UVLO condition removes, the FAULT pin outputs low impedance. 7.3.5 Power-up Sequencing and Soft Start-up The input voltage, UVLO pin voltage, EN input signal and the input dimming PWM signal control the power up of the TPS61196. After the input voltage is above the required minimal input voltage of 7.5 V, the internal circuit is ready to be powered up. After the UVLO pin is above the threshold of 1.229 V and the EN signal is high, the internal LDO and logic circuit are activated. The device outputs a 20-ms pulse to detect the unused channels and remove them from the control loop. When any PWM dimming signal is high, the soft start-up begins. If the PWM dimming signals come before the EN signal is high, the soft start-up begins immediately after the detection of unused channels. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 13 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com VIN Rising Threshold Falling Threshold UVLO EN 40μs VDD PWMx FAULT REF Voltage = OVP Voltage REF VOUT Switching Unused Channel Detection IFBx 200μs 20ms Figure 20. Power-Up Sequencing The TPS61196 has integrated the soft-start circuitry working with an external capacitor at the REF pin to avoid inrush current during start-up. During the start-up period, the capacitor at the REF pin is charged with a soft-start current source. When the REF pin voltage is higher than the output feedback voltage at the OVP pin, the boost controller starts switching and the output voltage starts to ramp up. At the same time, the LED current sink starts to drive the LED strings. At the beginning of the soft start, the charge current is 200 µA. Once the voltage of the REF pin exceeds 2 V, the charge current changes to 10 µA and continues to charge the capacitor. When the current sinks are driving the LED strings, the IFB voltages are monitored. When the minimum IFB voltage is above 200 mV less than the setting voltage at the IFBV pin, the charge current is stopped, and the soft start-up is finished. The TPS61196 enters normal operation to regulate the minimum IFB voltage to the required voltage set by the resistor at the IFBV pin. The total soft start time is determined by the external capacitance. The capacitance must be within 1 µF to 4.7 µF for different start-up time and different output voltage. 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 UVLO VIN EN PWM Dimming 200uA Charging Current 10uA Charging Current Soft Startup Done VIFB (min)>VIFBV – 200mV VREF =2V Dimming Off (VOUT = VIN – VD) 15ms 200ms VOUT Figure 21. Soft-Start Waveforms 7.3.6 Unused LED String If the application requires less than six LED strings, the TPS61196 simply requires connecting the unused IFB pin to ground through a resistor between 20 kΩ and 36 kΩ. Once the TPS61196 is turned on, the TPS61196 uses a 60-µA current source to detect the IFB pin voltage. If the IFB voltage is between 1 V and 2.5 V, the device immediately disables this string during start-up. 7.3.7 Current Regulation The six channel current sink regulators can be configured to provide up to 400 mA per string. The expected LED current is programmed by a resistor (R11 in Figure 23) at the ISET using Equation 3. V ILED = ISET ´ KISET R11 where • • VISET is the ISET pin voltage of 1.229 V KISET is the current multiple of 3992. (3) To sink the set LED current, the current sink regulator requires a minimum headroom voltage at the IFB pins for working properly. For example, when the LED current is set to 130 mA, the minimum voltage required at the IFB pin must be higher than 0.35 V. For other LED currents, refer to Figure 5 for recommended minimum headroom voltage required. The TPS61196 regulates the minimum voltage of the IFB pins to the IFBV voltage. The IFBV voltage is adjustable with an external resistor (R10 in the Figure 23) at the IFBV pin. After choosing the minimum IFB voltage, the IFBV voltage must be set to this value and the setting resistance can be calculated by Equation 4. R10 VIFBV = ´ 307.3 (mV ) (4) R11 If a large LED current is set, the headroom voltage is required higher. This leads to more heat on the device. To maintain the total power dissipation in the range of the package limit, normally all strings can not sink large current in continuous mode but pulse mode. The backlight of an active shutter glass 3-D TV may work with large LED current in pulse mode. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 15 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 7.3.8 PWM Dimming LED brightness dimming is set by applying an external PWM signal of 90 Hz to 22 kHz to the PWM pins. Each LED string has an independent PWM input. Varying the PWM duty cycle from 0% to 100% adjusts the LED from minimum to maximum brightness respectively. The recommended minimum on time of the LED string is 10 µsec. Thus, the device has a minimum dimming duty cycle of 500:1 at 200 Hz. When all PWM voltages are pulled low during dimming off, the TPS61196 turns off the LED strings and keeps the boost converter running at PFM mode. The output voltage is kept at the level which is a little bit lower than that when PWM is high. Thus, the device limits the output ripple due to the load transient that occurs during PWM dimming. When all PWM voltages are pulled low for more than 20 ms, to avoid the REF pin voltage dropping due to the leakage current, the voltage of the REF pin is held by an internal reference voltage which equals to the REF pin voltage in normal dimming operation. Thus, the output voltage will be kept at the same level as the normal output voltage. Since the output voltage in long time dimming off status is almost the same as the normal voltage for turning the LED on, the TPS61196 turns on the LED very fast without any flicker when recovering from long time dimming off to small duty cycle dimming on. 7.4 Device Functional Modes 7.4.1 Protections The TPS61196 has a full set of protections making the system safe to any abnormal conditions. Some protections will latch the TPS61196 in off state until its power supply is recycled or it is disabled and then enabled again. In latch off state, the REF pin voltage is discharged to 0 V. 7.4.1.1 Switch Current Limit Protection Using the ISNS Pin The TPS61196 monitors the inductor current through the voltage across a sense resistor (R7 in the Figure 23) in order to provide current limit protection. During the switch FET on period, when the voltage at the ISNS pin rises above 400 mV (VISNS in the Electrical Characteristics table), the TPS61196 turns off the FET immediately and does not turn it back on until the next switch cycle. The switch current limit is equal to 400 mV / R7. 7.4.1.2 LED Open Protection When one of the LED strings is open, the voltage at the IFB pin connecting to this LED string drops to zero during dimming-on time. The TPS61196 monitors the IFB voltage for 20 ms. If the IFB voltage is still below the threshold of 0.2 V, the current sink is disabled and an internal pull-up current is activated to detect the IFB voltage again. If the IFB voltage is pulled up to a high voltage, this LED string is recognized as LED open. As a result, the device deactivates the open IFB pin and removes it from the voltage feedback loop. Afterwards, the output voltage returns to the voltage required for the connected LED strings. The IFB pin currents of the connected strings remain in regulation during this process. If all the LED strings are open, the TPS61196 is latched off. 7.4.1.3 LED Short-Cross Protection Using the FBP Pin If one or several LEDs short in one string, the corresponding IFB pin voltage rises but continues to sink the LED current, causing increased device power dissipation. To protect the device, the TPS61196 provides a programmable LED short-across protection feature by properly sizing the resistor on the FBP pin (R12 in Figure 23) using Equation 5. R12 VLED _ SHORT = ´ 1.229V (5) R11 If any IFB pin voltage exceeds the threshold (VLED_SHORT), the device turns off the corresponding current sink and removes this IFB pin from the output voltage regulation loop. Current regulation of the remaining IFB pins is not affected. 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 Device Functional Modes (continued) 7.4.1.4 Schottky Diode Open Protection When the device is powered on, it checks the topology connection first. After the TPS61196 delays 400 µs, it checks the voltage at the OVP pin to see if the Schottky diode is not connected or the boost output is hardshorted to ground. If the voltage at the OVP pin is lower than 70 mV, the TPS61196 is locked in off state until the input power is recycled or it is enabled again. 7.4.1.5 Schottky Diode Short Protection If the rectifier Schottky diode is shorted, the reverse current from output capacitor to ground is very large when the switcher MOSFET is turned on. Because the current mode control topology has a minimum edge blanking time to immunize against the spike current through the switcher, if the parasite inductance between the output capacitor through the switcher to ground is zero, the external MOSFET will be damaged in this short period due to the huge power dissipation in this case. But with a small parasite inductance, the power dissipation is limited. The boost converter works in minimum pulse width in this situation due to cycle by cycle over-current protection. The output voltage drops and the all-string-open protection is triggered because of the low voltage at all IFB pins. The TPS61196 is latched off. 7.4.1.6 IFB Overvoltage Protection During Start-up When any of IFB pins reaches the threshold (VOVP_IFB) of 38 V during start-up, the device stops switching and stays in latch-off immediately to protect from damage. In latch-off state, the REF pin voltage is discharged. 7.4.1.7 Output Overvoltage Protection Using the OVP Pin Use a resistor divider to program the maximum output voltage of the boost converter. To ensure the LED string can be turned on with setting current, the maximum output voltage must be higher than the forward voltage drop of the LED string. The maximum required voltage can be calculated by multiplying the maximum LED forward voltage (VFWD(max)) and number (n) of series LEDs , and adding extra 1 V to account for regulation and resistor tolerances and load transients. The recommended bottom feedback resistor of the resistor divider (R4 in Figure 23) is 10 kΩ. Calculate the top resistor (R3 in the Figure 23) using Equation 6, where VOVP is the maximum output voltage of the boost converter. æV ö R3 = ç OVP - 1÷ ´ R4 è 3.02 ø (6) When the device detects that the voltage at the OVP pin exceeds overvoltage protection threshold of 3.02 V, indicating that the output voltage has exceeded the clamp threshold voltage, the TPS61196 clamps the output voltage to the set threshold. When the OVP pin voltage does not drop from the OVP threshold for more than 500 ms, the device is latched off until the input power or the EN pin voltage is re-cycled. 7.4.1.8 Output Short-to-Ground Protection When the inductor peak current reaches twice the switch current limit in each switching cycle, the device immediately disables the boost controller until the fault is cleared. This protects the device and external components from damage if the output is shorted to ground. 7.4.1.9 IFB Short-to-Ground Protection The IFB pin short to ground makes the LED current uncontrollable if there is no protection. If the device tries to increase the boost converter’s output voltage to lift the IFB voltage, it will make the situation worse and the LED string may be burned due to the high current. The TPS61196 implements a protection mechanism to protect the LED string in this failure mode. If the IFB is short to ground before the TPS61196 is turned on, the device detects the IFB voltage by sourcing a 60 µA current during start-up. If the IFB voltage is less than 0.4 V during start-up, the start-up stops and the device outputs fault indication so as to protect the LED string during start-up. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 17 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com Device Functional Modes (continued) When a LED feedback pin is shorted to ground during normal operation, the device first turns off this LED string for a very short time and detects the IFB voltage again. If the IFB voltage is lower than 1.8 V, it sources a 60-µA current and detects the IFB voltage again in off state. If the IFB voltage is still less than 1.8 V, this means the IFB pin is shorted to ground. The boost converter is turned off and the REF voltage is discharged to ground to protect the LED string. 7.4.1.10 ISET Short-to-Ground Protection The TPS61196 monitors the ISET pin voltage when the device is enabled. When the sourcing current from the ISET pin is larger than a threshold of 150 μA, the device disables the current sink because the ISET pin may be short to ground or the current setting resistor is too small. Once the current sourcing from the ISET pin recovers to the normal value, the current sink resumes working. 7.4.1.11 Thermal Protection When the device junction temperature is over 150°C, the thermal protection circuit is triggered and shuts down the device immediately. The device automatically restarts when the junction temperature falls back to less than 135°C, with approximate 15°C hysteresis. Table 2. Protection List PROTECTION ITEM RESULT FAULT LATCH OFF / RETRY Diode open Cannot start up Y Latch off Diode short Output voltage low Y Latch off LED string open LED string off Y LED string latch off LED string short during start-up IFB OVP Y Latch off LEDshort LED string off Y LED string latch off IFB short to GND Boost off Y Latch off ISET short to GND All LED strings off Y Retry All LED strings open during start-up VOUT OVP Y Latch off Input voltage UVLO Boost off Y Retry Thermal shutdown Shutdown Y Retry 7.4.2 Indication For Fault Conditions The TPS61196 has an open-drain fault indicator pin to indicate abnormal conditions. When the device is operating normally, the voltage at the FAULT pin is low. When any fault condition happens, it is in high impedance, which can be pulled to high level through an external resistor. The FAULT pin can indicate following conditions: • Overvoltage condition at the OVP or the IFB pin • LED short and open • IFB short to ground • ISET short to ground • Diode open and short • Output short circuit • Overtemperature 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information When more LED strings are required in the application, the TPS61196 can work in master/slave mode. The TPS61196 can be set as slave device when the voltage at the FSW pin is below 0.5 V or above 3.5 V. The master TPS61196 has booster controller and outputs the power rail for all LED strings. The slave TPS61196 only works as a LED driver and feedbacks the required headroom voltage to the master by connecting the slave's COMP pin to the master's REF pin. The ISNS pin of the slave TPS61196 must be connected to ground. The slave's OVP pin voltage must be 3% higher than the voltage at the master's OVP pin. The slave device can combine all fault conditions happening on both master and slave devices by connecting the master's FAULT output to the FSW pin of the slave device. The slave’s FAULT pin outputs the indication signal for all fault conditions. L1 68uH 8V to 30V D1 C1 EC1 100μF EC2 100μF 10μF R15 C2 2.2μF R5 R3 8V to 30V VIN VIN R14 GDRV GDRV ISNS ISNS R6 C5 R1 C4 10nF UVLO R2 VDD TPS61196 MASTER PGND R7 R4 UVLO VDD OVP TPS61196 SLAVE OVP COMP C3 1.0μF PGND COMP R8 FSW R9 REF EN FSW REF C6 EN C7 PWM1 IFB1 PWM1 IFB1 …... …... …... …... VDD PWM6 IFB6 R13 PWM6 IFB6 IFBV FAULT IFBV FBP AGND R12 R10 ISET FBP FAULT AGND ISET R11 Figure 22. Multi-Chip Operation In Parallel Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 19 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 8.2 Typical Application L1 68mH VIN = 24V D1 C1 EC1 100mF EC2 100mF 10mF R19 3 VIN R5 200k C4 10nF R1 182k ISNS UVLO PGND TPS61196 R2 24.9k VDD R3 255k Q1 GDRV C2 2.2mF R6 200 R4 10k R7 0.1 C5 470pF OVP COMP C3 1.0mF FSW REF C7 EN R9 200k R8 150k C8 160pF C6 47nF 2.2mF FAULT IFB1 IFB2 PWM1 IFB3 PWM2 IFB4 PWM3 IFB5 PWM4 IFB6 PWM5 IFBV PWM6 FBP ISET Thermal pad AGND R11 37.4k R12 196k R10 60.4k C9 0.1mF R13 R14 R15 R16 R17 R18 10M 10M 10M 10M 10M 10M Figure 23. TPS61196 Typical Application 8.2.1 Design Requirements 8.2.1.1 Design Requirements DESIGN PARAMETER EXAMPLE VALUE Input voltage range 10 V – 15 V LED forward voltage range 56 V - 64 V Number of LED strings × number of LEDs per string 6 x 20 LED string current 150 mA per channel Switching frequency 500 kHz 8.2.2 Detailed Design Procedure 8.2.2.1 Inductor Selection The inductor is the most important component in switching power regulator design because it affects power supply steady state operation, transient behavior, and loop stability. The inductor value, DC resistance (DCR), and saturation current are important specifications to be considered for better performance. Although the boost power stage can be designed to operate in discontinuous mode at maximum load, where the inductor current ramps down to zero during each switching cycle, most applications will be more efficient if the power stage operates in continuous conduction mode, where a DC current flows through the inductor. Therefore, the Equation 8 and Equation 9 below are for CCM operation only. The TPS61196 is designed to work with inductor values between 10 µH and 100 µH, depending on the switching frequency. Running the controller at higher switching frequencies allows the use of smaller and/or lower profile inductors in the 10-µH range. Running the controller at slower switching frequencies requires the use of larger inductors, near 100 µH, to maintain the same inductor current ripple but may improve overall efficiency due to smaller switching losses. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the 0-A value depending on how the inductor vendor defines saturation. In a boost regulator, the inductor DC current can be calculated with Equation 7. V ´ IOUT IL(DC) = OUT VIN ´ η where • • 20 VOUT = boost output voltage IOUT = boost output current Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 • • VIN = boost input voltage η = power conversion efficiency, use 95% for TPS61196 applications (7) The inductor current peak-to-peak ripple can be calculated with Equation 8. VIN ´ (VOUT - VIN ) DIL(P -P) = L ´ fSW ´ VOUT where • • • • • ΔIL(P-P) = inductor ripple current L = inductor value fSW = switching frequency VOUT = boost output voltage VIN = boost input voltage (8) Therefore, the inductor peak current is calculated with Equation 9. DIL(P -P) IL(P) = IL(DC) + 2 (9) Select an inductor, which saturation current is higher than calculated peak current. To calculate the worst-case inductor peak current, use the minimum input voltage, maximum output voltage, and maximum load current. Regulator efficiency is dependent on the resistance of its high current path and switching losses associated with the switch FET and power diode. Besides the external switch FET, the overall efficiency is also affected by the inductor DCR. Usually the lower DC resistance shows higher efficiency. However, there is a trade-off between DCR and the inductor footprint; furthermore, shielded inductors typically have higher DCR than unshielded ones. 8.2.2.2 Schottky Diode The TPS61196 demands a high-speed rectification for optimum efficiency. Ensure that the diode's average and peak current rating exceed the output LED current and inductor peak current. In addition, the diode's reverse breakdown voltage must exceed the application output voltage. 8.2.2.3 Switch MOSFET and Gate Driver Resistor The TPS61196 demands a power N-MOSFET (see Q1 in the Figure 23) as a switch. The voltage and current rating of the MOSFET must be higher than the application output voltage and the inductor peak current. The applications benefit from the addition of a resistor (See R19 in the Figure 23) connected between the GDRV pin and the gate of the switch MOSFET. With this resistor, the gate driving current is limited and the EMI performance is improved. A 3-Ω resistor value is recommended. The TPS61196 exhibits lower efficiency when the resistor value is above 3 Ω due to the more switching loss of the external MOSFET. 8.2.2.4 Current Sense and Current Sense Filtering R7 determines the correct overcurrent limit protection. To choose the right value of R7, start with the total system power needed POUT, and calculate the input current IIN by Equation 7. Efficiency can be estimated between 90% to 95%. The second step is to calculate the inductor peak current based on the inductor value L using Equation 8 and Equation 9. The maximum R7 can now be calculated as R7(max) = VISNS / IL(P). It is recommended to add 20% or more margins to account for component variations. A small filter placed on the ISNS pin improves performance of the converter (See R6 and C5 in Figure 23). The time constant of this filter should be approximately 100 ns. The range of R6 should be from about 100 Ω to 1 kΩ for best results. The C5 should be located as close as possible to the ISNS pin to provide noise immunity. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 21 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 8.2.2.5 Output Capacitor The output capacitor is mainly selected to meet the requirements for output ripple and loop stability of the whole system. This ripple voltage is related to the capacitance of the capacitor and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by: I ´ DMAX VRIPPLE(C) = OUT fSW ´ COUT where • • VRIPPLE is the peak to peak output voltage ripple DMAX is the duty cycle of the boost converter. (10) DMAX is approximately equal to (VOUT(MAX) – VIN(MIN) / VOUT(MAX)) in applications. Care must be taken when evaluating a capacitor’s derating under DC bias. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, leave the margin on the voltage rating to ensure adequate capacitance. The ESR impact on the output ripple must be considered as well if tantalum or aluminum electrolytic capacitors are used. Assuming there is enough capacitance such that the ripple due to the capacitance can be ignored, the ESR needed to limit the VRIPPLE is: VRIPPLE(ESR) = IL(P) ´ ESR (11) Ripple current flowing through a capacitor’s ESR causes power dissipation in the capacitor. This power dissipation causes a temperature increase internally to the capacitor. Excessive temperature can seriously shorten the expected life of a capacitor. Capacitors have ripple current ratings that are dependent on ambient temperature and should not be exceeded. Therefore, high ripple current type electrolytic capacitor with small ESR is used in typical application as shown in Figure 23. In the typical application, the output requires a capacitor in the range of 22 µF to 220 µF. The output capacitor affects the small signal control loop stability of the boost converter. If the output capacitor is below the range, the boost regulator may potentially become unstable. 8.2.2.6 Loop Consideration The COMP pin on the TPS61196 is used for external compensation, allowing the loop response to be optimized for each application. The COMP pin is the output of the internal trans-conductance amplifier. The external resistor R8, along with ceramic capacitors C6 and C8 (see in Figure 23), are connected to the COMP pin to provide poles and zero. The poles and zero, along with the inherent pole and zero in a peak current mode control boost converter, determine the closed loop frequency response. This is important to converter stability and transient response. The first step is to calculate the pole and the right half plane zero of the peak current mode boost converter by Equation 12 and Equation 13. 2IOUT fP = 2πVOUT ´ COUT (12) 2 fZRHP = VOUT ´ (1- D ) 2πL ´ IOUT (13) To make the loop stable, the loop must have sufficient phase margin at the crossover frequency where the loop gain is 1. To avoid the effect of the right half plane zero on the loop stability, choose the crossover frequency less than 1/5 of the ƒZRHP. Then calculate the compensation components by Equation 14 and Equation 15. R7 ´ 2 πfco ´ COUT V R8 = ´ OVP (1- D ) ´ GmEA VOVPTH where • • • 22 VOVPTH = 3.02 V which is the internal reference for the output overvoltage-protection setting voltage. GmEA is the trans-conductance of the error amplifier. Its typical value is 120 μS. ƒCO is the crossover frequency, which normally is less than 1/5 of the fZRHP Submit Documentation Feedback (14) Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 C6 = 1 2πfP ´ R8 where • ƒP is the pole’s frequency of the power stage calculated by Equation 12 (15) If the output capacitor is the electrolytic capacitor, which may have large ESR, a capacitor is required to cancel the zero of the output capacitor. Equation 16 calculates the value of this capacitor. ´ RESR C C8 = OUT R8 (16) 1 1 0.95 0.95 0.9 0.9 0.85 0.85 Efficiency (%) Efficiency (%) 8.2.3 Application Curves 0.8 0.75 20 LEDs (VOUT = 60 V) 200 Hz Dimming Frequency 0.7 0.65 16 LEDs (VOUT = 50 V) 200 Hz Dimming Frequency 0.7 0.65 0.6 0.6 VIN = 12 V VIN = 24 V 0.55 0.5 0.8 0.75 0 10 20 30 40 50 60 70 80 PWM Dimming Duty Cycle (%) 90 20 LEDs VIN = 12 V VIN = 24 V 0.55 100 0.5 0 10 20 G001 30 40 50 60 70 80 PWM Dimming Duty Cycle (%) 90 100 G002 16 LEDs Figure 24. Efficiency Figure 25. Efficiency 9 Power Supply Recommendations The TPS61196 requires a single supply input voltage. This voltage can range between 8 V to 30 V and be able to supply enough current for a given application. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 23 TPS61196 SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 www.ti.com 10 Layout 10.1 Layout Guidelines As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. The VDD capacitor, C3 (see Figure 23) is the filter and noise decoupling capacitor for the internal linear regulator powering the internal digital circuits. It should be placed as close as possible between the VDD and PGND pins to prevent any noise insertion to digital circuits. The switch node at the drain of Q1 carries high current with fast rising and falling edges. Therefore, the connection between this node to the inductor and the schottky diode should be kept as short and wide as possible. It is also beneficial to have the ground of the capacitor C3 close to the ground of the current sense resistor R7 since there is large driving current flowing between them. The ground of output capacitor EC2 should be kept close to input power ground or through a large ground plane because of the large ripple current returning to the input ground. When laying out signal grounds, it is recommended to use short traces separate from power ground traces and connect them together at a single point, for example on the thermal pad in the PWP package. Resistors R3, R4, R9, R10, R11, and R12 (see Figure 23) are setting resistors for switching frequency, LED current, protection threshold and feedback voltage programming. To avoid unexpected noise coupling into the pins and affecting the accuracy, these resistors need to be close to the pins with short and wide traces to GND. In the PWP package, the thermal pad needs to be soldered to the large ground plane on the PCB for better thermal performance. Additional thermal via can significantly improve power dissipation of the device. 10.2 Layout Example GND VIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TPS61196 GND UVLO EN PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 FBP ISET IFBV IFB1 IFB2 IFB3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VIN FAULT FSW VDD GDRV ISNS PGND REF COMP OVP AGND IFB6 IFB5 IFB4 GND D1 GND Bottom GND Plane VOUT GND Figure 26. Layout Example 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 TPS61196 www.ti.com SLVSBG1D – OCTOBER 2012 – REVISED MAY 2015 11 Device and Documentation Support 11.1 Trademarks PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPS61196 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS61196PWPR ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS61196 TPS61196PWPT ACTIVE HTSSOP PWP 28 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS61196 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of