Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
TPS6123x High Efficiency Synchronous Step Up Converters with 5-A Switches
1 Features
3 Description
•
•
•
The TPS6123x device family is a high efficiency
synchronous step up converter with compact solution
size. It is optimized for products powered by a onecell Li-Ion battery, or a regulated power rail of 3.3 V.
The IC integrates a 5-A switch and is capable of
delivering output currents up to 2.1 A at a 5-V output
with a 3.3-V input supply. The device is based on a
quasi-constant on-time valley current mode control
scheme. The typical operating frequency is 2 MHz,
which allows the use of small inductors and
capacitors to achieve a small solution size. The
TPS61230 and TPS61231 provide an adjustable
output voltage via an external resistor divider, and the
TPS61232 provides a fixed output voltage of 5 V.
1
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 2.3 V to 5.5 V
Output Voltage Range: 2.5 V to 5.5 V
Up to 96% Efficiency Synchronous Boost
Converter
3.3-V to 5-V Power Conversion with 2.1-A Output
Current
Input Supply Voltage Supervisor with Adjustable
Threshold/Hysteresis
Power Save Mode for Light Load Efficiency
Load Disconnect During Shutdown
Output Over Voltage Protection
Programmable Soft Start
Power Good Output
2-MHz Switching Frequency
Output Capacitor Discharge (TPS61231)
3 mm x 3 mm x 0.9 mm VSON Package
2 Applications
•
•
•
•
•
Low Voltage Li-Ion Battery Powered Products
USB Power Supply
Tablet PCs
Power Banks, Battery Backup Units
Industrial Metering Equipments
During light loads, the TPS6123x automatically enters
power save mode for maximum efficiency at lowest
quiescent currents. In shutdown, the load is
completely disconnected from the input, and the input
current consumption is reduced to 1.5 µA typical. The
device integrates a precise low power EN
comparator. The EN threshold as well as the
hysteresis of the enable comparator are adjustable
with external resistors and support application
specific system power up and down requirements.
Other features like output over voltage protection,
thermal shutdown protection, and a power good
output are built-in.
The devices are available in a 3 mm x 3 mm x 0.9
mm VSON package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS61230
TPS61231(2)
VSON (10)
3.00 mm x 3.00 mm
TPS61232
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
(2) Preview product. Contact TI factory for more information
TPS61230 Typical Application
TPS61230 Typical Application Efficiency
L1
1.0µH
C1
22µF
VIN
SW
EN
VOUT
HYS
C3
10nF
FB
SS
GND
90
VOUT
R1
402k
R2
100k
C2
3x22µF
Efficiency (%)
VIN
100
80
70
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
PG
TPS61230
R3
1.0Meg
Vout = 5.0 V
60
0.001
0.010
0.100
Iout (A)
1.000
C008
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 11
9
Applications and Implementation ...................... 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
11.3 Thermal Considerations ........................................ 21
12 Device and Documentation Support ................. 23
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support .......................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
Changes from Revision B (June 2014) to Revision C
•
Page
Changed Electrical Characteristics in the IQ row; VOUT = 3.5 V to VOUT = No Supply ........................................................... 5
Changes from Revision A (March 2014) to Revision B
Page
•
Added TPS61232 to the data sheet ...................................................................................................................................... 1
•
Changed the Device Information ........................................................................................................................................... 1
•
Changed the Device Comparison Table................................................................................................................................. 3
•
Changed the Handling Ratings table ..................................................................................................................................... 4
Changes from Original (September 2013) to Revision A
Page
•
Deleted TPS61232 from the data sheet ................................................................................................................................ 1
•
Changed the data sheet to the new TI format ....................................................................................................................... 1
•
Changed the Description From: input current consumption is reduced to 0.5 µA typical To: input current
consumption is reduced to 1.5 µA typical .............................................................................................................................. 1
•
Changed the Functional Block Diagram. Removed Note 2 ................................................................................................... 8
•
Deleted the Programming The Output Voltage section ....................................................................................................... 13
•
Changed Figure 14 label From: Startup (A) To: Startup (Ω) ................................................................................................ 15
2
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
5 Device Comparison Table
PART NUMBER
OUTPUT VOLTAGE
OUTPUT DISCHARGE
TPS61230DRC
Adjustable
No
Adjustable
Yes
5-V fixed output
No
TPS61231DRC
(1)
TPS61232DRC
(1)
Preview product. Contact TI factory for more information
6 Pin Configuration and Functions
11-PIN VSON
DRC PACKAGE
(Top View)
1
SW
VIN
10
2
SW
EN
9
3
VOUT
HYS
8
4
VOUT
FB
7
5
PG
SS
6
GND
11
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
SW
1,2
PWR
The switch pin of the converter. It is connected to the drain of the internal Power MOSFETs.
VOUT
3,4
PWR
Boost converter output pin.
PG
5
OUT
Power Good open drain output. Can be left floating if not used.
SS
6
IN
Soft startup pin. A soft startup capacitor connects to this pin to set the soft start time.
FB
7
IN
Voltage feedback of adjustable versions. Must be connected to VOUT on fixed output voltage version.
HYS
8
OUT
EN
9
IN
Enable logic input. Logic HIGH enables the device. Logic LOW disables the device and turns it into
shutdown mode. This pin must be terminated.
VIN
10
IN
Supply voltage pin.
GND
11
PWR
EN hysteresis program pin. See the application section for details. Can be left floating if not used.
Ground pin.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
3
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Voltage range at pins (2)
EN, FB, PG, SS, HYS, VIN, VOUT, SW
MIN
MAX
UNIT
–0.3
7
V
–40
150
°C
Operating junction temperature range, TJ
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground pin.
7.2 Handling Ratings
Tstg
Electrostatic
discharge
VESD
(1)
(2)
MIN
MAX
-65
150
°C
–2
2
kV
–500
500
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VIN
Supply voltage at VIN pin
ISINK_PG
Sink current at PG pin
VPG
Pull-up resistor voltage
TJ
Operating junction temperature
TYP
2.3
-40
MAX
UNIT
5.5
V
500
µA
5.5
V
125
°C
7.4 Thermal Information
TPS6123x
THERMAL METRIC (1)
DRC (11 PINS)
RθJA
Junction-to-ambient thermal resistance
49.1
RθJC(top)
Junction-to-case(top) thermal resistance
57.2
RθJB
Junction-to-board thermal resistance
26.6
ψJT
Junction-to-top characterization parameter
0.8
ψJB
Junction-to-board characterization parameter
23.8
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
4.5
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
7.5 Electrical Characteristics
TJ = –40°C to 125°C and VIN = 3.6 V. Typical values are at TJ = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN falling
2.0
2.1
VIN rising
2.1
2.2
IC enabled, No load, No switching
VOUT = 5 V, TJ = –40 °C to 85°C
35
60
IC enabled, No load
VIN = 4.2 V, VOUT = No supply, TJ = –40 °C to
85°C
200
230
Shutdown current into VIN
0 V ≤ VEN ≤ 0.4 V, VIN = 2.3 V to 5.5 V, TJ = -40
°C to 85°C
1.5
6
µA
Leakage current from SW to VOUT
VEN = 0 V, VOUT = 0 V; VSW = VIN = 3.6 V
2.5
µA
5.5
V
5.1
V
SUPPLY
VUVLO
IQ
Input under voltage lockout
Quiescent current into VIN
ISD
V
µA
OUTPUT
VOUT
Output voltage range
VOUT
Output voltage accuracy, TPS61232
2.5
PWM mode
4.9
(1)
5.0
VOUT
Output voltage accuracy, TPS61232
PFM mode
VFB
Feedback voltage, TPS61230 and
TPS61231
PWM mode
FB pin leakage current
VFB = 1 V
Output discharge resistor
TPS61231
VOUT = 5 V
Over voltage protection DC threshold
VOUT rising
Over voltage protection hysteresis
VOUT falling below VOVP
Bias current in soft start phase
After pre-charge phase
5
µA
Line regulation
IOUT = 1 A, VIN = 2.3 V to 4.5 V
0.06
%/V
Load regulation
IOUT = 0.5 A to 2 A
0.15
%/A
RDIS
VOVP
ISS
5.035
0.985
PFM mode (1)
1
V
1.015
1.007
100
6
nA
Ω
200
5.7
V
6.2
0.15
V
LOGIC INTERFACE
VTH_EN_ON
VTH_EN_OF
EN pin threshold rising
VIN = 2.3 V to 5.5 V
1.15
1.19
1.23
EN pin threshold falling
VIN = 2.3 V to 5.5 V
1.11
1.14
1.18
HYS pin low level voltage
ISINK_HYS = 1 mA, VEN = 1.1 V
VOUT rising, referenced to VOUT_NOMINAL
93%
95%
99%
VOUT falling referenced to VOUT_NOMINAL
87%
90%
93%
V
V
F
VOL_HYS
VTH_PG
Power good DC threshold
VOL_PG
PG pin low level voltage
0.7
ISINK_PG = 500 µA
V
0.4
V
A
POWER STAGE
ILIM_SW
Switch valley current limit
ILIM_Pre
Precharge current limit
RDS(on)
TJSD
(1)
4.0
5.0
6.0
VOUT = 5 V
2.0
2.8
3.5
VOUT = 3.5 V
1.8
2.6
3.3
VOUT = 0 V
0.4
0.55
0.7
High side MOSFET on resistance
VOUT = 5 V
50
75
Low side MOSFET on resistance
VOUT = 5 V
50
75
Thermal shutdown threshold
TJ rising
150
Thermal shutdown hysteresis
TJ falling below TJSD
20
A
mΩ
°C
L = 1 µH, COUT = 20 µF (effective capacitance value)
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
5
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
7.6 Typical Characteristics
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
70
LS FET On Resistance (m:)
HS FET On Resistance (m:)
70
60
50
40
30
50
40
30
-40
-20
0
20
40
60
80
100
120
Junction Temperature (C)
-40
-20
0
20
40
60
80
100
120
Junction Temperature (C)
C001
Figure 1. High-Side MOSFET On Resistance vs Junction
Temperature
C002
Figure 2. Low-Side MOSFET On Resistance vs Junction
Temperature
1.010
2.20
Vin UVLO Threshold (V)
Voltage Reference (V)
60
1.005
1.000
0.995
2.00
VIN
VIN Rising
VIN Falling
VIN
0.990
-40
-20
0
20
40
60
80
100
120
Junction Temperature (C)
1.80
±40
C003
Figure 3. Voltage Reference vs Junction Temperature
0
20
40
60
100
120
C013
Figure 4. Vin UVLO Threshold vs Junction Temperature
Quiescent Current (PA)
50
1.20
40
30
oC
85C
Tj = 85
EN Rising
oC
25C
Tj = 25
oC
Tj = -40
-40C
EN Falling
1.10
20
±40
±20
0
20
40
60
80
Junction Temperature (oC)
100
120
Submit Documentation Feedback
2
3
4
Input Voltage (V)
C014
Figure 5. EN Logic Threshold vs Junction Temperature
6
80
Junction Temperature (oC)
1.30
EN Logic Threshold (V)
±20
5
C010
Figure 6. Quiescent Current vs Input Voltage (Boost Mode)
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
Typical Characteristics (continued)
VIN = 3.6 V, VOUT = 5.0 V, TJ = -40°C to 125 °C, unless otherwise noted.
5.0
Switch Valley Current Limit (A)
Shutdown Current (PA)
4
3
2
1
Tj = 85C
85oC
Tj = 25C
25oC
-40oC
Tj = -40C
0
2
3
4
4.8
4.6
4.4
Tj
Tj == 125C
125oC
4.2
Tj
Tj==25C
25oC
Tj==-40C
-40oC
Tj
4.0
2
5
Input Voltage (V)
3
4
5
Input Voltage (V)
C011
Figure 7. Shutdown Current vs Input Voltage (Boost Mode)
C012
Figure 8. Switch Valley Current Limit vs Input Voltage
(Boost Mode)
Softstart Charge Current (PA)
5.1
5.0
4.9
4.8
4.7
4.6
4.5
±40
±20
0
20
40
60
80
100
120
Junction Temperature (oC)
C015
Figure 9. Soft Start Charge Current vs Junction Temperature
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
7
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
8 Detailed Description
8.1 Overview
The TPS6123x synchronous step-up converter typically operates at a quasi-constant 2-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6123x converter
operates in power-save mode with pulse frequency modulation (PFM). The converter uses a novel quasiconstant on-time valley current mode control scheme which provides excellent transient line / load response with
minimal output capacitance. Internal loop compensation simplifies the design process while minimizing the
number of external components. The TPS6123x device can smoothly transit in and out of zero duty cycle mode
(high side FET full on). Therefore the output can be kept as close as possible to its regulation limits even though
the converter is subject to an input voltage that tends to be excessive.
8.2 Functional Block Diagram
SW
VIN
Supply for
logic circuitry
61230/1
VOUT
FB
EA
Over Voltage
Protection
VOUT
61232
2)
REF
VOUT
Pulse
Modulator
Valley
Current
Sense
Gate
Driver
1)
EN
EN
Threshold/
Hysteresis
ON/
OFF
Thermal
Shutdown
EN
OVP
PG Comparator
PG
FB
HYS
REF
Logic
REF
EN Comparator
Softstart
SS
Undervoltage
Lockout
GND
(1)
Output discharge block is implemented in TPS61231 only.
(2)
Internal resistor divider is implemented in TPS61232 only. For adjustable output versions, the FB pin is directly
connected to the negative pin of the EA.
8.3 Feature Description
8.3.1 Startup
In boost mode (PWM or PFM), the rectifying switch is turned on first until the output capacitor is charged to 0.5 V
with the current limit of 550 mA after the device is enabled. Then, the output capacitor is continuously charged to
a value close to the input voltage. This is called the pre-charge phase. During the pre-charge phase, the output
current is limited by the pre-charge current limit of the high side rectifying switch and the SS pin voltage follows
the FB voltage (in the TPS61232, the SS pin follows the internal FB voltage). Once the output capacitor has
been biased to the input voltage, the device starts switching. This is called the soft start phase. During the soft
8
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
Feature Description (continued)
start phase, the SS pin voltage limits the FB pin voltage, and the output voltage rising slope follows the SS pin
voltage slope. The capacitor connected to the SS pin is charged by the internal bias current of ISS, giving the time
of the soft start phase shown in Equation 1. The larger the soft start capacitor, the longer the soft start phase
time. Leaving the SS pin floating sets the minimum soft startup phase time. The device finishes the soft start
phase and operates normally when the nominal output voltage is reached.
t SS =
æ
C SS
V IN
´ çç 1 5mA è
VO U T
ö
÷÷ ´ V R E F
ø
(1)
The SS pin voltage is discharged in the cases when the device gets disabled by the EN pin, thermal shutdown
and undervoltage lockout. The SS pin may be left floating to disable the soft start phase and start up with the
fastest time. In zero duty cycle mode, only the pre-charge phase works during startup.
8.3.2 Current Limit Operation
The device employs a valley current sensing scheme. Switch valley current limit detection occurs during the off
time through sensing of the voltage drop across the synchronous rectifier. If the current is above the valley
current limit level when it is time to turn off the synchronous rectifier, the device instead keeps the synchronous
rectifier on until its current decreases below the valley current limit level. The maximum continuous output current
IOUT(MAX), before entering switch valley current limit operation, is defined by Equation 2.
1
ö
æ
IOUT(MAX ) = (1 - D) ´ ç ILIM _ SW + DIL ÷
2
ø
è
D=
VOUT - VIN
VOUT
DIL =
VIN
D
´
L
fSW
(2)
Where
ILIM_SW = Switch valley current limit
L = Inductor value
fSW = Switching frequency
When the switch current limit is reached, the output voltage decreases from further load increase. The switch
valley current limit works in PWM, PFM and Zero Duty Cycle Mode operations.
Another current limit scheme, pre-charge current limit, ILIM_Pre is implemented. Pre-charge current limit detection
works when VOUT < VOUT_NOM and VOUT < VIN . It can happen when the device is in the pre-charge phase or an
over load condition. It impacts the minimum load resistance at startup as shown in Figure 14 and Figure 27.
8.3.3 Enable/Disable
The EN pin is connected to an ON/OFF detector (ON/OFF) and an input of the Enable Comparator, shown in the
functional block diagram. With a voltage level of 0.4 V or less at the EN pin, the ON/OFF detector turns the
device into Shutdown mode and the quiescent current is reduced to typically 1.5 uA. In this mode, the EN
comparator and the entire internal control circuitry are switched off. A voltage level of typically 0.9 V at the EN
pin triggers the ON/OFF detector and activates the internal reference, the EN comparator and the UVLO
comparator. Once the ON/OFF detector has tripped, the quiescent current into the VIN pin is typically 1.5 μA.
The TPS6123x starts regulation once the voltage at the EN pin trips the threshold VEN_TH_ON and the VIN pin
voltage is above the UVLO threshold. The device enters startup and ramps up the output voltage. The TPS6123x
stops regulation once the voltage on the EN pin falls blow the threshold VEN_TH_OFF or the VIN pin voltage falls
below the UVLO threshold. For proper operation, The EN pin must be terminated and must not be left floating.
An external logic signal applied directly to the EN pin can enable/disable the device. The device can be driven
into shutdown mode by pulling the EN pin to GND. In this mode, true load disconnect between the battery and
load prevents current flow from VIN to VOUT, as well as reverse flow from VOUT to VIN.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
9
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Feature Description (continued)
8.3.4 Undervoltage Lockout
An under voltage lockout is implemented to avoid mis-operation of the device at low input voltages. It shuts down
the device with voltages lower than VUVLO.
Use the HYS pin to configure a new undervoltage lockout threshold and hysteresis shown in Figure 10 and
Equation 3. The new thresholds must be higher than VUVLO; otherwise it does not work. The devices holds the
HYS pin low until the EN voltage rises above VEN_TH_ON. Then, the HYS pin goes high impedance.
VIN
REN1
EN
EN
Threshold/
Hysteresis
ON/
OFF
REF
REN2
HYS
EN Comparator
REN3
Figure 10. EN Comparator threshold and hysteresis setting
REN1
REN1
ö
ö
æ
æ
VIN _ OFF = VTH _ EN _ OFF ´ ç1 +
÷ = 1.14 V ´ ç1 +
÷
è REN2 + REN3 ø
è REN2 + REN3 ø
REN1 ö
REN1 ö
æ
æ
VIN _ ON = VTH _ EN _ ON ´ ç1 +
÷
÷ = 1.19 V ´ ç1 +
è REN2 ø
è REN2 ø
(3)
8.3.5 Output Capacitor Discharge, TPS61231
To make sure the device starts up under defined conditions, the output capacitor of the TPS61231 gets
discharged by the VOUT pin with a typical discharge resistor of RDIS in the cases when the device gets disabled
by the EN pin, thermal shutdown, and undervoltage lockout.
8.3.6 Power Good Output
The PG output is low when the output voltage is below 90% of its nominal value. The PG pin becomes high
impedance once the output is higher than 95% of its nominal voltage. The PG pin is an open drain output and is
specified to sink up to 500 µA. This PG output requires a pull-up resistor that cannot be connected to any voltage
higher than 5.5 V. PG is held low when the device is disabled by the EN pin and thermal shutdown.
8.3.7 Over Voltage Protection
The device stops switching as soon as the output voltage exceeds VOVP. When the output voltage falls 0.15V
below the OVP threshold, the device resumes normal operation until the output voltage exceeds the OVP
threshold again.
8.3.8 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the junction temperature falls below the threshold, it returns to normal operation automatically.
10
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
8.4 Device Functional Modes
The TPS6123x boost converter family has three operation modes, as shown in Table 1.
Table 1. Operation Mode Description
MODE
DESCRIPTION
CONDITION
PWM
Boost in normal switching operation VIN < VOUT + 0.2 V, heavy load
PFM
Boost in power save operation
VIN < VOUT + 0.2 V, light load
Zero duty cycle operation
VOUT < VIN ≤ VOUT + 0.24 V and VOUT ≥
VOUT_NOM
Zero Duty Cycle
8.4.1 Boost Normal Mode
The TPS6123x boost converter family typically operates at a quasi-constant 2-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit predicts the
required on-time. At the beginning of the switching cycle, the low-side N-MOS switch, shown in the functional
block diagram, is turned on and the inductor current ramps up to a peak current that is defined by the on-time
and the inductance. In the second phase, once this peak current is reached, the current comparator trips, the ontimer is reset turning off the low-side N-MOS switch and turning on the high-side rectifying switch. The current
through the inductor then decays to an internally set valley current. Once this occurs, the on-timer is set to turn
the boost switch back on again and the cycle is repeated.
8.4.2 Boost Power Save Mode
The device integrates a power save mode with pulse frequency modulation (PFM) to improve efficiency at light
load. In power save mode, the device only switches when the output voltage trips below a set threshold voltage.
It ramps up the output with several pulses and enters the power save mode when the output voltage exceeds the
set threshold voltage. PFM is left and PWM mode entered when the inductor current becomes discontinuous.
The DC output voltage in PFM mode rises above the nominal output voltage in PWM mode by 0.7%.
Output Voltage
PFM mode at light load
VOUT_DC = 1.007 x VOUT_NOM
VOUT_NOM
PWM mode at heavy load
t
Figure 11. Output Voltage in PFM/PWM Mode
8.4.3 Zero Duty Cycle Mode
When the input voltage is lower than VOUT + 0.24 V and VOUT is higher than the nominal output voltage, the
device automatically changes to a Zero Duty Cycle Mode. In Zero Duty Cycle Mode, the rectifying switch is
constantly turned on and the low side switch is turned off. The output voltage in this mode depends on the
resistance between the input and the output, calculated as:
VOUT = VIN - IOUT ´ (RDS(on ) + RL )
(4)
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
11
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The devices are designed to operate from an input voltage supply range between 2.3 V and 5.5 V with a
maximum output current of 2.1 A. The devices operate in PWM mode for medium to heavy load conditions and in
power save mode at light load currents. In PWM mode the TPS6123x converter operates with the nominal
switching frequency of 2 MHz which provides a controlled frequency variation over the input voltage range. As
the load current decreases, the converter enters power save mode, reducing the switching frequency and
minimizing the IC quiescent current to achieve high efficiency over the entire load current range. The WEBENCH
software uses an iterative design procedure and accesses a comprehensive database of components when
generating a design. See the Related Documentation section for additional documentation.
9.2 Typical Applications
9.2.1 TPS61230 2.3-V to 5.5-V Input, 5-V Output Converter
L1
1.0µH
VIN
C1
22µF
VIN
SW
EN
VOUT
HYS
C3
10nF
FB
SS
GND
VOUT
R1
402k
C2
3x22µF
R2
100k
PG
TPS61230
R3
1.0Meg
Figure 12. TPS61230 5-V Output Typical Application
9.2.1.1 TPS61230 5-V Output Design Requirements
Use the following typical application design procedure to select external components values for the TPS61230
device.
Table 2. TPS61230 5-V Output Design Parameters
12
DESIGN PARAMETERS
EXAMPLE VALUES
Input Voltage Range
2.3 V to 5.5 V
Output Voltage
5.0 V
Output Voltage Ripple
±3% VOUT
Transient Response
±10% VOUT
Input Voltage Ripple
±200 mV
Output Current Rating
2.1 A
Operating Frequency
2 MHz
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
9.2.1.2 TPS61230 5-V Detailed Design Procedure
Table 3. TPS61230 5-V Output List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
Coilcraft
L1
1.0 μH, power inductor, XFL4020-102MEB
C1
2 μF 6.3 V, 0805, X5R ceramic, GRM21BR60J226ME39
Murata
C2
3 × 22 μF 10 V, 0805, X5R ceramic, LMK212BBJ226MG
YUDEN
C3
10 nF, X7R ceramic
Murata
R1
402 k, resistor, chip, 1/10W, 1%
Rohm
R2
100 k, resistor, chip, 1/10W, 1%
Rohm
9.2.1.2.1 Programming the Output Voltage
The TPS6123x device family's output voltage need to be programmed via an external voltage divider to set the
desired output voltage.
An external resistor divider is used, as shown in Equation 5. By selecting R1 and R2, the output voltage is
programmed to the desired value. When the output voltage is regulated, the typical voltage at the FB pin is VFB.
The following equation can be used to calculate R1 and R2.
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç1 +
÷
÷ = 1V ´ ç1 +
R
2
R
2ø
è
è
ø
(5)
For best accuracy, R2 should be kept smaller than 100 kΩ to ensure that the current following through R2 is at
least 100 times larger than FB pin leakage current. Changing R2 towards a lower value increases the robustness
against noise injection. Changing the R2 towards higher values reduces the quiescent current for achieving
highest efficiency at low load currents.
For the fixed output voltage version, TPS61232, the FB pin must be tied to the output directly.
9.2.1.2.2 Inductor and Capacitor Selection
The second step is the selection of the inductor and capacitor components. To simplify this process, Table 4
outlines possible inductor and output capacitor value combinations.
Table 4. Inductor and Output Capacitor Combinations
L (µH) (1)
COUT (µF) (2)
20
47
100
0.47
10
√
√
√
1.0
√ (3)
√
√
1.5
(1)
(2)
(3)
This is the nominal inductance of inductor. Inductor tolerance and current de-rating is anticipated. The
effective inductance can vary by -30%.
This is the effective capacitance of output capacitors. A higher nominal value is required.
Typical application configuration. Other check mark indicates alternative filter combinations.
9.2.1.2.2.1 Inductor Selection
A boost converter requires two main passive components for storing energy during the conversion, an inductor
and an output capacitor. It is advisable to select an inductor with a saturation current rating higher than the
possible peak current flowing through the power switches. The inductor peak current varies as a function of the
load, the input and output voltages and is estimated using Equation 6.
IOUT
1 V ´D
IL(PEAK ) =
+ ´ IN
(1 - D) ´ h 2 L ´ fSW
(6)
Where
η = Power conversion estimated efficiency
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
13
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the
converter. This could eventually harm the device and reduce reliability. It's recommended to choose the
saturation current for the inductor 20%~30% higher than the IL(PEAK), from Equation 6. The following inductors are
recommended to be used in designs.
Table 5. List of Inductors
INDUCTANCE
[µH]
CURRENT
RATING [A]
DC RESISTANCE
[mΩ]
PART NUMBER
MANUFACTURER
1.0
5.4
10.8
XFL4020-102ME
Coilcraft
1.0
7.5
9
LQH6PPN1R0
muRata
0.47
6.6
7.6
XFL4015-471ME
Coilcraft
9.2.1.2.2.2 Output Capacitor Selection
For the output capacitor, it is recommended to use small X5R or X7R ceramic capacitors placed as close as
possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large
capacitors which cannot be placed close to the IC, using a smaller ceramic capacitor of 1 µF in parallel to the
large one is highly recommended. This small capacitor should be placed as close as possible to the VOUT and
GND pins of the IC.
Care must be taken when evaluating a capacitor’s derating under bias. The bias can significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of their capacitance at rated voltage. Therefore, leave
margin on the voltage rating to ensure adequate effective capacitance.
The ESR impact on the output ripple must be considered as well, if tantalum or electrolytic capacitors are used.
Assuming there is enough capacitance such that the ripple due to the capacitance can be ignored, the ESR
needed to limit the VRipple is:
VRipple(ESR ) = IL(PEAK ) ´ ESR
(7)
9.2.1.2.2.3 Input Capacitor Selection
Multilayer X5R or X7R ceramic capacitors are an excellent choice for input decoupling of the step-up converter
as they have extremely low ESR and are available in small footprints. Input capacitors should be located as
close as possible to the device. While a 22-μF input capacitor is sufficient for most applications, larger values
may be used to reduce input current ripple without limitations. Take care when using only ceramic input
capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires,
such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple
to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance
(electrolytic or tantalum) should in this circumstance be placed between CIN and the power source to reduce
ringing than can occur between the inductance of the power source leads and CIN.
9.2.1.2.3 Loop Stability, Feed Forward Capacitor
The third step is to check the loop stability. The stability evaluation is to look from a steady-state perspective at
the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple, VRipple(OUT)
When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows
oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
The load transient response is another approach to check the loop stability. During the load transient recovery
time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability.
Without any ringing, the loop has usually more than 45° of phase margin.
As for the heavy load transient applications such as a 2 A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in Figure 36. Set the feed forward capacitor zero near 20 kHz for most
applications. See application report Optimizing Transient Response of Internally Compensated dc-dc Converters
With Feedforward Capacitor (SLVA289).
14
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
9.2.1.3 TPS61230 5-V Output Application Performance Plots
4.0
Vout = 5 V
Minimum Resistance at Startup (:)
Maximum Load after Startup (A)
6.0
5.0
4.0
3.0
TA = -40 °C
TA = 25 °C
TA = 85 °C
2.0
1.0
2.3
2.8
3.3
3.8
4.3
4.8
Vout = 5 V
3.0
2.0
1.0
TA = -40 C
TA = 25 C
TA = 85 C
0.0
5.3
2.3
Vin (V)
2.8
90
5.10
Vout (V)
Efficiency (%)
5.20
80
0.010
0.100
5.3
C006
5.00
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vout = 5 V, Vin = 3.6 V
4.80
0.001
1.000
Iout (A)
4.8
4.90
Vin = 3.0 V
Vin = 3.6 V
Vin = 4.2 V
Vout = 5.0 V
4.3
Figure 14. Minimum Resistance at Startup
100
70
3.8
Vin (V)
Figure 13. Maximum Load Current after Startup
60
0.001
3.3
C004
0.010
0.100
1.000
Iout (A)
C008
Figure 15. Efficiency
C0011
Figure 16. Load Regulation
5.20
10,000K
Switching Frequency (Hz)
Vout = 5.0 V
Vout (V)
5.10
5.00
4.90
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vout = 5 V, Iout = 1 A
4.80
2.3
2.8
3.3
3.8
Vin (V)
4.3
4.8
1,000K
100K
10K
1K
0.001
Vin = 2.3 V
Vin = 3.6 V
Vin = 4.2 V
0.010
Figure 17. Line Regulation
0.100
1.000
Iout (A)
C0013
C0015
Figure 18. Switching Frequency
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
15
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
Vout (AC, 50 mV/div)
www.ti.com
t -- 300 ns/div
t -- 10 µs/div
Vout (AC, 50 mV/div)
Icoil (DC, 1 A/div)
Icoil (DC, 1 A/div)
SW (DC, 5 V/div)
SW (DC, 5 V/div)
Figure 19. PWM Operation (VOUT = 5 V, IOUT = 2 A)
Figure 20. PFM Operation (VOUT = 5 V, IOUT = 50 mA)
t -- 10 µs/div
t -- 50 µs/div
Vout (DC, 1 V/div)
Load (DC, 2 A/div)
PG (DC, 5 V/div)
PG (LOW, 0 V)
SW (DC, 5 V/div)
Vout (AC, 0.5 V/div)
Icoil (DC, 5 A/div)
Icoil (DC, 5 A/div)
Figure 21. Load Transient (VOUT = 5 V, IOUT = 0.5 A to 2 A)
t -- 300 µs/div
Figure 22. Output Over Voltage Protection (FB = 0 V, ROUT
= 30 Ω)
t -- 100 µs/div
EN (DC, 5 V/div)
EN (DC, 5 V/div)
PG (DC, 5 V/div)
PG (DC, 5 V/div)
Vout (DC, 2 V/div)
Icoil (DC, 2 A/div)
Vout (DC, 2 V/div)
Icoil (DC, 2 A/div)
Figure 23. Startup (VOUT = 5 V, ROUT = 2.5 Ω)
16
Submit Documentation Feedback
Figure 24. Shutdown (VOUT = 5 V, ROUT = 2.5 Ω)
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
9.2.2 TPS61230 2.3-V to 5.5-V Input, 3.5-V Output Converter
L1
1.0µH
VIN
C1
22µF
VIN
SW
EN
VOUT
HYS
C3
10nF
FB
SS
GND
VOUT
R1
250k
C2
3x22µF
R2
100k
PG
TPS61230
R3
1.0Meg
Figure 25. TPS61230 3.5-V Output Typical Application
9.2.2.1 TPS61230 3.5-V Output Design Requirements
Table 6. TPS61230 3.5-V Output Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUES
Input Voltage Range
2.3 V to 5.5 V
Output Voltage
3.5 V
Output Voltage Ripple
±3% VOUT
Transient Response
±10% VOUT
Input Voltage Ripple
±200 mV
Output Current Rating
2.1 A
Operating Frequency
2 MHz
9.2.2.2 Detailed Design Procedure
Refer to the TPS61230 5-V Detailed Design Procedure section for the 3.5-V detailed design procedures.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
17
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
9.2.2.3 TPS61230 3.5-V Output Application Performance Plots
3.0
Minimum Resistance at Startup ()
Maximum Load after Startup (A)
5.0
Vout = 3.5 V
4.0
3.0
2.0
TA = -40 °C
TA = 25 °C
TA = 85 °C
1.0
2.3
2.8
3.3
3.8
Vout = 3.5 V
2.5
2.0
1.5
TA = -40 °C
TA = 25 °C
TA = 85 °C
1.0
4.3
Vin (V)
2.3
90
3.57
Vout (V)
Efficiency (%)
3.64
80
70
0.100
3.3
3.5
C005
3.50
Vout = 3.5 V, Vin = 3.0 V
3.36
0.001
0.010
1.000
Iout (A)
3.1
3.43
Vin = 2.5 V
Vin = 3.0 V
Vin = 3.3 V
Vout = 3.5 V
2.9
Figure 27. Minimum Resistance at Startup
100
0.010
2.7
Vin (V)
Figure 26. Maximum Load Current after Startup
60
0.001
2.5
C003
TA = -40 °C
TA = 25 °C
TA = 85 °C
0.100
1.000
Iout (A)
C007
Figure 28. Efficiency
C0010
Figure 29. Load Regulation
3.64
10,000K
Switching Frequency (Hz)
Vout = 3.5 V
Vout (V)
3.57
3.50
3.43
TA = -40 °C
TA = 25 °C
TA = 85 °C
Vout = 3.5 V, Iout = 1 A
3.36
2.3
2.5
2.7
2.9
Vin (V)
Submit Documentation Feedback
3.3
100K
10K
1K
0.001
Vin = 2.3 V
Vin = 2.7 V
Vin = 3.0 V
0.010
0.100
1.000
Iout (A)
C0012
Figure 30. Line Regulation
18
3.1
1,000K
C0014
Figure 31. Switching Frequency
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
t -- 2 ms/div
t -- 200 µs/div
PG (DC, 2 V/div)
EN (DC, 5 V/div)
Vin (DC, 1 V/div)
PG (DC, 5 V/div)
Vout (DC, 1 V/div)
Icoil (DC, 1.5 A/div)
Vout (DC, 2 V/div)
Icoil (DC, 1 A/div)
Figure 32. Input Sweep (VOUT = 3.5 V, VIN = 2.7 V to 4.2 V,
IOUT = 1.5 A)
Figure 33. Startup (VOUT = 3.5 V, VIN = 3.0 V, ROUT = 2.3 Ω)
t -- 75 µs/div
EN (DC, 5 V/div)
PG (DC, 5 V/div)
Vout (DC, 2 V/div)
Icoil (DC, 1 A/div)
Figure 34. Shutdown (VOUT = 3.5 V, VIN = 3.0 V, ROUT = 2.3 Ω)
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
19
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
9.2.3
www.ti.com
TPS61230 Application with Feed Forward Capacitor for Best Transient Response
As for the heavy load transient applications such as a 2-A load step transient, a feed forward capacitor in parallel
with R1 is recommended. The feed forward capacitor increases the loop bandwidth by adding a zero. This results
in a lower output voltage drop, as shown in Figure 36. Set the feed forward capacitor zero near 20 kHz for most
applications. See application report Optimizing Transient Response of Internally Compensated dc-dc Converters
With Feedforward Capacitor (SLVA289).
L1
1.0µH
VIN
C1
22µF
VIN
SW
EN
VOUT
HYS
C3
10nF
FB
SS
GND
VOUT
R1
402k
C4
18pF
C2
3x22µF
R2
100k
PG
TPS61230
R3
1.0Meg
Figure 35. TPS61230 5-V Output with Cff Typical Application
9.2.3.1 Design Requirements
Refer to the TPS61230 5-V Output Design Requirements section for the design requirements.
9.2.3.2 Detailed Design Procedure
Refer to the TPS61230 5-V Detailed Design Procedure section for the detailed design procedures.
9.2.3.3 Application Curve
t -- 50 µs/div
Load (DC, 2 A/div)
PG (DC, 5 V/div)
Vout (AC, 0.5 V/div)
Icoil (DC, 5 A/div)
Figure 36. Load Transient (VOUT = 5 V, IOUT = 0.5 A to 2 A, CFF = 18 pF)
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.3 V and 5.5 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor
with a value of 47 μF is a typical choice.
20
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
11 Layout
11.1 Layout Guidelines
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at the GND pin of the IC. The most critical current path for all boost
converters is from the switching FET, through the synchronous FET, then the output capacitors, and back to
ground of the switching FET. Therefore, the output capacitors and their traces should be placed on the same
board layer as the IC and as close as possible between the IC’s VOUT and GND pin.
See Figure 37 for the recommended layout.
11.2 Layout Example
Top Layer
GND
R2
Bottom Layer
R1
C3
GND
C1
VIN
1
L1
C2
VOUT
R3
Figure 37. Layout Recommendation
11.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Two basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Introducing airflow in the system
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
21
TPS61230, TPS61231, TPS61232
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
www.ti.com
Thermal Considerations (continued)
For more details on how to use the thermal parameters in the dissipation ratings table please check the
application report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
and the application report Semiconductor and IC Package Thermal Metrics (SPRA953).
22
Submit Documentation Feedback
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
TPS61230, TPS61231, TPS61232
www.ti.com
SLVSAQ2C – JANUARY 2014 – REVISED OCTOBER 2014
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor
SLVA289
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
Semiconductor and IC Package Thermal Metrics (SPRA953)
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS61230
Click here
Click here
Click here
Click here
Click here
TPS61231
Click here
Click here
Click here
Click here
Click here
TPS61232
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2014, Texas Instruments Incorporated
Product Folder Links: TPS61230 TPS61231 TPS61232
Submit Documentation Feedback
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS61230DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBK
TPS61230DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBK
TPS61232DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBL
TPS61232DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
SBL
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
