TPS61378-Q1
SLVSET0D – MAY 2020 – REVISED OCTOBER 2021
TPS61378-Q1 25-µA Quiescent Current Synchronous Boost Converter with Load
Disconnect
1 Features
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
– Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Function Safety-Capable
– Documentation available to aid functional safety
system design
Flexible input and output operation range
– Input voltage range: 2.3 V to 14 V
– Programmable output voltage range: 4.0 V to
18.5 V
– Fixed output options: 5 V, 5.25 V, and 5.5 V
– Programmable peak current limit: 1 A to 4.8 A
Avoid AM band interference and crosstalk
– Dynamically programmable switching
frequency: 200 kHz to 2.2 MHz
– Spread spectrum frequency modulation
– Optional clock synchronization
Minimize solution size for space constraint
applications
– Integrated LS/HS/ISO FET:
RDS(ON) 50 mΩ/50 mΩ/100 mΩ
– Support up to 2.2 MHz with small L-C
Minimized light load and idle state current
consumption
– 25-µA quiescent current into VIN pin
– 0.5-µA shutdown current into VIN pin
– Selectable auto PFM and forced PWM mode
– True load disconnect during shutdown or fault
conditions
Integrated protection features
– Supports VIN close to VOUT operation
– Input undervoltage lockout and output
overvoltage protection
– Hiccup output short circuit protection
– Power good indicator
– Thermal shutdown protection at 165°C
Higher than 90% efficiency under 0.8-A load from
3.3-V to 9-V conversion
2 Applications
•
•
•
•
Advanced driver-assistance system (ADAS)
Automotive infotainment and cluster
Body electronics and lighting
Emergency call (eCall)
function. The input voltage covers 2.3 V to 14 V while
the maximal output voltage covers up to 18.5 V. The
switching current limit is programmable from 1 A to
4.8 A. The device consumes 25-μA quiescent current
from VIN.
The TPS61378-Q1 employs peak current mode
control with the switching frequency programmable
from 200 kHz to 2.2 MHz. The device works in
fixed frequency PWM operation in medium to heavy
loads. There are two optional modes in light load
by configuring the MODE pin: auto PFM mode and
forced PWM to balance the efficiency and noise
immunity in light load. The switching frequency can be
synchronized to an external clock. The TPS61378-Q1
uses the spread spectrum of the internal clock to be
more EMI friendly at FPWM mode. In addition, there
is an internal soft-start time to limit the inrush current.
The TPS61378-Q1 has various fixed output voltage
versions to save the external feedback resistor. It
supports the external loop compensation so that the
stability and transient response can be optimized
at wider VOUT/VIN ranges. It also integrates robust
protection features including output short protection,
output overvoltage protection, and thermal shutdown
protection. The TPS61378-Q1 is available in a 3-mm
× 3-mm 16-pin QFN package with wettable flank.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TPS61378-Q1
VQFN-16
3.0-mm × 3.0-mm
(1)
VIN
For all available packages, see the orderable addendum at
the end of the data sheet.
L1
SW
PG
BST
VCC
R1
C2
VIN
C1
EN
C6
OUT
C3
TPS61378-Q1
VOUT
FREQ
VO
COMP
FB
R3
R6
C4
R2
C5
MODE/SYNC
GND
ILIM
R4
R5
Typical Application
3 Description
The TPS61378-Q1 is a fully-integrated synchronous
boost converter with an integrated load disconnect
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61378-Q1
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SLVSET0D – MAY 2020 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics ............................................6
7.6 Typical Characteristics................................................ 8
8 Detailed Description...................................................... 11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 16
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Device Support....................................................... 27
12.2 Receiving Notification of Documentation Updates..27
12.3 Support Resources................................................. 27
12.4 Trademarks............................................................. 27
12.5 Glossary..................................................................27
12.6 Electrostatic Discharge Caution..............................27
13 Mechanical, Packaging, and Orderable
Information.................................................................... 27
4 Revision History
Changes from Revision C (June 2021) to Revision D (October 2021)
Page
• Replaced the operating ambient temperature with the operating junction temperature and added table note in
Section 7.3 .........................................................................................................................................................5
• Updated Section 8.3.13 ................................................................................................................................... 14
• Updated Figure 9-2 ..........................................................................................................................................20
Changes from Revision B (February 2021) to Revision C (June 2021)
Page
• Updated resistor from FB to GND values........................................................................................................... 3
• Updated voltage reference specifications...........................................................................................................6
• Updated Section 9.2.2.1 .................................................................................................................................. 16
Changes from Revision A (October 2020) to Revision B (February 2021)
Page
• Added TPS613783-Q1 and TPS613785-Q1 variants to data sheet................................................................... 6
Changes from Revision * (May 2020) to Revision A (October 2020)
Page
• Changed TPS61378-Q1 device status from Advance Information to Production Data...................................... 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
2
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5 Device Comparison Table
PART NUMBER
TPS61378-Q1
TPS613781-Q1(1)
TPS613782-Q1(1)
TPS613783-Q1
TPS613784-Q1(1)
TPS613785-Q1
(1)
OUTPUT VOLTAGE (V)
RESISTOR FROM FB TO GND (RFB_LOW)
5
0Ω≤ RFB_LOW ≤ 2.4 kΩ
5.25
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
5.5
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
Adjustable
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
5.7
0Ω≤ RFB_LOW ≤ 2.4 kΩ
6.2
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
7
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
8
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
9
0Ω≤ RFB_LOW ≤ 2.4 kΩ
10
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
11
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
12
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
5
0Ω≤ RFB_LOW ≤ 2.4 kΩ
5.25
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
5.5
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
Adjustable
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
5.7
0Ω≤ RFB_LOW ≤ 2.4 kΩ
6.2
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
7
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
8
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
9
0Ω≤ RFB_LOW ≤ 2.4 kΩ
10
3.6kΩ ≤ RFB_LOW ≤ 4.8kΩ
11
7.2kΩ ≤ RFB_LOW ≤ 9.6kΩ
12
14.4kΩ ≤ RFB_LOW ≤ 100kΩ
SPREAD SPECTRUM
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1
VIN
2
BST
16
15
14
13
FREQ
EN
COMP
FB
6 Pin Configuration and Functions
ILIM
12
PG
11
Exposed
Thermal Pad
4
SW
VO
9
5
6
7
GND
10
GND
OUT
VCC
SW
MODE
/SYNC
3
8
Figure 6-1. 16-Pin WQFN RTE Package (Transparent Top View)
Table 6-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
VIN
1
I
IC power supply input
BST
2
I
Power supply for high-side N-MOSFET gate drivers. A capacitor must be connected
between this pin and the SW pin.
SW
3, 4
PWR
The switching node pin of the converter. It is connected to the drain of the internal low-side
FET and the source of the high-side FET.
MODE/SYNC
5
I
Mode selection pin.
MODE = high, forced PWM mode
MODE = low or floating, auto PFM mode
This pin can also be used to synchronize the external clock. Refer to Table 8-1 for details.
VCC
6
O
Output of internal regulator. A ceramic capacitor with more than 1 μF must be connected
between this pin and GND.
GND
7, 8
PWR
Power ground of the IC. It is connected to the source of the low-side FET.
VO
9
PWR
Output of the isolation FET. Connect load to this pin to achieve input/output isolation.
OUT
10
PWR
Output of the drain of the HS FET. Connect this pin because the output can disable the load
disconnect/short protection feature (or short this pin with the VO pin).
PG
11
O
Power good indicator and open drain output
ILIM
12
I
Current limit setting pin. Use a resistor to set the desired peak current limit. Refer to Section
8.3.7 for details.
FB
13
I
Feedback pin. Use a resistor divider to set the desired output voltage. Refer to Section
9.2.2.1 for details.
COMP
14
I
Output of the internal transconductance error amplifier. An external RC network is connected
to this pin to optimize the loop stability and response time.
EN
15
I
Enable logic input
FREQ
16
I
Frequency setting pin. Connect a resistor between this pin and GND pin to set the desired
frequency.
-
-
The thermal pad must be connected to the power ground plane for good power dissipation.
Thermal Pad
4
NO.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
VIN
-0.3
16
V
VO, SW, OUT
–0.3
23
V
BST
–0.3
SW + 6
V
MODE/SYNC, FB, FREQ, ILIM, VCC, COMP, EN
–0.3
6
V
PG
-0.3
20
V
TJ (3)
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
Voltage range at terminals (2)
Voltage range at terminals (2)
(1)
(2)
(3)
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values are with respect to network ground terminal.
High junction temperatures degrade operating lifetime. Operating lifetime is de-rated for junction temperatures greater than 125°C
7.2 ESD Ratings
VALUE
V(ESD) (1)
Electrostatic discharge
V(ESD) (1)
Electrostatic discharge
(1)
(2)
(3)
Human-body model (HBM), per AEC Q100-002(2)
±2000
Charged-device model (CDM), per AEC Q100-011, all pins(3)
±500
Charged-device model (CDM), per AEC Q100-011, corner pins
(1,4,5,8,9,12,13,16)(3)
±750
UNIT
V
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary
precautions.
Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows
safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary
precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
Input voltage
VOUT
Outputvoltage
TJ
Operating junction temperature(1)
(1)
NOM
MAX
UNIT
2.3
14
4
18.5
V
V
–40
150
°C
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
7.4 Thermal Information
TPS61378-Q1
THERMAL METRIC(1)
RTE
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
46.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
43.5
°C/W
RθJB
Junction-to-board thermal resistance
18.5
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
18.5
°C/W
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TPS61378-Q1
THERMAL METRIC(1)
RTE
UNIT
16 PINS
RθJC(bot)
(1)
Junction-to-case (bottom) thermal resistance
8.8
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
TJ = -40 to 125°C, L = 1 µH, VIN = 3.3 V and VOUT = 9 V (VO pin). Typical values are at TJ = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14
V
VIN rising
2.2
2.3
V
VIN falling
2.04
2.2
POWER SUPPLY
VIN
Input voltage range
2.3
VIN_UVLO
VIN under voltage lockout threshold
VIN_HYS
VIN UVLO hysteresis
VCC_UVLO
VCC UVLO threshold
VCC rising
2.2
V
VCC_HYS
VCC UVLO hysteresis
VCC hysteresis
150
mV
VCC
VCC regulation
IVCC = 6 mA, VOUT = 9V
4.8
V
IQ
Quiescent current into VIN pin
IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF +
0.1 V,
25
35
µA
IQ
Quiescent current into OUT pin
IC enabled, no load,
VIN = 3.3 V, VOUT = 18.5 V, VFB = VREF +
0.1 V,
10
20
µA
ISD
Shutdown current into VIN pin
IC disabled, VIN =14 V, EN = GND
0.6
5
µA
ISW_LKG
Leakage current into SW
IC disabled, VIN = OUT = SW =14 V
5
µA
IVO_LKG
Reverse leakage current into VO
IC disabled, OUT= VO = 5 V, SW = 0
5
µA
20.5
V
160
V
mV
OUTPUT VOLTAGE
VOVP
Output over-voltage protection threshold
VIN = 3.3 V, VOUT rising
VOVP_HYS
Output over-voltage protection hysteresis
VIN = 3.3 V, OVP threshold
19.3
20
0.5
V
VOLTAGE REFERENCE
VREF
Reference Voltage at FB pin
TJ = -40 to 125°C, RFB = 16.0kΩ
0.788
0.800
0.812
V
TJ = -40 to 125°C, RFB = 2.0 kΩ
4.85
5.00
5.15
V
VOUT_5.25V
TJ = -40 to 125°C, RFB = 4.0 kΩ
5.10
5.25
5.35
V
VOUT_5.5V
TJ = -40 to 125°C, RFB = 8.0 kΩ
5.35
5.50
5.65
V
VOUT_5V
TPS613783Q1, TJ = -40 to 125°C, RFB =
2.0 kΩ
4.85
5.00
5.15
V
VOUT_5.25V
TPS613783Q1, TJ = -40 to 125°C, RFB =
4.0 kΩ
5.10
5.25
5.35
V
VOUT_5.5V
TPS613783Q1, TJ = -40 to 125°C, RFB =
8.0 kΩ
5.35
5.50
5.65
V
VOUT_9V
TPS613785Q1, TJ = -40 to 125°C, RFB =
2.0 kΩ
8.75
9.00
9.15
V
VOUT_10V
TPS613785Q1, TJ = -40 to 125°C, RFB =
4.0 kΩ
9.75
10.00
10.20
V
VOUT_11V
TPS613785Q1, TJ = -40 to 125°C, RFB =
8.0 kΩ
10.70
11.00
11.20
V
VOUT_12V
TPS613785Q1, TJ = -40 to 125°C, RFB =
16.0 kΩ
11.70
12.00
12.22
V
50
nA
VOUT_5V
IFB_LKG
Leakage current into FB pin
POWER SWITCH
RDS(on)
Low-side MOSFET on resistance
VCC = 4.85 V
50
mΩ
RDS(on)
High-side MOSFET on resistance
RDS(on)
Isolation MOSFET on resistance
VCC = 4.85 V
50
mΩ
VCC = 4.85 V
100
mΩ
CURRENT LIMIT
6
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TJ = -40 to 125°C, L = 1 µH, VIN = 3.3 V and VOUT = 9 V (VO pin). Typical values are at TJ = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ILIM_SW
Peak switching current limit FPWM
RLIM = 20 kΩ , Duty cycle = 65%
4
4.8
5.55
A
ILIM_SW
Peak switching current limit Auto PFM
RLIM = 20 kΩ , Duty cycle = 65%
4
4.8
5.55
A
ILIM_SW
Peak switching current limit FPWM
RLIM = 102 kΩ, Duty cycle = 65%, 4.7uH
0.75
ILIM_SW
Peak switching current limit Auto PFM
RLIM = 102 kΩ, Duty cycle = 65%, 4.7uH
0.75
ILIM_SS_1
Peak switching current limit at softstart
VIN = 3.3 V, VOUT = 0 V, RLIM = 20 kΩ
A
A
0.9
1.15
1.4
A
SWITCHING FREQUENCY
Fsw
Switching frequency
RFREQ = 18 kΩ
2050
2200
2400
kHz
Fsw
Switching frequency
RFREQ = 218 kΩ
180
200
230
kHz
Dmax
Maximum Duty Cycle
RFREQ = 18 kΩ
78
tON_min
Minimal on time
%
70
ns
FDITHER
10%
Fsw
Fpattern
0.4%
Fsw
ERROR AMPLIFIER
ISINK
COMP pin sink current
VFB = VREF + 0.2V
6
uA
ISOURCE
COMP pin source current
VFB = VREF - 0.2V
6
uA
VCCLPH
COMP pin high clamp voltage
VFB = VREF - 0.2V, ILIM = 4.8 A
1.3
V
VCCLPL
COMP pin high low voltage
VFB = VREF + 0.2V,
0.6
V
GmEA
Error amplifier trans conductance
VCOMP = 1.0 V
70
uS
POWER GOOD
VPG_TH
PG threhold for rising FB voltage
Reference to VREF
90%
VPG_HYS
PG hysteresis
Reference to VREF
5%
IPG_SINK
PG pin sink current capability
VPG = 0.4 V
tPG_DELAY
PG delay time
20
2.5
3.4
mA
4.3
ms
DOWN MODE
tEN_DELAY
Delay time between EN high and device
working
0.4
ms
tSS
Softstart time
2.5
ms
tHCP_ON
Hiccup on time
1.8
ms
tHCP_OFF
Hiccup off time
67
ms
fSYNC_MIN
200
kHz
fSYNC_MAX
2200
kHz
SYNC TIMING
EN/SYNC LOGIC
VIH
EN, MODE/SYNC pins Logic high
threshold
VIL
EN, MODE/SYNC pins Logic Low
threshold
RDOWN
EN, MODE/SYNC pins internal pull down
resistor
1.2
0.4
V
V
800
kΩ
THERMAL SHUTDOWN
tSD_R
Thermal shutdown rising threshold
TJ rising
165
°C
tSD_F
Thermal shutdown falling threshold
TJ falling
145
°C
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7.6 Typical Characteristics
VIN = 3.3 V, VOUT = 9 V (VO pin), TA = 25°C, Fsw = 2.2 MHz, unless otherwise noted.
100
100
Vin = 2.7 V
Vin = 3.3 V
Vin = 3.8 V
80
80
70
70
60
50
40
50
40
30
20
20
10
10
0.0001
0.001
0.01
0.1
1
Output Current (A)
VOUT = 5 V
0
0.0001
2
Auto PFM
Fsw = 2.2 MHz
0.1
VOUT = 5 V
1
2
D015
FPWM
Fsw = 2.2 MHz
Figure 7-2. 5 VOUT Efficiency vs Output Current
100
Vin = 2.7 V
Vin = 3.3 V
Vin = 5 V
90
70
70
Efficiency (%)
80
60
50
40
60
50
40
30
30
20
20
10
10
0
1E-5
0.0001
Vin = 2.7 V
Vin = 3.3 V
Vin = 5 V
90
80
0.001
0.01
0.1
VOUT = 9 V
0
0.0001
1
Output Current (A)
0.001
0.01
Auto PFM
0.1
1
Output Current (A)
D007
Fsw = 2.2 MHz
Figure 7-3. 9 VOUT Efficiency vs Output Current
VOUT = 9 V
D006
FPWM
Fsw = 2.2 MHz
Figure 7-4. 9 VOUT Efficiency vs Output Current
30
9.05
Vin = 2.7 V
Vin = 3.3 V
Vin = 5 V
TJ = -40 °C
TJ = 25 °C
TJ = 125 °C
Quiescent Current into Vin (PA)
9.04
Output Voltage (V)
0.01
Output Current (A)
100
9.03
9.02
9.01
9
0.0001
0.001
0.01
0.1
Output Current (A)
VOUT = 9 V
PFM
28
26
24
22
1
D009
Fsw = 2.2 MHz
Figure 7-5. 9 VOUT Regulation vs Output Current
8
0.001
D016
Figure 7-1. 5 VOUT Efficiency vs Output Current
Efficiency (%)
60
30
0
1E-5
Vin = 2.7 V
Vin = 3.3 V
Vin = 3.8 V
90
Efficiency (%)
Efficiency (%)
90
20
2.3
2.6
2.9
3.2
3.5
3.8
Input Voltage (V)
4.1
4.4
4.7
5
D001
Figure 7-6. Quiescent Current into VIN vs Input
Voltage
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5.7
0.5
TJ = -40 °C
TJ = 25 °C
TJ = 125 °C
5V Output (V)
5.238V Output (V)
5.5V Output (V)
5.6
Fixed Output Voltage (V)
Shutdown Current (PA)
0.4
0.3
0.2
5.5
5.4
5.3
5.2
5.1
0.1
5
0
2.3
2.6
2.9
3.2
3.5
3.8
4.1
4.4
4.7
Input Voltage (V)
4.9
-40
5
-20
0
20
Figure 7-7. Shutdown Current vs Input Voltage
40
60
80
100
120
140
Temperature (°C)
D002
D014
Figure 7-8. Fixed Output Voltage vs Temperature
0.805
5
0.804
4.5
FPWM
4
0.802
Current Limit (A)
Reference Voltage (V)
0.803
0.801
0.8
0.799
3.5
3
2.5
2
0.798
1.5
0.797
1
0.796
0.795
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
0.5
10
140
20
30
40
50
Figure 7-9. Reference Voltage vs Temperature
60
70
80
90
100
110
Resistor (k:)
D003
D004
Figure 7-10. Current Limit vs Setting Resistance
2.3
2.4
Rising
Falling
1.8
2.2
VIN UVLO (V)
Switching Frequency (MHz)
2.1
1.5
1.2
0.9
2.1
0.6
0.3
0
0
25
50
75
100
125
Resistor (k:)
150
175
200
225
2
-40
-20
Figure 7-11. Switching Frequency vs Setting
Resistance
0
20
40
60
80
100
120
140
Temperature (°C)
D005
D010
Figure 7-12. VIN UVLO Threshold Voltage vs
Temperature
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1.2
3.5
Rising
Falling
3.475
1
PG Delay Time (ms)
EN Threshold Voltage (V)
1.1
0.9
0.8
0.7
3.45
3.425
0.6
0.5
0.4
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
3.4
-40
140
40
60
80
100
120
140
D012
5.2
5Vin Current Limit (A)
3.3Vin Current Limit (A)
2.7Vin Current Limit (A)
Low Side FET (m:)
High Side FET (m:)
Isolation FET (m:)
5.1
120
110
Current Limit (A)
ON Resistance (m:)
20
Figure 7-14. PG Delay Time vs Temperature
150
130
0
Temperature (°C)
Figure 7-13. EN Threshold Voltage vs Temperature
140
-20
D011
100
90
80
70
5
4.9
60
50
4.8
40
30
20
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
4.7
30
40
50
60
Duty Cycle (%)
D013
Figure 7-15. RDSON vs Temperature
10
140
70
D008
Figure 7-16. Duty Cycle vs Current Limit
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8 Detailed Description
8.1 Overview
The TPS61378-Q1 is a fully-integrated synchronous boost converter with load disconnect function. It supports
output voltage up to 18.5 V with a maximum of a 4.8-A programmable switching peak current limit. The input
voltage ranges from 2.3 V to 14 V while consuming 25-µA quiescent current.
The TPS61378-Q1 utilizes the fixed-frequency peak current control scheme, which has an internal oscillator and
supports adjustable switching frequency from 200 kHz to 2.2 MHz.
The TPS61378-Q1 operates with fixed-frequency pulse width modulation (PWM) from medium to heavy load. At
the beginning of each switching cycle, the low-side N-MOSFET switch is turned on. The inductor current ramps
up to a peak current that is determined by the output of the internal error amplifier (EA). Once the switching
peak current triggers the output of the EA, the low-side N-MOSFET is turned off and the high-side N-MOSFET
is turned on after a short dead time. The high-side N-MOSFET switch is not turned off until the next cycle
as determined by the internal oscillator. The low-side switch turns on again after a short dead time and the
switching cycle is repeated.
The TPS61378-Q1 provides either auto PFM or forced PWM for the light load operation by configuring the
MODE/SYNC pin. In forced PWM mode, the switching frequency remains constant across the entire load range,
which helps avoid frequency variation with load. The internal oscillator can be synchronized to an external clock
applied on the MODE/SYNC pin. Spread spectrum modulation of the frequency in forced PWM mode helps
optimize the EMI performance for automotive applications. In auto PFM mode, the switching frequency can
decrease, resulting in higher efficiency.
The TPS61378-Q1 implements a cycle-by-cycle current limit to protect the device from overload during the boost
operation phase. If the output current further increases and triggers the output voltage to fall below the input
voltage, the TPS61378-Q1 enters into hiccup mode short protection.
There is a built-in soft-start time, which prevents the inrush current during the start-up. The TPS61378-Q1 also
provides a power good (PG) indicator to enable the power sequence control for start-up.
The TPS61378-Q1 also has a number of protection features including output short protection, output overvoltage
protection (OVP), and thermal shutdown protection (OTP).
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8.2 Functional Block Diagram
L1
VIN
C1
C3
C2
OUT
SW
BST
VIN
OUT
VCC
VO
1/K
Logic
LDO
& BIAS
EN
ULVO
COMP
VUVLO
C4
HS
Fixed
Output
SW
OVP
VOUT
BST
ISO
SCP
VCC
LS
OTP
Soft
Start
Q
VCC
S
C6
R
MODE
COMP
CLIM
Slope Compensation
R6
CLK
R1
COMP
Gm
Vref
PG
FB
VO Voltage
SELECT
FREQ
Frequency
SELECT
MODE
PGOOD
OSC
SYNC
MODE
CLIM
VOVP
R4
COMP
OVP
COMP
OTP
VOUT 1/N
Dithering
Current Limit SELECT
VOTP
Temp
R3
ILIM
MODE/
SYNC
R5
COMP
GND
R2
C5
8.3 Feature Description
8.3.1 VCC Power Supply
The internal LDO in the TPS61378-Q1 outputs a regulated voltage of 4.8 V with 10-mA output current capability.
A ceramic capacitor is connected between the VCC pin and GND pin to stabilize the VCC voltage and also
decouple the noise on the VCC pin. The value of this ceramic capacitor should be above 1 µF. A ceramic
capacitor with an X7R or X5R grade dielectric with a voltage rating higher than 10 V is recommended.
8.3.2 Input Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit stops the operation of the converter when the input voltage drops below
the UVLO threshold of 2.04 V (typical). A hysteresis of 160 mV (typical) is added so that the device cannot be
enabled again until the input voltage exceeds 2.2 V (typical). This function is implemented to prevent the device
from malfunctioning when the input voltage is between 2.04 V and 2.2 V.
8.3.3 Enable and Soft Start
When the input voltage is above the UVLO threshold and the EN pin is pulled above 1.2 V, the TPS61378-Q1
is enabled. The device starts to monitor the FB pin. With a typical 400-µs delay time after EN is pulled high,
the TPS61378-Q1 starts switching. There is an internal built-in start-up time, typically 2.5 ms, to limit the inrush
current during start-up.
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8.3.4 Shut Down
When the input voltage is below the UVLO threshold or the EN pin is pulled low, the TPS61378-Q1 is in
shutdown mode and all the functions are disabled. The input voltage is isolated from the output to minimize the
leakage currents.
8.3.5 Switching Frequency Setting
The TPS61378-Q1 uses a fixed-frequency control scheme. The switching frequency can be programmed
between 200 kHz and 2.2 MHz using a resistor from the FREQ pin to GND. The resistor must be connected
when the oscillator is synchronized by an external clock. The resistance is defined by Equation 1.
(59 (/*V) =
41.9
4(4'3 :GÀ; + 1.05
(1)
where
• RFREQ is the resistance between the FREQ pin and the GND pin
For example, the switching frequency is 2.2 MHz if the resistance between the FREQ pin and GND is 18 kΩ.
This pin cannot be left floating or tied to VCC.
8.3.6 Spread Spectrum Frequency Modulation
The TPS61378-Q1 uses a triangle waveform to spread the switching frequency with ±10% of normal frequency.
The frequency of the triangle waveform is typically 0.4% of the switching frequency. For example, if the normal
switching frequency of the TPS61378-Q1 is programmed to 2.2 MHz, the spread spectrum function modulates
the switching frequency in the range of 1.98 MHz to 2.42 MHz in a triangle behavior with an 8.8-kHz rate.
The spread spectrum is only available while the clock of the TPS61378-Q1 is free running at its natural
frequency. Any of the following conditions overrides spread spectrum, turning it off:
• An external clock is applied to the MODE/SYNC pin.
• The device works in PFM operation at light load.
8.3.7 Adjustable Peak Current Limit
The TPS61378-Q1 adopts a cycle-by-cycle peak current limit internally. The low-side switch is turned off
immediately as soon as the switch peak current triggers the limit threshold. The peak switch current limit can be
set by a resistor from the ILIM pin to ground. The relationship between the current limit and the resistor is shown
in Equation 2.
R LIM k:
1.184
90.56
I LIM A
(2)
where
• RILIM is the resistance between the ILIM pin and the GND pin
• ILIM is switch peak current limit
For instance, the current limit is set to 4.8 A if the RLIM is 20 kΩ. This pin cannot be left floating or connected to
VCC.
8.3.8 Bootstrap
The TPS61378-Q1 has an integrated bootstrap regulator circuit. A small ceramic capacitor is needed between
the BST pin and SW pin to provide the gate drive supply voltage for high-side switches. The bootstrap capacitor
is charged during the time when the low-side switch is in the ON state. The value of this ceramic capacitor
should be above 0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating higher
than 6.3 V is recommended.
8.3.9 Load Disconnect
The TPS61378-Q1 integrates a load disconnect function when the input source is DC, completely cutting off the
path between the input side and output side during shutdown.
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The output disconnect function also allows the output short protection and minimizes the inrush current at
start-up.
8.3.10 MODE/SYNC Configuration
Table 8-1 summarizes the MODE/SYNC function and the entry condition.
Table 8-1. MODE/SYNC Configuration
MODE/SYNC PIN CONFIGURATION
MODE
Logic Low or Floating
Auto PFM Mode
Logic High
Forced PWM Mode
External Synchronization
Forced PWM Mode
The TPS61378-Q1 can be synchronized to an external clock applied to the MODE/SYNC pin.
8.3.11 Overvoltage Protection (OVP)
If the output voltage exceeds the OVP threshold (typically 20 V), the TPS61378-Q1 immediately stops switching
until the output voltage drops below the recovery threshold (typically 19.5 V). This function protects the device
against excessive voltage.
8.3.12 Output Short Protection/Hiccup
In addition to the cycle-by-cycle current limit function, the TPS61378-Q1 also has output short protection. If
the output current causes the low-side FET to reach current limit and pull the output voltage below the input
voltage, the device enters into short circuit protection mode, triggering the hiccup timer. When the hiccup timer is
triggered, the device limits the current to a relative lower level for 1.8 ms and then shuts down. After 67 ms, it will
restart. If the short condition disappears, the device will automatically restart.
When FB voltage is below ≤ 0.1 V during fault condition, the current limit threshold is reduced to 1/5 of the
programmed current limit. Frequency is clamped to 1.1 MHz if the FREQ pin setting is greater than 1.1 MHz.
8.3.13 Power-Good Indicator
The TPS61378-Q1 integrates a power-good function. The power-good output consists of an open-drain NMOS,
requiring an external pullup resistor connect to a suitable voltage supply like VCC. The PG pin goes high with a
typical 3.4-ms delay time after VOUT reaches 90% of the target output voltage. When the output voltage drops
below 85% of the target output voltage, the PG pin immediately goes low without delay.
8.3.14 Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to excessive heat and power dissipation. Typically,
the thermal shutdown occurs at junction temperatures exceeding 165°C. When the thermal shutdown is
triggered, the device stops switching and recovers when the junction temperature falls below 145°C (typical).
8.4 Device Functional Modes
8.4.1 Forced PWM Mode
The TPS61378-Q1 enters forced PWM mode by pulling the MODE/SYNC pin to logic high for more than five
switching cycles. In forced PWM mode, the TPS61378-Q1 keeps the switching frequency constant at light load
condition. When the load current decreases, the output of the internal error amplifier also decreases to keep the
inductor peak current down. When the output current decreases further, the high-side switch is not turned off
even if the current of the high-side switch goes negative to keep the frequency constant.
8.4.2 Auto PFM Mode
The TPS61378-Q1 enters auto PFM Mode by pulling the MODE/SYNC pin to logic low for more than five
switching cycles or leaving the pin floating. The TPS61378-Q1 improves the efficiency at light load when
operating in PFM mode. When the output current decreases to a certain level, the output voltage of the error
amplifier is clamped by the internal circuit. If the output current reduces further, the inductor current through the
high-side switch will be clamped but not lowered further. Pulses are skipped to improve the efficiency at light
load.
14
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8.4.3 External Clock Synchronization
The TPS61378-Q1 supports external clock synchronization with a range of 200 kHz to 2.2 MHz. The TPS61378Q1 remains in forced PWM mode and operates in CCM across the entire load range if the oscillator is
synchronized by an external clock. The spread spectrum feature is disabled when external synchronization
is used.
8.4.4 Down Mode
The TPS61378-Q1 features down mode operation when input voltage is close to or higher than output voltage.
In down mode, output voltage is regulated at target value, even when VIN > VO. The TPS61378-Q1 high-side
and low-side FETs are switching devices that always work in boost operation, where the isolation FET always
works as a linear device.
For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378Q1 enters down mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz. Exiting down mode requires
VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.
In normal operation, the isolation FET is fully on.
When down mode is triggered and VIN is less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above
VO pin voltage. An isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage
drop.
When down mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin has an
approximated 3 V (typical) above the VIN pin voltage. As VIN keeps rising, the OUT pin continues rising with
3 V on top of VIN. In addition, an isolation FET works in LDO mode to regulate VO pin voltage with a voltage
differential of the OUT pin and VO pin.
Refer to Figure 8-1.
Vin > Vo
Down Mode
Entering
Voltage Threshold
Vin < Vo
Down Mode
Exiting
Threshold
OUT
VO
VIN
T
Figure 8-1. Down Mode
Take care during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the device
operates in down mode and the isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS61378-Q1 is a 25-µA quiescent current boost converter that supports a 2.3-V to 14-V input voltage
range. The device also supports load disconnect to minimize the leakage current. The following design
procedure can be used to select component values for the TPS61378-Q1.
9.2 Typical Application
VIN
L1
SW
PG
BST
VCC
R1
C2
VIN
C1
EN
C6
OUT
C3
TPS61378-Q1
VOUT
FREQ
VO
COMP
FB
R3
R6
C4
R2
C5
MODE/SYNC
GND
ILIM
R4
R5
Figure 9-1. Typical Application
9.2.1 Design Requirements
A typical application example is dual cameras powered through a coax cable, which normally requires 9.0-V
output as its bias voltage and consumes less than 600 mA current. 800-mA load current is designed to provide
margin. The following design procedure can be used to select external component values for the TPS61378-Q1.
Table 9-1. Design Requirements
PARAMETERS
VALUES
Input Voltage
3.3 V to 6.4 V
Output Voltage
9.0 V
Switching Frequency
2.2 MHz
Output Current
800 mA
Output Voltage Ripple
± 25 mV
9.2.2 Detailed Design Procedure
9.2.2.1 Programming the Output Voltage
There are two ways to set the output voltage of the TPS61378-Q1: adjustable or fixed. If the resistance between
FB and GND is higher than 14.4 kΩ and less than 100kΩ during start-up, the TPS61378-Q1 works as an
adjustable output version. The FB pin is connected to the negative input of the internal error amplifier directly.
The output voltage can be programmed by adjusting the external resistor divider RUpper and RLower according to
Equation 3. When the output voltage is in well regulation, the typical voltage at the FB pin is VREF of 0.8 V.
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8176 = 84'( ×
(47LLAN + 4.KSAN )
4.KSAN
(3)
For some applications where the resistor needs to be as low as possible, the low-side divider can be 20 kΩ. The
reference voltage is 0.8 V and the high-side divider is 205 kΩ for 9-V output voltage.
For other applications without specific requirements on divider resistance, you can choose RLower to be
approximately 80.6 kΩ. Slightly increasing or decreasing RLower can result in closer output voltage matching
when using standard values resistors.
For the best accuracy, RLower is recommended to be smaller than 100 kΩ to ensure that the current flowing
through RLower is at least 100 times larger than FB pin leakage current. Changing RLower towards the lower
value increases the robustness against noise injection. Changing RLower to higher values reduces the quiescent
current to achieve higher efficiency at light load.
If the resistance between FB and GND is less than 9.6kΩ during start-up, the TPS61378-Q1 works as a fixed
output voltage version. The TPS61378-Q1 uses the internal resistor divider.
For 5-V fixed output voltage, RLower is between 0Ω and 2.4kΩ and RUpper should be removed.
For 5.25-V fixed output voltage, RLower is between 3.6kΩ and 4.8 kΩ and RUpper should be removed.
For 5.5-V fixed output voltage, RLower is between 7.2kΩ and 9.6kΩ and RUpper should be removed.
9.2.2.2 Setting the Switching Frequency
The switching frequency of the TPS61378-Q1 is set at 2.2 MHz. Use Equation 1 to calculate the required resistor
value. The calculated value is 18 kΩ to get the frequency of 2.2 MHz.
9.2.2.3 Setting the Current Limit
The current limit of the TPS61378-Q1 can be programmed by an external resistor. For a target current limit of 4.8
A, use Equation 2. The calculated resistor value is 20 kΩ.
9.2.2.4 Selecting the Inductor
A boost converter normally requires two main passive components for storing energy during power conversion:
an inductor and an output capacitor. The inductor affects the steady state efficiency (including the ripple and
efficiency), transient behavior, and loop stability, which makes the inductor the most critical component in
application.
When selecting the inductor and the inductance, the other important parameters are:
•
•
•
The maximum current rating (RMS and peak current should be considered)
The series resistance
Operating temperature
The TPS61378-Q1 has built-in slope compensation to avoid subharmonic oscillation associated with current
mode control. If the inductor value is too low and makes the inductor peak-to-peak ripple higher than 2 A, the
slope compensation may not be adequate, and the loop can be unstable. Therefore, it is recommended to make
the peak-to-peak current ripple between 800 mA to 2 A when selecting the inductor.
The inductance can be calculated by Equation 4, Equation 5, and Equation 6:
DIL =
VIN ´ D
L ´ fSW
DIL _ R = Ripple% ´
L=
(4)
VOUT ´ IOUT
h ´ VIN
(5)
h ´ VIN
V ´D
1
´
´ IN
Ripple % VOUT ´ IOUT
ƒSW
(6)
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where
•
•
•
•
•
•
•
•
•
ΔIL is the peak-peak inductor current ripple
VIN is the input voltage
D is the duty cycle
L is the inductor
ƒSW is the switching frequency
Ripple % is the ripple ration versus the DC current
VOUT is the output voltage
IOUT is the output current
η is the efficiency
The current flowing through the inductor is the inductor ripple current plus the average input current. During
power up, load faults, or transient load conditions, the inductor current can increase above the peak inductor
current calculated.
Inductor values can have ±20%, or even ±30%, tolerance with no current bias. When the inductor current
approaches the saturation level, the inductance can decrease 20% to 35% from the value at 0-A bias current,
depending on how the inductor vendor defines saturation. When selecting an inductor, make sure the rated
current, especially the saturation current, is larger than its peak current during the operation.
The inductor peak current varies as a function of the load, switching frequency, and input and output voltages.
The peak current can be calculated with Equation 7 and Equation 8.
IPEAK = IIN +
1
´ DIL
2
(7)
where
•
•
•
IPEAK is the peak current of the inductor
IIN is the input average current
ΔIL is the ripple current of the inductor
The input DC current is determined by the output voltage. The output current can be calculated by:
IIN =
VOUT ´ IOUT
VIN ´ h
(8)
where
•
•
•
•
IIN is the input current of the inductor
VOUT is the output voltage
VIN is the input voltage
η is the efficiency
While the inductor ripple current depends on the inductance, the frequency, the input voltage, and duty cycle are
calculated by Equation 4. Replace Equation 4 and Equation 8 into Equation 7 and get the inductor peak current:
IPEAK =
IOUT
1 V ´D
+ ´ IN
(1 - D) ´ h 2 L ´ fSW
(9)
where
•
•
•
•
•
•
18
IPEAK is the peak current of the inductor
IOUT is the output current
D is the duty cycle
η is the efficiency
VIN is the input voltage
L is the inductor
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ƒSW is the switching frequency
The heat rating current (RMS) is can be calculated with Equation 10:
IL _ RMS = IIN 2 +
1
( DIL )2
12
(10)
where
•
•
•
IL_RMS is the RMS current of the inductor
IIN is the input current of the inductor
ΔIL is the ripple current of the inductor
It is important that the peak current does not exceed the inductor saturation current and the RMS current is not
over the temperature-related rating current of the inductors.
For a given physical inductor size, increasing inductance usually results in an inductor with lower saturation
current. The total losses of the coil consists of the DC resistance (DCR) loss and the following frequencydependent loss:
•
•
•
The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
Additional losses in the conductor from the skin effect (current displacement at high frequencies)
Magnetic field losses of the neighboring windings (proximity effect)
For a certain inductor, the larger current ripple (smaller inductor) generates the higher DC and also the
frequency-dependent loss. An inductor with lower DCR is basically recommended for higher efficiency. However,
it is usually a tradeoff between the loss and foot print. Table 9-2 lists some recommended inductors.
Table 9-2. Recommended Inductors
PART NUMBER
L (μH)
DCR TYP
(mΩ) MAX
SATURATION
CURRENT (A)
SIZE (L × W × H mm)
VENDOR(1)
XEL4030-471MEB
0.47
4.1
15.5
4x4x3
Coilcraft
XEL4030-102MEB
1
8.9
9
4x4x3
Coilcraft
DFE2HCAHR47MJ0L
0.47
25
5.1
2.5 x 2 x 1.2
Murata
DFE322520FD-1R0M
1
22
7.5
3.2 x 2.5 x 2
Murata
TFM322512ALMAR47MTAA
0.47
16
7.6
3.2 x 2.5 x 1.2
TDK
TFM322512ALMA1R0MTAA
1
30
5.1
3.2 x 2.5 x 1.2
TDK
(1)
See the Third-party Products Disclaimer.
9.2.2.5 Selecting the Output Capacitors
The output capacitor is mainly selected to meet the requirements at load transient or steady state. The loop
is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series
resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum
capacitance needed for a given ripple can be calculated by Equation 11:
COUT =
IOUT ´ (VOUT - VIN )
fSW ´ DV ´ VOUT
(11)
where
•
•
•
•
•
•
COUT is the output capacitor
IOUT is the output current
VOUT is the output voltage
VIN is the input voltage
ΔV is the output voltage ripple required
ƒSW is the switching frequency
The additional output ripple component caused by ESR is calculated by Equation 12:
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DVESR = IOUT ´ RESR
(12)
where
•
•
ΔVESR is the output voltage ripple caused by ESR
RESR is the resistor in series with the output capacitor
For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors,
it must be considered if used.
The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using
Equation 13:
COUT =
DISTEP
2p ´ fBW ´ DVTRAN
(13)
where
•
•
•
ΔISTEP is the transient load current step
ΔVTRAN is the allowed voltage dip for the load current step
ƒBW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)
For the output capacitor on the OUT pin, the effective capacitance is recommended between 0.22 μF to 1 μF.
Take care when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors can
derate by as much as 70% of the capacitance at the respective rated voltage. Therefore, enough margins on the
voltage rating must be considered to ensure adequate capacitance at the required output voltage.
9.2.2.6 Selecting the Input Capacitors
Multilayer ceramic capacitors are an excellent choice for the input decoupling of the step-up converter since
they have extremely low ESR and are available in small footprints. Input capacitors must be located as close as
possible to the device. While a 22-µF input capacitor or equivalent is sufficient for the most applications, larger
values can be used to reduce input current ripple.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or can even
damage the device. Additional "bulk" capacitance (electrolytic or tantalum) in this circumstance, must be placed
between CIN and the power source lead to reduce ringing that can occur between the inductance of the power
source leads and CIN.
9.2.2.7 Loop Stability and Compensation
9.2.2.7.1 Small Signal Model
The TPS61378-Q1 uses the fixed frequency peak current mode control. There is an internal adaptive slope
compensation to avoid subharmonic oscillation. With the inductor current information sensed, the small-signal
model of the power stage reduces from a two-pole system, created by L and COUT, to a single-pole system,
created by ROUT and COUT. The single-pole system is easily used with the loop compensation. Figure 9-2 shows
the equivalent small signal elements of a boost converter.
20
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L
VIN
VOUT
CIN
Q
ROUT
RSENSE
Slope
Comp
Q
COUT
ISENSE
VOUT
RUP
S
Q
R
RESR
FB
+
GEA
Cc
Cp
VREF
RDOWN
REA
RC
Figure 9-2. TPS61378-Q1 Control Equivalent Circuitry Model
The small signal of power stage is:
5
5
4176 × (1 F &) (1 + 2è × B'54 )(1 F 2è × B4*2 )
-25 (5) =
×
5
2 × 45'05'
(1 +
)
2è × B2
(14)
where
•
•
•
D is the duty cycle
ROUT is the output load resistor
RSENSE is the equivalent internal current sense resistor, which is typically 118 mΩ
The single pole of the power stage is:
fP =
2
2p ´ ROUT ´ COUT
(15)
where
•
COUT is the output capacitance. For a boost converter having multiple identical output capacitors in parallel,
simply combine the capacitors with the equivalent capacitance
The zero created by the ESR of the output capacitor is:
fESR =
1
2p ´ RESR ´ COUT
(16)
where
•
RESR is the equivalent resistance in series of the output capacitor
The right-hand plane zero is:
fRHP =
ROUT ´ (1 - D)2
2p ´ L
(17)
where
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•
•
•
D is the duty cycle
ROUT is the output load resistor
L is the inductance
Equation 18 shows the equation for feedback resistor network and the error amplifier.
RDOWN
HEA (S) = GEA ´ REA ´
´
RUP + RDOWN
1+
(1 +
S
2 ´ p ´ fZ
S
S
) ´ (1 +
)
2 ´ p ´ fP1
2 ´ p ´ fP2
(18)
where
•
•
•
REA is the output impedance of the error amplifier, typically REA = 500 MΩ
ƒP1, ƒP2 is the pole's frequency of the compensation
fZ is the zero’s frequency of the compensation network
1
fP1 =
2p ´ REA ´ Cc
(19)
where
•
CC is the zero capacitor compensation
fP2 =
1
2p ´ RC ´ CP
(20)
where
•
•
CP is the pole capacitor compensation
RC is the resistor of the compensation network
fZ =
1
2p ´ RC ´ CC
(21)
9.2.2.7.2 Loop Compensation Design Steps
With the small signal models coming out, the next step is to calculate the compensation network parameters with
the given inductor and output capacitance.
1. Set the Crossover Frequency, ƒC.
The first step is to set the loop crossover frequency, ƒC. The higher the crossover frequency, the faster
the loop response is. It is generally accepted that the loop gain crosses over no higher than the lower of
either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then, calculate the loop
compensation network values of RC, CC, and CP by the following equations.
2. Set the Compensation Resistor, RC.
By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~ = RC, so RC × GEA sets the compensation
gain. Setting the compensation gain, KCOMP-dB, at ƒZ results in the total loop gain, T(s) = KPS(s) × HEA(s),
being zero at ƒC.
Therefore, to approximate a single-pole rolloff up to fP2, rearrange Equation 18 to solve for RC so that the
compensation gain, KEA, at fC is the negative of the gain, KPS. Read at frequency fC for the power stage
bode plot or more simply:
KEA (fC ) = 20 ´ log(GEA ´ RC ´
22
RDOWN
) = - KPS (fC )
RUP + RDOWN
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where
• KEA is gain of the error amplifier network
• KPS is the gain of the power stage
• GEA is the transconductance of the amplifier, the typical value of GEA = 70 µA / V
3. Set the Compensation Zero capacitor, CC.
Place the compensation zero at the power stage ROUT ,COUT pole’s position to get:
fZ =
1
2p ´ RC ´ CC
(23)
Set ƒZ = ƒP, and get:
CC =
ROUT ´ COUT
2RC
(24)
4. Set the Compensation Pole Capacitor, CP.
Place the compensation pole at the zero produced by RESR and COUT. It is useful for canceling unhelpful
effects of the ESR zero.
fP2 =
1
2p ´ RC ´ CP
fESR =
(25)
1
2p ´ RESR ´ COUT
(26)
Set ƒP2 = ƒESR, and get:
CP =
RESR ´ COUT
RC
(27)
9.2.2.7.3 Selecting the Bootstrap Capacitor
The bootstrap capacitor between the BST and SW pin supplies the gate current to charge the high-side FET
device gate during the turnon of each cycle. The gate current also supplies charge for the bootstrap capacitor.
The recommended value of the bootstrap capacitor is 0.1 µF to 1 µF. CBST must be a good quality, low-ESR
ceramic capacitor located at the pins of the device to minimize potentially damaging voltage transients caused
by trace inductance. A value of 0.1 µF was selected for this design example.
9.2.2.7.4 VCC Capacitor
The primary purpose of the VCC capacitor is to supply the peak transient currents of the driver and bootstrap
capacitor and provide stability for the VCC regulator. The value of CVCC must be at least 10 times greater than the
value of CBST, and must be a good quality, low-ESR ceramic capacitor. CVCC must be placed close to the pins
of the IC to minimize potentially damaging voltage transients caused by the trace inductance. A value of 2.2 µF
was selected for this design example.
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9.2.3 Application Curves
Figure 9-3. Switching Waveform VIN = 5 V,
VOUT = 9 V, IOUT = 800 mA, FPWM
Figure 9-4. Switching Waveform VIN = 5 V,
VOUT = 9 V, IOUT = 0 mA, Auto PFM
EN
2 V/div
SW
5 V/div
Vout
5 V/div
500 µs/div
Inductor
Current
2 A/div
Figure 9-5. Load Transient VIN = 5 V, VOUT = 9 V,
IOUT = 300 mA to 800 mA, FPWM
Figure 9-7. Shutdown from EN Waveforms
VIN = 5 V, VOUT = 9 V, IOUT = 500 mA, FPWM
24
Figure 9-6. Start-up from EN Waveform VIN = 5 V,
VOUT = 9 V, IOUT = 500 mA, FPWM
Figure 9-8. Short Circuit Protection VIN = 5 V,
VOUT = 9 V, FPWM
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Vout
5 V/div
SW
5 V/div
50 µ s/div
Inductor
Current
500 mA/div
Figure 9-9. Short Circuit Recovery VIN = 5 V,
VOUT = 9 V, IOUT = 0 mA, FPWM
Figure 9-10. Hiccup Short Circuit Protection
VIN = 5 V, VOUT = 9 V, FPWM
10 Power Supply Recommendations
The TPS61378-Q1 is designed to operate from an input voltage supply range between 2.3 V to 14 V. This input
supply must be well regulated. If the input supply is located more than a few inches from the device, the bulk
capacitance can be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value
of 47 µF is a typical choice.
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11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator can show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
paths. The input and output capacitor, as well as the inductor must be placed as close as possible to the IC.
11.2 Layout Example
The bottom layer is a large GND plane connected by vias.
GND
GND
FB
COMP
EN
FREQ
GND
VIN
ILIM
BST
PG
GND
SW
VIN
OUT
SW
VO
VO
GND
GND
VCC
MODE
/SYNC
SW
GND
Figure 11-1. Recommended Layout
26
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS613783QWRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2G8H
TPS613785QWRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2G9H
TPS61378QWRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2ELH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
