TPS62085, TPS62086, TPS62087
TPS62085,
TPS62087
SLVSB70C – OCTOBER
2013 TPS62086,
– REVISED JANUARY
2021
SLVSB70C – OCTOBER 2013 – REVISED JANUARY 2021
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TPS6208x, 3-A Step-Down Converter With Hiccup Short-Circuit Protection
in 2-mm × 2-mm VSON Package
1 Features
DCS-Control™ topology
Up to 95% efficiency
Hiccup short-circuit protection
Power save mode for light load efficiency
100% duty cycle for lowest dropout
2.5-V to 6.0-V input voltage range
17-μA operating quiescent current
0.8-V to VIN adjustable output voltage
1.8-V and 3.3-V fixed output voltage
Output discharge
Power good output
Thermal shutdown protection
Available in 2-mm × 2-mm VSON package
Create a custom design using the:
– TPS62085 WEBENCH® Power Designer
– TPS62086 WEBENCH® Power Designer
– TPS62087 WEBENCH® Power Designer
The TPS62085, TPS62086, and TPS62087 devices
are
high-frequency
synchronous
step-down
converters optimized for small solution size and high
efficiency. With an input voltage range of 2.5 V to
6.0 V, common battery technologies are supported.
The devices focus on high-efficiency step-down
conversion over a wide output current range. At
medium to heavy loads, the converter operates in
PWM mode and automatically enters Power Save
Mode operation at light load to maintain high
efficiency over the entire load current range.
To address the requirements of system power rails,
the internal compensation circuit allows a large
selection of external output capacitor values ranging
from 10 µF to 150 µF. Together with its DCS-Control
architecture, excellent load transient performance and
output voltage regulation accuracy are achieved. The
devices are available in a 2-mm × 2-mm VSON
package.
2 Applications
•
•
•
•
Device Information
Battery-powered applications
Point-of-load
Processor supplies
Hard disk drives
TPS62087
VIN
SW
EN
VOS
TPS62086
VSON (7)
2.00 mm × 2.00 mm
TPS62087
L1
0.47µH
For all available packages, see the orderable addendum at
the end of the data sheet.
100
R3
1M
C2
22µF
VOUT
1.8V/3A
FB
GND
BODY SIZE (NOM)
TPS62085
(1)
VIN
2.5V to 6V C1
10µF
PACKAGE(1)
PART NUMBER
PG
POWER GOOD
Typical Application Schematic
90
Efficiency (%)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3 Description
80
70
Vin = 2.5V
Vin = 3.3V
Vin = 4.2V
Vin = 5.0V
60
Vout = 1.8 V
50
0.001
0.010
0.100
1.000
Iout (A)
C004
Typical Application Efficiency
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 6
8 Detailed Description........................................................7
8.1 Overview..................................................................... 7
8.2 Functional Block Diagram........................................... 7
8.3 Feature Description.....................................................7
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
11.3 Thermal Considerations.......................................... 16
12 Device and Documentation Support..........................17
12.1 Device Support....................................................... 17
12.2 Documentation Support.......................................... 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks............................................................. 17
12.6 Electrostatic Discharge Caution..............................18
12.7 Glossary..................................................................18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (July 2018) to Revision C (January 2021)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Changed maximum IPG,LKG specification up to 125°C TJ from 0.16 µA to 0.25 µA in Electrical Characteristics
table.................................................................................................................................................................... 5
Changes from Revision A (June 2015) to Revision B (July 2018)
Page
• Changed package name from QFN to VSON in the Features list...................................................................... 1
• Added Webench links to the data sheet ............................................................................................................ 1
• Added SW node AC value in Absolute Maximum Ratings table ........................................................................4
• Changed fPFM To: fPSM in Equation 1 .................................................................................................................7
• Added Figure 8-1 to Power Save Mode section................................................................................................. 7
• Added Table 8-1 to Power Good section ........................................................................................................... 9
• Changed Murata inductor part number in Table 9-4 ........................................................................................ 11
Changes from Revision * (October 2013) to Revision A (June 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
2
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5 Device Options
(1)
PART NUMBER(1)
OUTPUT VOLTAGE
TPS62085RLT
Adjustable
TPS62086RLT
3.3 V
TPS62087RLT
1.8 V
For detailed ordering information, please check the Section Mechanical, Packaging, and Orderable Information section at the end of
this datasheet.
6 Pin Configuration and Functions
EN
1
PG
2
FB
3
VOS
4
7
VIN
6
SW
5
GND
Figure 6-1. RLT Package 7-Pin VSON Top View
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
1
IN
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device.
This pin has a pulldown resistor of typically 400 kΩ when the device is disabled.
FB
3
IN
Feedback pin. For the fixed output voltage versions this pin must be connected to the output voltage.
GND
5
PG
2
OUT
Power good open drain output pin. The pullup resistor can not be connected to any voltage higher than 6 V. If
unused, leave it floating.
SW
6
PWR
Switch pin of the power stage.
VIN
7
PWR
Input voltage pin.
VOS
4
IN
Ground pin.
Output voltage sense pin. This pin must be directly connected to the output capacitor.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Voltage at Pins(2)
Temperature
(1)
(2)
(3)
MIN
MAX
VIN, FB, VOS, EN, PG
–0.3
7
SW (DC)
UNIT
–0.3
VIN + 0.3
SW (AC, less than 100ns)(3)
–3
11
V
Operating Junction, TJ
–40
150
°C
Storage, Tstg
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
While switching.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN(1)
VIN
Input voltage range
ISINK_PG
Sink current at PG pin
NOM
2.5
VPG
Pullup resistor voltage
TJ
Operating junction temperature
(1)
Refer to Section 9 for further information.
–40
MAX(1)
UNIT
6
V
1
mA
6
V
125
°C
7.4 Thermal Information
TPS6208x
THERMAL METRIC(1)
RLT [VSON]
UNIT
7 PINS
4
RθJA
Junction-to-ambient thermal resistance
107.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66.2
°C/W
RθJB
Junction-to-board thermal resistance
17.1
°C/W
ψJT
Junction-to-top characterization parameter
2.1
°C/W
ψJB
Junction-to-board characterization parameter
17.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
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7.5 Electrical Characteristics
TJ = –40 °C to 125 °C, and VIN = 3.6 V. Typical values are at TJ = 25 °C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
IQ
Quiescent current into VIN
No load, device not switching
TJ = –40 °C to 85 °C, VIN = 2.5 V to 5.5 V
ISD
Shutdown current into VIN
EN = Low,
TJ = –40 °C to 85 °C, VIN = 2.5 V to 5.5 V
Undervoltage lockout threshold
VIN falling
Undervoltage lockout hysteresis
VIN rising
200
mV
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
VUVLO
TJSD
2.5
2.1
6
V
17
25
µA
0.7
5
µA
2.2
2.3
V
LOGIC INTERFACE EN
VIH
High-level input voltage
VIN = 2.5 V to 6.0 V
VIL
Low-level input voltage
VIN = 2.5 V to 6.0 V
1.0
V
0.4
0.16
V
IEN,LKG
Input leakage current into EN pin
EN = High
0.01
RPD
Pulldown resistance at EN pin
EN = Low
400
kΩ
µA
Time from EN high to 95% of VOUT nominal
0.8
ms
SOFT START, POWER GOOD
tSS
Soft-start time
VPG
Power good threshold
VOUT rising, referenced to VOUT nominal
93%
95%
98%
VOUT falling, referenced to VOUT nominal
88%
90%
93%
VPG,OL
Low-level output voltage
Isink = 1 mA
0.4
V
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V, TJ = –40 °C to 85 °C
0.01
0.16
µA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
0.01
0.25
µA
V
OUTPUT
Output voltage range, TPS62085
VOUT
Output voltage accuracy,
TPS62086, TPS62087(1)
0.8
VIN
IOUT = 1 A, VIN ≥ VOUT + 1 V, PWM mode
–1.0%
1.0%
IOUT = 0 A, VIN ≥ VOUT + 1 V, PSM mode
–1.0%
IOUT = 1A , VIN ≥ VOUT + 1 V, PWM mode
792
800
808
IOUT = 0 A, VIN ≥ VOUT + 1 V, PSM mode
792
800
817
0.01
0.1
2.1%
VFB
Feedback regulation voltage(1) (2)
IFB,LKG
Feedback input leakage current
VFB = 1 V
RDIS
Output discharge resistor
EN = LOW, VOUT = 1.8 V
260
Ω
Line regulation
IOUT = 1 A, VIN = 2.5 V to 6.0 V
0.02
%/V
Load regulation
IOUT = 0.5 A to 3 A
0.16
%/A
mV
µA
POWER SWITCH
RDS(on)
High-side FET ON-resistance
ISW = 500 mA
31
56
mΩ
Low-side FET ON-resistance
ISW = 500 mA
23
45
mΩ
4.6
5.5
A
ILIM
High-side FET switch current limit
fSW
PWM switching frequency
(1)
(2)
3.7
IOUT = 1 A
2.4
MHz
For more information, see Section 8.3.1.
Conditions: L = 0.47 μH, COUT = 22 μF
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7.6 Typical Characteristics
Switching Frequency (Hz)
10M
1M
100k
10k
Vin = 2.5 V
Vin = 3.6 V
Vin = 6.0 V
Vout = 1.2 V
1000
0.001
0.010
0.100
1.000
Iout (A)
C007
Figure 7-1. Switching Frequency
6
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8 Detailed Description
8.1 Overview
The TPS62085, TPS62086, and TPS62087 synchronous step-down converters are based on the DCS-Control
(Direct Control with Seamless transition into Power Save Mode) topology. This is an advanced regulation
topology that combines the advantages of hysteretic, voltage, and current mode control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 2.4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
quiescent current to achieve high efficiency over the entire load current range. Because DCS-Control supports
both operation modes (PWM and PSM) within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage. Fixed output voltage version provides smallest
solution size combined with lowest no load current. The devices offer both excellent DC voltage and superior
load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.
8.2 Functional Block Diagram
PG
Hiccup
Counter
VFB
VREF
EN
400 kΩ
(2)
VIN
High Side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
SW
MOSFET Driver
Control Logic
GND
Ramp
Comparator
Timer
ton
Direct Control
and
Compensation
VOS
R1
(1)
R2
(1)
FB
Error Amplifier
DCS - Control
TM
EN
VREF
260 Ω
Output Discharge
Logic
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 400 kΩ resistor is disconnected.
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the TPS62085, TPS62086, and TPS62087 enter Power Save Mode (PSM)
operation. During Power Save Mode, the converter operates with reduced switching frequency and with a
minimum quiescent current maintaining high efficiency. The power save mode occurs when the inductor current
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becomes discontinuous. Power Save Mode is based on a fixed on-time architecture, as related in Equation 1.
The switching frequency over the whole load current range is also shown in Figure 7-1 for a typical application.
t ON = 420 ns ´
V OUT
V IN
2 ´ I OUT
f PSM =
t ON2 ´
V IN
V OUT
´
V IN - V OUT
L
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage, as shown in Figure 9-7.
This effect is minimized by increasing the output capacitor or inductor value. The output voltage accuracy in
PSM operation is reflected in the electrical specification table and given for a 22-μF output capacitor.
During PAUSE period in PSM (shown in Figure 8-1 ), the device does not change the PG pin state nor does it
detect an UVLO event, in order to achieve a minimum quiescent current and maintain high efficiency at light
loads.
VOUT
tPAUSE
IINDUCTOR
tON
Figure 8-1. Power Save Mode Waveform Diagram
8.3.2 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )
(2)
with
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
8.3.3 Soft Start
The TPS62085, TPS62086, and TPS62087 have an internal soft-start circuitry which monotonically ramps up the
output voltage and reaches the nominal output voltage during a soft-start time of typically 0.8 ms. This avoids
excessive inrush current and creates a smooth output voltage slope. It also prevents excessive voltage drops of
primary cells and rechargeable batteries with high internal impedance. The device is able to start into a
prebiased output capacitor. The device starts with the applied bias voltage and ramps the output voltage to its
nominal value.
8
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8.3.4 Switch Current Limit and Hiccup Short-Circuit Protection
The switch current limit prevents the devices from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET is turned on to ramp down the inductor current. When this switch current
limits is triggered 32 times, the devices stop switching and enable the output discharge. The devices then
automatically start a new start-up after a typical delay time of 66 µs has passed. This is named HICCUP shortcircuit protection. The devices repeat this mode until the high load condition disappears.
8.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the devices at voltages lower than VUVLO with a hysteresis of 200 mV.
8.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Functional Modes
8.4.1 Enable and Disable
The devices are enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN
pin is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 260 Ω discharges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, UVLO, or short-circuit protection are triggered.
An internal pulldown resistor of 400 kΩ is connected to the EN pin when the EN pin is LOW. The pulldown
resistor is disconnected when the EN pin is HIGH.
8.4.2 Power Good
The TPS62085, TPS62086, and TPS62087 have a power good output. The power good goes high impedance
once the output is above 95% of the nominal voltage, and is driven low once the output voltage falls below
typically 90% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power good output requires a pullup resistor connecting to any voltage rail less than 6 V. The PG signal can be
used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin
unconnected when not used. Table 8-1 shows the PG pin logic.
Table 8-1. PG Pin Logic
DEVICE CONDITIONS
Enable
EN = High, VFB ≥ VPG
LOGIC STATUS
HIGH Z
LOW
√
EN = High, VFB < VPG
√
Shutdown
EN = Low
√
Thermal Shutdown
TJ > TJSD
√
UVLO
0.5 V < VIN < VUVLO
√
Power Supply
Removal
VIN ≤ 0.5 V
√
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS62085 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using typical applications as a reference. The TPS62086
and TPS62087 devices provide a fixed output voltage which does not need an external resistor divider.
9.2 Typical Application
TPS62085
VIN
2.5V to 6V C1
10µF
EN
L1
0.47µH
VOUT
1.2V/3A
SW
VIN
VOS
R1
80.6k
R3
1M
C2
22µF
FB
GND
PG
R2
162k
POWER GOOD
Figure 9-1. 1.2-V Output Voltage Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.5 V to 6 V
Output voltage
1.2 V
Output ripple voltage
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