TPS62088, TPS62088A, TPS62089A
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
TPS62088 and TPS6208xA, 2.4-V to 5.5-V Input, Tiny 6-Pin 2-A/3-A Step-Down
Converter in 1.2-mm × 0.8-mm Wafer Chip Scale Package and Suitable for Embedding
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The TPS6208xx device family is a high-frequency
synchronous step-down converters optimized for
small solution size and high efficiency. With an
input voltage range of 2.4 V to 5.5 V, common
battery technologies are supported. At medium
to heavy loads, the converter operates in PWM
mode and automatically enters power save mode
operation at light load to maintain high efficiency
over the entire load current range. The forced PWM
version of the device maintains a CCM operation
across any load. The 4-MHz switching frequency
allows the device to use small external components.
Together with its DCS-control architecture, excellent
load transient performance, and output voltage
regulation accuracy are achieved. Other features like
overcurrent protection, thermal shutdown protection,
active output discharge, and power good are built in.
The device is available in a 6-pin WCSP package.
•
•
•
(1)
TPS6208818
VIN
R3
100 k
C1
4.7 µF
TPS62088
TPS62088A
Solid-state drives
Wearable products
Smartphones
Camera modules
Optical modules
VIN
2.4 V to 5.5 V
PART NUMBER
TPS62089A
2 Applications
•
•
•
•
•
Device Information
EN
YFP (6)
0.8 mm × 1.2 mm × 0.5 mm
YWC (6)
0.8 mm × 1.2 mm × 0.3 mm
95
SW
FB
BODY SIZE (NOM)
100
VOUT
1.8 V
L1
0.24 µH
PACKAGE(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
90
C2
10 µF
VPG
PG GND
Copyright Ú 2017, Texas Instruments Incorporated
Typical Application Schematic
C3
10 µF
85
Efficiency (%)
•
DCS-Control topology
Up to 95% efficiency
26-mΩ and 26-mΩ internal power MOSFETs
2.4-V to 5.5-V input voltage range
4-μA operating quiescent current
1% output voltage accuracy
4-MHz switching frequency
Power save mode for light-load efficiency
A forced-PWM version for CCM operation
100% duty cycle for lowest dropout
Active output discharge
Power good output
Thermal shutdown protection
Hiccup short-circuit protection
Available in 6-pin WCSP and PowerWCSP with
0.4-mm pitch
0.3-mm tall YWC package supports embedded
systems
Supports 12 mm2 solution size
Supports < 0.6 mm height solution
Create a custom design using the TPS62088 with
the WEBENCH® Power Designer
80
75
70
65
60
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
55
50
45
40
100P
1m
10m
Load (A)
100m
1
3
D007
3.3-V Input Voltage Efficiency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings .............................................................. 4
7.3 Recommended Operating Conditions ........................4
7.4 Thermal Information ..................................................4
7.5 Electrical Characteristics ............................................5
7.6 Typical Characteristics................................................ 6
8 Detailed Description........................................................7
8.1 Overview..................................................................... 7
8.2 Functional Block Diagram........................................... 7
8.3 Feature Description.....................................................7
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 Device Support....................................................... 21
12.2 Documentation Support.......................................... 21
12.3 Receiving Notification of Documentation Updates..21
12.4 Support Resources................................................. 21
12.5 Trademarks............................................................. 21
12.6 Electrostatic Discharge Caution..............................22
12.7 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2019) to Revision E (November 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document. ................1
• Added information for the FPWM devices.......................................................................................................... 3
• Added new curves for FPWM devices..............................................................................................................14
Changes from Revision C (May 2019) to Revision D (September 2019)
Page
• Changed TPS62088YWC status to production.................................................................................................. 1
• Added TPS62088YWCEVM-084 to the Thermal information table.................................................................... 4
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
5 Device Options
Device Options
(1)
PART NUMBER(1)
OPERATION MODE
OUTPUT VOLTAGE
TPS62088YFP
PFM/PWM
3-A adjustable
TPS62088YWC
PFM/PWM
3-A adjustable
TPS6208812YFP
PFM/PWM
3 A with 1.2 V
TPS6208818YFP
PFM/PWM
3 A with 1.8 V
TPS6208833YFP
PFM/PWM
3 A with 3.3 V
TPS62088AYFP
Forced-PWM
3-A adjustable
TPS62089AYFP
Forced-PWM
2-A adjustable
For detailed ordering information, please check the package option addendum section at the end of this data sheet.
6 Pin Configuration and Functions
1
2
1
2
A
EN
VIN
A
EN
VIN
B
PG
SW
B
PG
SW
C
FB
GND
C
FB
GND
Figure 6-1. YFP Package Top View
Figure 6-2. YWC Package Top View
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
A1
I
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
PG
B1
O
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
FB
C1
I
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
output.
GND
C2
—
Ground pin
SW
B2
O
Switch pin of the power stage
VIN
A2
I
Input voltage pin
NAME
NO.
EN
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
3
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
MIN
Voltage at pins (2)
Temperature
(1)
(2)
(3)
MAX
VIN, FB, EN, PG
–0.3
6
SW (DC)
–0.3
VIN + 0.3
SW (DC, in current limit)
–1.0
VIN + 0.3
SW (AC, less than 10 ns) (3)
–2.5
10
Operating junction temperature, TJ
–40
150
Storage temperature, Tstg
–65
150
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
While switching.
7.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
VALUE
UNIT
±2000
V
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input voltage range
2.4
5.5
V
VOUT
Output voltage range
0.6
4.0
V
IOUT
Output current range, TPS62089A
0
2
A
0
3
A
1
mA
IOUT
Output current range, TPS62088, TPS62088A
ISINK_PG
Sink current at the PG pin
VPG
Pullup resistor voltage
TJ
Operating junction temperature
(1)
(1)
-40
5.5
V
125
°C
For YFP package versions, lifetime is reduced when operating continuously at 3-A output current with the junction temperature higher
than 85°C.
7.4 Thermal Information
TPS62088/TPS6208xA
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
UNIT
YWC (6 PINS)
YFP EVM-814
YWC EVM-084
141.3
130.9
85.7
70.6
(2)
°C/W
Junction-to-case (top) thermal resistance
1.7
1.1
n/a
RθJB
Junction-to-board thermal resistance
47.3
27.3
n/a (2)
n/a (2)
°C/W
ψJT
Junction-to-top characterization parameter
0.5
0.7
1.9
0.5
°C/W
ψJB
Junction-to-board characterization
parameter
47.5
27.2
55.9
38.7
°C/W
(2)
n/a
°C/W
(2)
RθJC(top)
(1)
4
6 PINS
YFP (6 PINS)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Not applicable to an EVM.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
7.5 Electrical Characteristics
TJ = –40°C to 125°C, and VIN = 2.4 V to 5.5 V. Typical values are at TJ = 25°C and VIN = 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
SUPPLY
IQ
Quiescent current
EN = HIGH, no load, device not switching
4
IQ
Quiescent current
EN = HIGH, no load, TPS62088A and TPS62089A
8
ISD
Shutdown current
EN = LOW, TJ = –40℃ to 85℃
Undervoltage lockout threshold
VIN falling
Undervoltage lockout hysteresis
VIN rising
160
mV
Thermal shutdown threshold
TJ rising
150
°C
Thermal shutdown hysteresis
TJ falling
20
°C
VUVLO
TJSD
2.1
µA
mA
0.05
0.5
2.2
2.3
µA
V
LOGIC INTERFACE EN
VIH
High-level input threshold voltage
VIL
Low-level input threshold voltage
IEN,LKG
Input leakage current into EN pin
1.0
V
0.01
0.4
V
0.1
µA
SOFT START, POWER GOOD
tSS
Soft-start time
Time from EN high to 95% of VOUT nominal
VPG rising, VFB referenced to VFB nominal
Power-good lower threshold
VPG
Power-good upper threshold
1.25
94%
96%
ms
98%
VPG falling, VFB referenced to VFB nominal
90%
92%
94%
VPG rising, VFB referenced to VFB nominal
103%
105%
107%
VPG falling, VFB referenced to VFB nominal
108%
110%
112%
VPG,OL
Low-level output voltage
Isink = 1 mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0 V
0.4
V
0.01
0.1
µA
OUTPUT
VOUT
Output voltage accuracy
TPS6208812, PWM mode
1.188
1.2
1.212
TPS6208818, PWM mode
1.782
1.8
1.818
TPS6208833, PWM mode
3.267
3.3
3.333
594
600
606
mV
0.01
0.05
µA
VFB
Feedback regulation voltage
PWM mode
IFB,LKG
Feedback input leakage current
TPS62088, VFB = 0.6 V
RFB
Internal resistor divider connected to FB
pin
TPS6208812, TPS6208818, TPS6208833
IDIS
Output discharge current
VSW = 0.4V; EN = LOW
75
V
7.5
MΩ
400
mA
26
mΩ
POWER SWITCH
RDS(on)
High-side FET on-resistance
Low-side FET on-resistance
26
mΩ
ILIM
High-side FET switch current limit
TPS62089A
2.7
3.3
3.9
A
ILIM
High-side FET switch current limit
TPS62088 and TPS62088A
3.6
4.3
5.0
A
ILIM
Low-side FET switch negative current limit
TPS62088A and TPS62089A
fSW
PWM switching frequency
IOUT = 1 A, VOUT = 1.8 V
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
-1.6
4
A
MHz
Submit Document Feedback
5
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
70.0
70.0
60.0
60.0
50.0
50.0
RDS(on) (mOhm)
RDS(on) (mOhm)
7.6 Typical Characteristics
40.0
30.0
20.0
10.0
0.0
2.5
30.0
20.0
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
3.0
40.0
10.0
3.5
4.0
4.5
Input Voltage (V)
5.0
0.0
2.5
5.5
$
6.0
6KXWGRZQ &XUUHQW
$
4XLHVFHQW &XUUHQW
4.0
4.5
Input Voltage (V)
5.0
5.5
D011
0.5
0.4
4.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
3.0
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
0.3
0.2
0.1
3.5
4.0
4.5
Input Voltage (V)
5.0
Figure 7-3. Quiescent Current
6
3.5
Figure 7-2. Low-Side FET On-Resistance
8.0
0.0
2.5
3.0
D010
Figure 7-1. High-Side FET On-Resistance
2.0
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
5.5
0.0
2.5
3.0
3.5
D001
4.0
4.5
Input Voltage (V)
5.0
5.5
D000
Figure 7-4. Shutdown Current
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
8 Detailed Description
8.1 Overview
The TPS62088xx family is synchronous step-down converter that adopts a new generation DCS-Control (Direct
Control with Seamless transition into power save mode) topology without the output voltage sense (VOS) pin.
This is an advanced regulation topology that combines the advantages of hysteretic, voltage, and current mode
control schemes.
The DCS-Control topology operates in PWM (pulse width modulation) mode for medium to heavy load conditions
and in power save mode at light load currents. In PWM mode, the converter operates with its nominal switching
frequency of 4 MHz, having a controlled frequency variation over the input voltage range. As the load current
decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the IC
current consumption to achieve high efficiency over the entire load current range. In forced PWM devices,
the converter maintains a continuous conduction mode operation and keeps the output voltage ripple very low
across the whole load range and at a nominal switching frequency of 4 MHz. Because DCS-Control supports
both operation modes (PWM and PFM) within a single building block, the transition from PWM mode to power
save mode is seamless and without effects on the output voltage. The devices offer both excellent DC voltage
and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with
RF circuits.
8.2 Functional Block Diagram
PG
VPG_H
Control Logic
VREF
UVLO
Thermal Shutdown
Startup
EN
VIN
+
±
VFB
VPG_L
+
±
GND
Peak Current Detect
VSW
TON
VIN
VSW
HICCUP
Direct Control
&
Compensation
VREF
Modulator
Comparator
FB
Zero Current Detect
Discharge
+
_EA
SW
Gate
Drive
GND
Fixed VOUT
GND
8.3 Feature Description
8.3.1 Power Save Mode
As the load current decreases, the device enters power save mode operation. The power save mode occurs
when the inductor current becomes discontinuous. Power save mode is based on a fixed on-time architecture,
as related in Equation 1.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
7
TPS62088, TPS62088A, TPS62089A
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
tON
250ns u
VOUT
VIN
www.ti.com
(1)
In power save mode, the output voltage rises slightly above the nominal output voltage. This effect is minimized
by increasing the output capacitor or inductor value.
When the device operates close to 100% duty cycle mode, the device cannot enter power save mode regardless
of the load current if the input voltage decreases to typically 10% above the output voltage. The device maintains
output regulation in PWM mode.
8.3.2 Pulse Width Modulation (PWM) Operation
At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in
continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with
stabilized switching frequency.
In forced-PWM devices, the device always operates in pulse width modulation in continuous conduction mode
(CCM).
8.3.3 100% Duty Cycle Low Dropout Operation
The devices offer low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. This is particularly
useful in battery powered applications to achieve the longest operation time by taking full advantage of the whole
battery voltage range. The minimum input voltage to maintain output regulation, depending on the load current
and output voltage can be calculated as:
VIN,MIN = VOUT + IOUT,MAX ´ (RDS(on) + RL )
(2)
where
•
•
•
•
VIN,MIN = Minimum input voltage to maintain an output voltage
IOUT,MAX = Maximum output current
RDS(on) = High-side FET ON-resistance
RL = Inductor ohmic resistance (DCR)
8.3.4 Soft Start
After enabling the device, there is a 250-µs delay before switching starts. Then, an internal soft start-up circuitry
ramps up the output voltage which reaches nominal output voltage during the start-up time of 1 ms. This avoids
excessive inrush current and creates a smooth output voltage rise slope. It also prevents excessive voltage
drops of primary cells and rechargeable batteries with high internal impedance.
The device is able to start into a pre-biased output capacitor. It starts with the applied bias voltage and ramps the
output voltage to its nominal value.
8.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a heavy
load or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET
is turned off and the low-side MOSFET remains off, while the inductor current flows through its body diode and
quickly ramps down.
When this switch current limits is triggered 32 times, the device stops switching. The device then automatically
starts a new start-up after a typical delay time of 128 µs has passed. This is named HICCUP short-circuit
protection. The device repeats this mode until the high load condition disappears.
8
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
In forced PWM devices, a negative current limit (ILIMN) is enabled to prevent excessive current flowing
backwards to the input. When the inductor current reaches ILIMN, the low-side MOSFET turns off and the
highside MOSFET turns on and kept on until TON time expires.
8.3.6 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, undervoltage lockout is implemented that shuts down
the device at voltages lower than VUVLO.
8.3.7 Thermal Shutdown
The device goes into thermal shutdown and stops the power stage switching when the junction temperature
exceeds TJSD. When the device temperature falls below the threshold by 20°C, the device returns to normal
operation automatically by switching the power stage again.
8.4 Device Functional Modes
8.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 50 nA. In shutdown mode, the internal power switches as well
as the entire control circuitry are turned off. An internal switch smoothly discharges the output through the SW
pin in shutdown mode. Do not leave the EN pin floating.
The typical threshold value of the EN pin is 0.89 V for rising input signal, and 0.62 V for falling input signal.
8.4.2 Power Good
The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 96%
and less than 105% of the nominal voltage, and is driven low once the voltage falls below typically 92% or higher
than 110% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The
power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG
falling edge has a deglitch delay of 20 µs.
Table 8-1. PG Pin Logic
DEVICE CONDITIONS
EN = HIGH, VFB ≥ 0.576 V
Enable
LOGIC STATUS
HIGH IMPEDANCE
EN = HIGH, VFB ≤ 0.552 V
EN = HIGH, VFB ≤ 0.63 V
LOW
√
√
√
EN = HIGH, VFB ≥ 0.66 V
√
Shutdown
EN = LOW
√
Thermal shutdown
TJ > TJSD
√
UVLO
0.7 V < VIN < VUVLO
√
Power supply removal
VIN < 0.7 V
undefined
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
9
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application
VIN
2.4 V to 5.5 V
TPS62088
VIN
C1
4.7 µF
R3
100 k
L1
0.24 µH
VOUT
1.8 V
SW
C2
10 µF
EN
C3
10 µF
R1
200 k
C4
120 pF
VPG
PG GND FB
R2
100 k
Copyright Ú 2017, Texas Instruments Incorporated
Figure 9-1. Typical Application of Adjustable Output
VIN
2.4 V to 5.5 V
TPS6208818
R3
100 k
C1
4.7 µF
VIN
SW
EN
FB
VOUT
1.8 V
L1
0.24 µH
C2
10 µF
C3
10 µF
VPG
PG GND
Copyright Ú 2017, Texas Instruments Incorporated
Figure 9-2. Typical Application of Fixed Output
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
10
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
2.4 V to 5.5 V
Output voltage
1.8 V
Maximum peak output current
3A
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
Table 9-2 lists the components used for the example.
Table 9-2. List of Components of Figure 9-1
REFERENCE
C1
C2, C3
(1)
MANUFACTURER(1)
DESCRIPTION
4.7 µF, Ceramic capacitor, 6.3 V, X7R, size 0603, JMK107BB7475MA
Taiyo Yuden
10 µF, Ceramic capacitor, 10 V, X7R, size 0603, GRM188Z71A106MA73D
Murata
C4
120 pF, Ceramic capacitor, 50 V, size 0603, GRM1885C1H121JA01D
Murata
L1
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
Murata
R1
Depending on the output voltage, 1%, size 0603
Std
R2
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
R3
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
See Third-party Products disclaimer.
Table 9-3. List of Components of Figure 9-2, Smallest Solution
REFERENCE
C1, C2, C3
(1)
DESCRIPTION
MANUFACTURER(1)
10 µF, Ceramic capacitor, 6.3 V, X5R, size 0402, GRM155R60J106ME47
Murata
L1
0.24 µH, Power Inductor, size 0603, DFE160810S-R24M (DFE18SANR24MG0)
Murata
R3
100 kΩ, Chip resistor, 1/16 W, size 0402
Std
See Third-party Products disclaimer.
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Setting The Output Voltage
Choose resistors R1 and R2 to set the output voltage within a range of 0.6V to 4V, according to Equation 3. To
keep the feedback (FB) net robust from noise, set R2 equal to or lower than 100 kΩ to have at least 0.6 µA of
current in the voltage divider. Lower values of FB resistors achieve better noise immunity, and lower light load
efficiency, as explained in the Design Considerations For A Resistive Feedback Divider In A DC/DC Converter
Analog Design Journal.
§V
R1 R2 u ¨ OUT
© VFB
·
1¸
¹
§V
R2 u ¨ OUT
© 0.6V
·
1¸
¹
(3)
For devices with a fixed output voltage, the FB pin must be connected to VOUT. R1, R2, and C4 are not needed.
The fixed output voltage devices have an internal feedforward capacitor.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
11
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
9.2.2.3 Feedforward Capacitor
A feedforward capacitor (C4) is required in parallel with R1. Equation 4 calculates the capacitor value. For
the recommended 100 k value for R2, a 120 pF feedforward capacitor is used. For forced PWM devices, a
feedforward capacitor is not needed.
12 Ps
R2
C4
(4)
9.2.2.4 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify this process, Table 9-4
outlines possible inductor and capacitor value combinations for most applications. Checked cells represent
combinations that are proven for stability by simulation and lab test. Further combinations should be checked for
each individual application.
Table 9-4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](3)
NOMINAL L [µH](2)
10
2 x 10 or 1 x 22
47
0.24
+
+(1)
+
0.33
+
+
+
100
0.47
(1)
(2)
(3)
This LC combination is the standard value and recommended for most applications. Other '+' marks indicate recommended filter
combinations. Other values may be acceptable in some applications but should be fully tested by the user.
Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and –30%.
Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by 20% and –50%.
9.2.2.5 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, Equation 5 is given.
IL,MAX = IOUT,MAX +
DIL
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
(5)
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
It is recommended to choose a saturation current for the inductor that is approximately 20% to 30% higher than
IL,MAX. In addition, DC resistance and size should also be taken into account when selecting an appropriate
inductor. Table 9-5 lists recommended inductors.
Table 9-5. List of Recommended Inductors(1)
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
[L × W × H mm]
DC RESISTANCE
[mΩ]
PART NUMBER
0.24
4.9
1.6 × 0.8 × 1.0
30
Murata, DFE160810S-R24M
(DFE18SANR24MG0)
0.24
6.5
2.0 × 1.2 × 1.0
25
Murata, DFE201210U-R24M
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
Table 9-5. List of Recommended Inductors(1) (continued)
INDUCTANCE
[µH]
CURRENT RATING
[A]
DIMENSIONS
[L × W × H mm]
0.24
4.9
0.25
9.7
0.24
0.24
(1)
DC RESISTANCE
[mΩ]
PART NUMBER
1.6 × 0.8 × 0.8
22
Cyntec, HTEH16080H-R24MSR
4.0 × 4.0 × 1.2
7.64
Coilcraft, XFL4012-251ME
3.5
2.0 × 1.6 × 0.6
35
Wurth Electronics, 74479977124
3.5
2.0 × 1.6 × 0.6
35
Sunlord, MPM201606SR24M
See Third-party Products disclaimer.
9.2.2.6 Capacitor Selection
The input capacitor is the low-impedance energy source for the converters which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is recommended for best filtering and must be placed
between VIN and GND as close as possible to those pins. For most applications, 4.7 μF is sufficient, though a
larger value reduces input current ripple.
The architecture of the device allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends
using X7R or X5R dielectrics. The recommended typical output capacitor value is 2 × 10 μF or 1 × 22 µF; this
capacitance can vary over a wide range as outline in the output filter selection table.
A feedforward capacitor is required for the adjustable version, as described in Section 9.2.2.2. This capacitor is
not required for the fixed output voltage versions.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
13
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
9.2.3 Application Curves
VIN = 5.0 V, VOUT = 1.8 V, TA = 25°C, BOM = Table 9-2, unless otherwise noted.
90
0.612
85
0.609
80
0.606
Efficiency (%)
75
0.603
Vout (V)
70
65
60
0.6
0.597
55
0.594
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
50
45
40
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
0.591
1m
10m
Load (A)
100m
1
0.588
100P
3
1m
D002
10m
Load (A)
100m
1
3
D021
VOUT = 0.6 V
VOUT = 0.6 V
Figure 9-4. Load Regulation
Figure 9-3. Efficiency
100%
0.606
95%
90%
0.604
85%
Efficiency (%)
80%
0.602
Vout (V)
75%
70%
65%
60%
0.6
0.598
55%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
50%
45%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
0.596
40%
0.594
0
0.5
1
1.5
Load (A)
2
VOUT = 0.6 V
2.5
3
0
FPWM devices
0.5
1
1.5
Load (A)
VOUT = 0.6 V
Figure 9-5. Efficiency
2
2.5
3
FPWM devices
Figure 9-6. Load Regulation
90
0.909
85
0.906
80
0.903
70
Vout (V)
Efficiency (%)
75
65
60
0.9
0.897
55
50
45
40
100P
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
1m
0.894
10m
Load (A)
100m
3
1m
D003
VOUT = 0.9 V
Figure 9-7. Efficiency
14
1
0.891
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
10m
Load (A)
100m
1
3
D031
VOUT = 0.9 V
Figure 9-8. Load Regulation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
100%
0.909
95%
90%
0.906
80%
0.903
75%
Vout (V)
Efficiency (%)
85%
70%
65%
60%
0.9
0.897
55%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
50%
45%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
0.894
40%
0.891
0
0.5
1
1.5
Load (A)
2
VOUT = 0.9 V
2.5
3
0
0.5
FPWM devices
1
1.5
Load (A)
2
2.5
3
VOUT = 0.9 V
Figure 9-9. Efficiency
Figure 9-10. Load Regulation
100
1.212
95
1.209
90
1.206
1.203
80
Vout (V)
Efficiency (%)
85
75
70
1.2
1.197
65
1.194
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
60
55
50
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1.191
1m
10m
Load (A)
100m
1
1.188
100P
3
1m
D004
100m
1
3
D041
VOUT = 1.2 V
VOUT = 1.2 V
Figure 9-12. Load Regulation
Figure 9-11. Efficiency
100%
1.212
95%
1.209
90%
85%
1.206
80%
1.203
75%
Vout (V)
Efficiency (%)
10m
Load (A)
70%
65%
1.2
1.197
60%
55%
1.194
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
50%
45%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
1.191
40%
1.188
0
0.5
1
1.5
Load (A)
VOUT = 1.2 V
2
2.5
FPWM devices
Figure 9-13. Efficiency
3
0
0.5
VOUT = 1.2 V
1
1.5
Load (A)
2
2.5
3
FPWM devices
Figure 9-14. Load Regulation
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
15
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
100
1.818
95
1.812
90
Efficiency (%)
1.806
Vout (V)
85
80
75
1.8
1.794
70
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
65
60
100P
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1.788
1m
10m
Load (A)
100m
1
1.782
100P
3
1m
D005
100m
1
3
D051
VOUT = 1.8 V
VOUT = 1.8 V
Figure 9-16. Load Regulation
Figure 9-15. Efficiency
100%
1.818
95%
1.815
90%
1.812
85%
1.809
80%
1.806
75%
1.803
Vout (V)
Efficiency (%)
10m
Load (A)
70%
65%
60%
1.8
1.797
1.794
55%
1.791
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
50%
45%
VIN=2.5V
VIN=3.3V
VIN=4.2V
VIN=5.0V
1.788
1.785
40%
1.782
0
0.5
1
1.5
Load (A)
2
VOUT = 1.8 V
2.5
3
0
FPWM devices
0.5
1
1.5
Load (A)
VOUT = 1.8 V
Figure 9-17. Efficiency
2
2.5
3
FPWM devices
Figure 9-18. Load Regulation
100
3.333
3.322
95
3.3
90
Vout (V)
Efficiency (%)
3.311
85
3.289
3.278
3.267
80
3.256
75
70
100P
3.245
VIN = 4.2V
VIN = 5.0V
1m
10m
Load (A)
100m
1
3
3.234
100P
VIN = 4.2V
VIN = 5.0V
1m
D006
16
100m
1
3
D061
VOUT = 3.3 V
VOUT = 3.3 V
Figure 9-19. Efficiency
10m
Load (A)
Figure 9-20. Load Regulation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
100%
95%
90%
80%
75%
Vout (V)
Efficiency (%)
85%
70%
65%
60%
55%
50%
VIN=4.2V
VIN=5.0V
45%
40%
0
0.5
1
1.5
Load (A)
2
VOUT = 3.32 V
2.5
3.356
3.351
3.346
3.341
3.336
3.331
3.326
3.321
3.316
3.311
3.306
3.301
3.296
3.291
3.286
3
VIN=4.2V
VIN=5.0V
0
FPWM devices
0.5
2
2.5
3
FPWM devices
Figure 9-22. Load Regulation
5.0
5.0
Switching Frequency (MHz)
4.0
3.0
2.0
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
1.0
0.0
0.0
0.5
1.0
1.5
Load (A)
2.0
2.5
4.0
3.0
VOUT = 0.6V
VOUT = 0.9V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 3.3V
2.0
1.0
2.5
3.0
3.0
3.5
D008
VIN = 3.3 V
4.00x10
4.00x106
3.50x106
3.50x106
Switching Frequency (Hz)
4.50x106
6
6
3.00x10
2.50x106
6
2.00x10
1.50x106
VOUT=0.6V
VOUT=0.9V
VOUT=1.2V
VOUT=1.8V
6
1.00x10
500.00x103
0
1
1.5
Load (A)
VIN = 3.3 V
5.5
D009
2
2.5
FPWM devices
Figure 9-25. Switching Frequency
3.00x106
2.50x106
2.00x106
1.50x106
VOUT=0.6V
VOUT=0.9V
VOUT=1.2V
VOUT=1.8V
VOUT=3.3V
1.00x106
500.00x103
0.00x10
0.5
5.0
Figure 9-24. Switching Frequency
4.50x106
0
4.0
4.5
Input Voltage (V)
IOUT = 1.0 A
Figure 9-23. Switching Frequency
Switching Frequency (Hz)
1.5
Load (A)
VOUT = 3.32 V
Figure 9-21. Efficiency
Switching Frequency (MHz)
1
3
0.00x100
2.5
3
IOUT = 1.0 A
3.5
4
4.5
Input Voltage (V)
5
5.5
FPWM devices
Figure 9-26. Switching Frequency
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
17
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
ICOIL
1A/DIV
ICOIL
1A/DIV
VOUT
10mV/DIV
AC
VOUT
10mV/DIV
AC
VSW
5V/DIV
VSW
5V/DIV
Time - 200ns/DIV
7LPH
V ',9
D014
D013
IOUT = 0.1 A
IOUT = 3.0 A
Figure 9-28. PSM Operation
Figure 9-27. PWM Operation
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
ICOIL
0.5A/DIV
IOUT = 0.1 A
FPWM devices
7LPH
Figure 9-29. FPWM Operation
V ',9
D015
No load
Figure 9-30. Start-Up with No-Load
VEN
5V/DIV
VPG
5V/DIV
VOUT
1V/DIV
ICOIL
2A/DIV
No load
FPWM devices
7LPH
V ',9
Figure 9-31. Start-Up with No-Load
D016
IOUT = 3.0 A
Figure 9-32. Start-Up with Load
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
VPG
5V/DIV
VPG
5V/DIV
ILOAD
2A/DIV
ICOIL
2A/DIV
VOUT
50mV/DIV
AC
VOUT
1V/DIV
7LPH
V ',9
7LPH
D017
V ',9
D018
IOUT = 0.1 A to 3 A
IOUT = 1 A
Figure 9-33. Load Transient
Figure 9-34. HICCUP Short Circuit Protection
VPG
5V/DIV
ICOIL
2A/DIV
VOUT
1V/DIV
7LPH
V ',9
D019
IOUT = 1 A
Figure 9-35. HICCUP Short Circuit Protection (Zoom In)
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.4 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
19
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
11 Layout
11.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the device. See
Figure 11-1 and Figure 11-2 for the recommended PCB layout.
• The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps
the power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
• The low side of the input and output capacitors must be connected properly to the power GND to avoid a
GND potential shift.
• The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes. The connection of the output voltage trace for the FB
resistors should be made at the output capacitor.
• Refer to Figure 11-1 and Figure 11-2 for an example of component placement, routing and thermal design.
11.2 Layout Example
Figure 11-1. PCB Layout of Adjustable Output
Voltage Application
Figure 11-2. PCB Layout of Fixed Output Voltage
Application
11.2.1 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
For more details on how to use the thermal parameters, see the Thermal Characteristics Application Notes,
Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Report and
Semiconductor and IC Package Thermal Metrics Application Report.
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPS62088 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs
Application Report
Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
21
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
PACKAGE OUTLINE
YWC0006A
PowerWCSP - 0.3 mm max height
SCALE 15.000
POWER CHIP SCALE PACKAGE
0.82
0.78
B
A
PIN A1 INDEX
AREA
1.22
1.18
0.20
0.16
0.3 MAX
C
SEATING PLANE
0.10
0.07
3X
PKG
0.16
0.14
3X
0.378
0.358
C
SYMM
B
0.86
2X
0.43
0.187
0.167
0.015
C A B
A
1
2
4X
0.165
0.247
0.227
0.015
0.439
C A B
4223997/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
23
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
EXAMPLE BOARD LAYOUT
YWC0006A
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
PKG
PKG
3X (0.15)
3X (0.368)
1
3X (0.2)
2
A
2
A
4X (0.237)
(0.43) TYP
3X (0.368)
1
4X (0.237)
2X (0.2)
(0.43) TYP
2X (0.177)
SYMM
SYMM
B
B
(R0.05) TYP
SOLDER MASK
OPENING
TYP
C
(R0.05) TYP
SOLDER MASK
OPENING
TYP
C
METAL UNDER
SOLDER MASK
TYP
METAL EDGE
TYP
0.0375 MAX
ALL AROUND
TYP
(0.165)
0.0375 MIN
ALL AROUND
TYP
(0.165)
(0.464)
(0.439)
LAND PATTERN EXAMPLE
LAND PATTERN EXAMPLE
NON SOLDER MASK DEFINED
SCALE: 40X
SOLDER MASK DEFINED
SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
EXAMPLE STENCIL DESIGN
YWC0006A
PowerWCSP - 0.3 mm max height
POWER CHIP SCALE PACKAGE
PKG
3X (0.2)
3X (0.368)
3X (0.2)
3X (0.348)
1
A
4X (0.237)
(0.43) TYP
2
4X (0.237)
(0.43) TYP
PKG
SYMM
SYMM
2X (0.2)
2X (0.2)
B
(R0.05) TYP
(R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
C
SOLDER MASK
OPENING
TYP
EXPOSED
METAL
3X
(0.165)
(0.175)
TO PKG
(0.464)
(0.474)
SOLDER PASTE EXAMPLE
SOLDER PASTE EXAMPLE
SOLDER MASK DEFINED
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
NON SOLDER MASK DEFINED
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4223997/B 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
25
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
PACKAGE OUTLINE
YFP0006-C01
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.30
0.25
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
0.4
TYP
SYMM
C
D: Max = 1.22 mm, Min = 1.18 mm
0.8
TYP
SYMM
B
E: Max = 0.82 mm, Min = 0.78 mm
0.4 TYP
A
6X
0.015
0.25
0.21
C A B
1
2
4224455/B 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
26
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
EXAMPLE BOARD LAYOUT
YFP0006-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
6X (
0.23)
2
1
A
(0.4) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:50X
0.05 MAX
( 0.23)
METAL
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.23)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224455/B 02/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
Submit Document Feedback
27
TPS62088, TPS62088A, TPS62089A
www.ti.com
SLVSD94E – NOVEMBER 2017 – REVISED NOVEMBER 2021
EXAMPLE STENCIL DESIGN
YFP0006-C01
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
6X ( 0.25)
1
2
A
(0.4) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4224455/B 02/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
28
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TPS62088 TPS62088A TPS62089A
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS6208812YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B5
Samples
TPS6208812YFPT
ACTIVE
DSBGA
YFP
6
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B5
Samples
TPS6208818YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B6
Samples
TPS6208818YFPT
ACTIVE
DSBGA
YFP
6
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B6
Samples
TPS6208833YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B7
Samples
TPS6208833YFPT
ACTIVE
DSBGA
YFP
6
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
1B7
Samples
TPS62088AYFPJ
ACTIVE
DSBGA
YFP
6
6000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
W
Samples
TPS62088AYFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
W
Samples
TPS62088YFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
15X
Samples
TPS62088YFPT
ACTIVE
DSBGA
YFP
6
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
15X
Samples
TPS62088YWCR
ACTIVE
DSBGA
YWC
6
3000
RoHS & Green
Call TI
Level-1-260C-UNLIM
-40 to 125
1GB
Samples
TPS62089AYFPR
ACTIVE
DSBGA
YFP
6
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
X
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
