TPS62097
TPS62097
SLVSCD6A – DECEMBER 2015 – REVISED JANUARY
2021
SLVSCD6A – DECEMBER 2015 – REVISED JANUARY 2021
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TPS62097 2-A High Efficiency Step-Down Converter with iDCS-Control, Forced PWM
Mode and Selective Switching Frequency
1 Features
3 Description
•
The TPS62097 device is a synchronous step-down
converter optimized for high efficiency and noise
critical applications. The devices focus on high
efficiency conversion over a wide output current
range. At medium to heavy loads, the converter
operates in PWM mode and automatically enters
Power Save Mode operation at light load. The
switching frequency is selectable in the range of 1.5
MHz to 2.5 MHz by an external resistor. iDCS-Control
is able to be operated in forced PWM mode for low
noise operation with a fixed switching frequency.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
New product available: TPS62851x, 6-V, 0.5-A / 1A / 2-A step-down converter in SOT583 package
iDCS-control topology
Forced PWM or power save mode
Up to 97% efficiency
2.5-V to 6.0-V input voltage
0.8-V to VIN adjustable output voltage
1.8-V and 3.3-V fixed output voltage
±1% output voltage accuracy
Hiccup short circuit protection
Programmable soft start-up
Output voltage tracking
Selectable switching frequency
100% duty cycle for lowest dropout
Output discharge
Power good output
Thermal shutdown protection
-40°C to 125°C operating junction temperature
Available in 2-mm × 2-mm VQFN package
2 Applications
•
•
•
•
To address the requirements of system power rails,
the internal compensation circuit allows a large
selection of external output capacitor values in excess
of 150 µF. To control the inrush current during the
start-up, the device provides a programmable soft
start-up by an external capacitor connected to the
SS/TR pin. The SS/TR pin is also used in voltage
tracking configurations. The device integrates short
circuit protection, power good and thermal shutdown
features. The device is available in a 2-mm x 2-mm
VQFN package.
The new product, TPS62851x, offers reduced BOM
cost, smaller total solution size and other features.
Motor drives
Programmable logic controllers (PLCs)
Solid state drives (SSDs)
Point of load (POL) regulators
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
VQFN (11)
2.0 mm x 2.0 mm
TPS62097
TPS6209718
TPS6209733
(1)
TPS6209718
C1
10µF
PVIN
SW
AVIN
VOS
C3
10nF
MODE
C2
22µF
VOUT
1.8V/2A
90
VIN
EN
SS/TR
100
L1
1.0µH
FB
PG
R3
100k
POWER GOOD
AGND PGND
Efficiency (%)
VIN
2.5V to 6.0V
For all available packages, see the orderable addendum at
the end of the data sheet.
80
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
1.8-V Output, PWM/PSM Mode Application
60
1m
10m
100m
Load (A)
1
5
D003
1.8-V Output, PWM/PSM Mode Efficiency
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Options................................................................ 3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommend Operating Conditions.............................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 6
8 Detailed Description........................................................7
8.1 Overview..................................................................... 7
8.2 Functional Block Diagram........................................... 7
8.3 Feature Description.....................................................8
8.4 Device Function Modes.............................................. 8
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 1.2-V Output Application........................................... 12
10 Power Supply Recommendations..............................20
11 Layout........................................................................... 21
11.1 Layout Guidelines................................................... 21
11.2 Layout Example...................................................... 21
12 Device and Documentation Support..........................22
12.1 Device Support....................................................... 22
12.2 Support Resources................................................. 22
12.3 Receiving Notification of Documentation Updates..22
12.4 Trademarks............................................................. 22
12.5 Electrostatic Discharge Caution..............................22
12.6 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (December 2015) to Revision A (January 2021)
Page
• Added links to new device (TPS62851x)............................................................................................................ 1
• Added links to relevant applications pages on TI website.................................................................................. 1
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
2
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5 Device Options
(1)
PART NUMBER(1)
OUTPUT VOLTAGE
PACKAGE MARKING
TPS62097
Adjustable
ZFZ5
TPS6209718
1.8V
ZGB5
TPS6209733
3.3V
ZGC5
For detailed ordering information, please check the Mechanical, Packaging, and Orderable Information section at the end of this
datasheet.
6 Pin Configuration and Functions
AGND MODE SS/TR AVIN
11
PGND
1
SW
2
10
9
8
7
PVIN
SW
3
4
5
6
VOS
FB
PG
EN
Figure 6-1. 11-Pin VQFN RWK Package (Top View)
Table 6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
PGND
1
SW
2
PWR
VOS
3
I
Output voltage sense pin. This pin must be directly connected to the output capacitor.
FB
4
I
Feedback pin. For the fixed output voltage versions, this pin is recommended to be connected to AGND for
improved thermal performance. The pin also can be left floating as an internal 400-kΩ resistor is connected
between this pin and AGND for fixed output voltage versions. For the adjustable output voltage version, a resistor
divider sets the output voltage.
PG
5
O
Power-good open-drain output pin. The pullup resistor should not be connected to any voltage higher than 6 V. If
it is not used, leave the pin floating.
EN
6
I
Enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device. This
pin has an internal pulldown resistor of typically 375 kΩ when the device is disabled.
PVIN
7
PWR
Power ground pin
Switch pin. It is connected to the internal MOSFET switches. Connect the external inductor between this terminal
and the output capacitor.
Power input supply pin
AVIN
8
I
Analog input supply pin. Connect it to the PVIN pin together.
SS/TR
9
I
Soft start-up and voltage tracking pin. A capacitor is connected to this pin to set the soft start-up time. Leaving
this pin floating sets the minimum start-up time.
MODE
10
I
Mode selection pin. Connect this pin to AGND to enable Power Save Mode with automatic transition between
PWM and Power Save Mode. Connect this pin to an external resistor or leave floating to enable forced PWM
mode only. See Table 8-1.
AGND
11
Analog ground pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Voltage at Pins(2)
MIN
MAX
UNIT
–0.3
6.0
V
MODE, SS/TR, SW
–0.3
VIN+0.3V
FB
–0.3
3.0
AVIN, PVIN, EN, VOS, PG
Sink current
PG
0
1.0
mA
Temperature
Operating Junction, TJ
-40
150
°C
Storage, Tstg
–65
150
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
VESD
(1)
(2)
Human Body Model (HBM) ESD stress voltage(1)
±2000
Charged Device Model (CDM) ESD stress voltage(2)
±500
UNIT
V
JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommend Operating Conditions
Over operating free-air temperature range, unless otherwise noted.
MIN
MAX
UNIT
2.5
6.0
V
0
6.0
V
VIN
Input voltage range
VPG
Pull-up resistor voltage
VOUT
Output voltage range
0.8
VIN
V
IOUT
Output current range
0
2.0
A
TJ
Operating junction temperature
-40
125
°C
7.4 Thermal Information
THERMAL METRIC(1)
UNITS
RθJA
Junction-to-ambient thermal resistance
83.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
61.0
°C/W
RθJB
Junction-to-board thermal resistance
19.9
°C/W
ψJT
Junction-to-top characterization parameter
4.4
°C/W
ψJB
Junction-to-board characterization parameter
19.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.0
°C/W
(1)
4
TPS62097xx
RWK (11 TERMINALS)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953
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7.5 Electrical Characteristics
TJ = -40°C to 125°C, and VIN = 2.5V to 6.0V. Typical values are at TJ = 25°C and VIN = 3.6V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
EN = High, Device not switching, TJ = –40°C to 85°C
40
57
EN = High, Device not switching
40
65
EN = Low, TJ = –40°C to 85°C
0.7
3
EN = Low
0.7
10
UNIT
SUPPLY
IQ
Quiescent current into AVIN, PVIN
ISD
Shutdown current into AVIN, PVIN
VUVLO
TJSD
Under voltage lock out threshold
VIN falling
2.2
2.3
2.4
VIN rising
2.3
2.4
2.5
µA
µA
V
Thermal shutdown threshold
TJ rising
160
°C
Thermal shutdown hysteresis
TJ falling
20
°C
1.6
V
LOGIC INTERFACE (EN, MODE)
VH_EN
High-level input voltage, EN pin
VL_EN
Low-level input voltage, EN pin
IEN,LKG
Input leakage current into EN pin
EN = High
RPD
Pull-down resistance at EN pin
EN = Low
VH_MO
High-level input voltage, MODE pin
VL_MO
Low-level input voltage, MODE pin
IMO,LKG
Input leakage current into MODE pin
2.0
1.3
1.0
V
0.01
0.9
µA
375
kΩ
1.2
V
0.4
V
0.01
0.16
µA
5.5
7.5
9.5
µA
VOUT rising, referenced to VOUT nominal
92
95
98
VOUT falling, referenced to VOUT nominal
87
90
92
MODE = High
SOFT STARTUP, POWER GOOD (SS/TR, PG)
ISS
Soft startup current
Voltage tracking gain factor
VFB / VSS/TR
1
VPG
Power good threshold
VPG,OL
Low-level output voltage, PG pin
Isink = 1mA
IPG,LKG
Input leakage current into PG pin
VPG = 5.0V
VOUT
Output voltage accuracy
TPS6209718, TPS6209733
PWM mode, No load
–1.0
1.0
PSM mode(1)
–1.0
2.1
VFB
Feedback reference voltage
PWM mode
792
800
808
PSM mode(1)
792
800
817
IFB,LKG
Input leakage current into FB pin
VFB = 0.8V
0.01
0.1
RDIS
Output discharge resistor
EN = Low, VOUT = 1.8V
165
Ω
0.01
%
0.4
V
1.6
µA
OUTPUT
1.8V(1)
%
mV
µA
Line regulation
IOUT = 0.5A, VOUT =
0.02
%/V
Load regulation
PWM mode, VOUT = 1.8V (1)
0.2
%/A
ISW = 500mA, VIN = 5.0V
40
73
ISW = 500mA, VIN = 3.6V
50
96
ISW = 500mA, VIN = 5.0V
40
68
ISW = 500mA, VIN = 3.6V
50
85
3.1
3.6
4.2
3.3
3.6
3.9
–1.25
–1.1
-0.7
POWER SWITCH
High-side FET on-resistance
RDS(on)
Low-side FET on-resistance
ILIMF
High-side FET forward current limit
ILIMN
Low-side FET negative current limit
(1)
VIN = 5.0V
Forced PWM mode
mΩ
mΩ
A
A
Conditions: L = 1 μH, COUT = 22 μF, Switching Frequency = 2.0 MHz
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7.6 Typical Characteristics
120
120
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
100
)(7 2Q 5HVLVWDQFH P
)(7 2Q 5HVLVWDQFH P
100
80
60
40
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
6.0
60
40
0
2.5
D014
Figure 7-1. High-Side FET On-Resistance
6
80
20
20
0
2.5
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
6.0
D015
Figure 7-2. Low-Side FET On-Resistance
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8 Detailed Description
8.1 Overview
The TPS62097 synchronous step-down converter is based on the iDCS-Control (Industrial Direct Control with
Seamless transition into Power Save Mode) topology. The control topology not only keeps the advantages of
DCS-Control, but also provides other features:
•
•
•
•
Forced PWM mode over the whole load range
Selectable PWM switching frequency
1% output voltage accuracy
Output voltage sequencing and tracking
The iDCS-Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode (PSM) at light load conditions. Or it forces the device in fixed frequency
PWM mode only operation for the whole load range.
In PWM mode, the device operates with a predictive on-time switching pulse. A quasi-fixed switching frequency
over the input and output voltage range is achieved by using an input and output voltage feedforward to set the
on-time, as shown in Table 8-1. The converter enters Power Save Mode, reducing the switching frequency and
minimizing current consumption, to achieve high efficiency over the entire load current range. Since iDCSControl supports both operation modes within a single building block, the transition from PWM mode to Power
Save Mode is seamless and without effects on the output voltage.
8.2 Functional Block Diagram
AVIN
Hiccup
Counter
PG
PVIN
VFB
High-side
Current Sense
VREF
EN
375kΩ
(2)
AGND
Low-side
Current Sense
Bandgap
Undervoltage Lockout
Thermal Shutdown
VIN
SS/TR
Voltage
Clamp
VREF
PGND
Ramp
VIN
MODE
SW
MOSFET Driver
Control Logic
On time
Selection
Comparator
Direct Control
and
Compensation
tON
Timer
VOS
R1
(1)
R2
(1)
FB
Error Amplifier
VREF
iDCS - Control
EN
165Ω
Output Discharge
Logic
Note:
(1) R1, R2 are implemented in the fixed output voltage versions only.
(2) When the device is enabled, the 375 kΩ resistor is disconnected.
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8.3 Feature Description
8.3.1 100% Duty Cycle Mode
The device offers a low input to output voltage dropout by entering 100% duty cycle mode when the input
voltage reaches the level of the output voltage. In this mode, the high-side MOSFET switch is constantly turned
on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation,
depending on the load current and output voltage, is calculated as:
VIN(min) = VOUT(min) + IOUT x (RDS(on) + RL)
(1)
where
•
•
•
•
VIN(min) = Minimum input voltage to maintain a minimum output voltage
IOUT = Output current
RDS(on) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
When the device operates close to 100% duty cycle mode, the TPS62097 cannot enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
8.3.2 Switch Current Limit and Hiccup Short Circuit Protection
The switch current limit prevents the devices from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted/saturated inductor or a heavy load/
shorted output circuit condition. If the inductor current reaches the threshold ILIMF, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current. Once this switch current
limit is triggered 32 times, the devices stop switching and enable the output discharge. The devices then
automatically start a new start-up after a typical delay time of 100 µs has passed. This is HICCUP short circuit
protection and is implemented to reduce the current drawn during a short circuit condition. The devices repeat
this mode until the high load condition disappears.
When the device is in forced PWM mode, the negative current limit of the low-side MOSFET is active. The
negative current limit prevents excessive current from flowing back through the inductor to the input.
8.3.3 Undervoltage Lockout (UVLO)
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is implemented, which shuts
down the devices at voltages lower than VUVLO with a hysteresis of 100 mV.
8.3.4 Thermal Shutdown
The device goes into thermal shutdown and stops switching once the junction temperature exceeds TJSD. Once
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
8.4 Device Function Modes
8.4.1 Enable and Disable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
resistor of 165 Ω discharges the output through the VOS pin smoothly. The output discharge function also works
when thermal shutdown, undervoltage lockout, or HICCUP short circuit protection are triggered.
An internal pulldown resistor of 375 kΩ is connected to the EN pin when the EN pin is low. The pulldown resistor
is disconnected when the EN pin is high.
8.4.2 Power Save Mode and Forced PWM Mode (MODE)
The MODE pin is a multi-functional pin that allows the device operation in forced PWM mode or PWM/PSM
mode, and to select the PWM switching frequency.
8
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Once the EN pin is pulled high, the IC enables internal circuit blocks and prepares to ramp the output up. The
period between the rising edge of the EN pin and the beginning of the power stage switching is called the MODE
detection time, typically 50 µs. During the MODE detection time period, shown in Figure 8-1, the PWM switching
frequency and operating mode are set by the MODE pin status, as shown in Table 8-1.
The PWM switching frequency cannot be changed after the detection time period. Only when the device is set in
PWM/PSM mode during the MODE detection time period (MODE = AGND), it is possible to switch between
PWM/PSM and forced PWM operation modes by toggling the MODE pin with a GPIO pin of a microcontroller, for
example. The other four MODE pin selections force the device in PWM mode only.
EN
Disable
Enable
VOUT
Soft Startup
PG
MODE
Detection
Figure 8-1. Power-up Sequence
Table 8-1. Switching Frequency and Mode Selection
TYPICAL PWM
SWITCHING
FREQUENCY
(MHZ)
RESISTANCE AT MODE
PIN
(E24 EIA VALUE)
TOGGLE MODE PIN
AFTER MODE DETECTION
ON-TIME EQUATION
OPERATING
MODE
1.50
8.2 kΩ ±5%
No
tON = 667 ns x VOUT / VIN
Forced PWM
1.75
18 kΩ ±5%
No
tON = 571 ns x VOUT / VIN
Forced PWM
2.00
AGND
Yes
tON = 500 ns x VOUT / VIN
PWM/PSM and
Forced PWM
2.25
39 kΩ ±5%
No
tON = 444 ns x VOUT / VIN
Forced PWM
2.50
75 kΩ ±5% or Open
No
tON = 400 ns x VOUT / VIN
Forced PWM
Connecting the MODE pin to AGND with a resistor or leaving the MODE pin open forces the device into PWM
mode for the whole load range. The device operates with a fixed switching frequency that allows simple filtering
of the switching frequency for noise sensitive applications. In forced PWM mode, the efficiency is lower than that
of PSM at light load.
Connecting the MODE pin to the AGND pin enables Power Save Mode with an automatic transition between
PWM and Power Save Mode. As the load current decreases and the inductor current becomes discontinuous,
the device enters Power Save Mode operation automatically. In Power Save Mode, the switching frequency is
reduced and estimated by Equation 2. In Power Save Mode, the output voltage rises slightly above the nominal
output voltage, as shown in Figure 9-8. This effect is minimized by increasing the output capacitor.
fPSM =
t ON
2
2 ´ IOUT
V - VOUT
VIN
´
´ IN
VOUT
L
(2)
When the device operates close to 100% duty cycle mode, the TPS62097 cannot enter Power Save Mode
regardless of the load current if the input voltage decreases to typically 15% above the output voltage. The
device maintains output regulation in PWM mode.
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8.4.3 Soft Start-up (SS/TR)
The TPS62097 programs its output voltage ramp rate with the SS/TR pin. Connecting an external capacitor to
SS/TR enables output soft start-up to reduce inrush current from the input supply. The device charges the
capacitor voltage to the input supply voltage with a constant current of typically 7.5 μA. The FB pin voltage
follows the SS/TR pin voltage until the internal reference voltage of 0.8 V is reached. The soft start-up time is
calculated using Equation 3. Keep the SS/TR pin floating to set the minimum start-up time.
t SS = CSS / TR ´
0 .8 V
7.5mA
(3)
An active pulldown circuit is connected to the SS/TR pin. It discharges the external soft start-up capacitor in case
of disable, UVLO, thermal shutdown, and HICCUP short circuit protection.
8.4.4 Voltage Tracking (SS/TR)
The SS/TR pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 8-2. From 0 V to 0.8 V, the internal reference voltage to the internal error amplifier
follows the SS/TR pin voltage. When the SS/TR pin voltage is above 0.8 V, the voltage tracking is disabled and
the FB pin voltage is regulated at 0.8 V. The device achieves ratiometric or coincidental (simultaneous) output
tracking, as shown in Figure 8-3.
VOUT1
VOUT2
TPS62097
R3
R1
SS/TR
FB
R2
R4
Figure 8-2. Output Voltage Tracking
Voltage
Voltage
VOUT1
VOUT1
VOUT2
VOUT2
R3 R1
<
R 4 R2
R3 R1
=
R 4 R2
t
a) Ratiometric Tracking
t
b) Coincidental Tracking
Figure 8-3. Voltage Tracking Options
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 µA soft start-up current
into account. 1 kΩ or smaller is a sufficient value for R2.
For decreasing SS/TR pin voltage, the device does not sink current from the output when the device is in PSM,
so the resulting decreases of the output voltage can be slower than the SS/TR pin voltage if the load is light.
When driving the SS/TR pin with an external voltage, do not exceed the voltage rating of the SS/TR pin which is
VIN + 0.3 V.
10
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8.4.5 Power Good (PG)
The TPS62097 has a power-good output. The PG pin goes high impedance once the output voltage is above
95% of the nominal voltage and is driven low once the output voltage falls below typically 90% of the nominal
voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power-good output requires
a pullup resistor connected to any voltage rail less than 6 V. The PG pin goes low when the device is disabled or
in thermal shutdown. When the devices are in UVLO, the PG pin is high impedance.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin floating when not used.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design of
the TPS62097.
9.2 1.2-V Output Application
TPS62097
VIN
2.5V to 6.0V
C1
10µF
PVIN
SW
AVIN
VOS
L1
1.0µH
C2
22µF
EN
C3
10nF
SS/TR
FB
MODE
PG
VOUT
1.2V/2A
R1
10k
VIN
R2
20k
R3
100k
AGND PGND
POWER GOOD
Figure 9-1. 1.2-V Output Application Schematic
9.2.1 Design Requirements
For this design example, use the following as the input parameters.
Table 9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 6 V
Output voltage
1.2 V
Output current
2.0 A
Output voltage ripple
< 30 mV
Table 9-2 lists the components used for the example.
Table 9-2. List of Components
REFERENCE
12
DESCRIPTION
MANUFACTURER
C1
10 μF, Ceramic Capacitor, 6.3 V, X7R, size 0805, C2012X7R0J106M125AB
TDK
C2
22 μF, Ceramic Capacitor, 6.3 V, X7S, size 0805, C2012X7S1A226M125AC
C3
10 nF, Ceramic Capacitor, 6.3 V, X7R, size 0603, GRM188R70J103KA01
Murata
Coilcraft
TDK
L1
1 µH, Shielded, 5.4 A, XFL4020-102MEB
R1
Depending on the output voltage, 1% accuracy
Std
R2
20 kΩ, 1% accuracy
Std
R3
100 Ωk, 1% accuracy
Std
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9.2.2 Detailed Design Procedure
9.2.2.1 Setting the Output Voltage
The output voltage is set by an external resistor divider according to Equation 4:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
÷ = 0.8 V ´ ç 1 + R2 ÷
R2
è
ø
è
ø
(4)
R2 should not be higher than 20 kΩ to reduce noise coupling into the FB pin and improve the output voltage
regulation. Figure 9-1 shows the external resistor divider value for 1.2-V output. Choose additional resistor
values for other outputs. A feedforward capacitor is not required.
The fixed output voltage versions, TPS6209718 and TPS6209733, do not need the external resistor divider. TI
recommends to connect the FB pin to AGND for improved thermal performance.
9.2.2.2 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, Table
9-3 outlines possible inductor and capacitor value combinations for most applications.
Table 9-3. Output Capacitor / Inductor Combinations
NOMINAL L [µH](2)
NOMINAL COUT [µF](3)
10
22
47
100
150
+(1)
+
+
+
0.47
1
2.2
(1)
(2)
(3)
Typical application configuration. Other '+' mark indicates recommended filter combinations. Other
values may be acceptable in applications but should be fully tested by the user. Refer to the
application note SLVA710.
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20%
and -30%. The required effective inductance is 500-nH minimum.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary
by 20% and -50%.
9.2.2.3 Inductor Selection
The main parameters for the inductor selection are the inductor value and the saturation current. To calculate the
maximum inductor current under static load conditions, Equation 5 is given.
IL,MAX = IOUT,MAX +
DIL
2
VOUT
VIN
DIL = VOUT ´
L ´ fSW
1-
(5)
Where:
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
TI recommends to choose the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of
Equation 5. A higher inductor value is also useful to lower ripple current but increases the transient response
time as well. The following inductors are recommended to be used in designs.
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Table 9-4. List of Recommended Inductors
INDUCTANCE
[µH]
(1)
CURRENT RATING
[A]
DIMENSIONS
L x W x H [mm3]
DC RESISTANCE
[mΩ TYP]
PART NUMBER(1)
1
5.4
4.0x4.0x2.0
11
COILCRAFT XFL4020-102ME
1
5.3
2.5x2.0x1.2
33
TOKO DFE252012F-1R0M
1
3.4
2.0x1.2x1.0
62
TOKO DFE201210S-1R0M
1
5.1
3.0x3.0x1.2
43
TAIYO YUDEN MDMK3030T1R0MM
1
4.2
2.5x2.0x1.2
43
CYNTEC SDEM25201B-1R0MS-79
1
2.6
2.5x2.0x1.2
48
Murata LQH2HPN1R0NJR
1
6.6
3.0x3.0x1.2
42
Wurth Electronics 74438334010
See Third-Party Products Disclaimer
9.2.2.4 Capacitor Selection
The input capacitor is the low impedance energy source for the converters which helps to provide stable
operation. A low-ESR multilayer ceramic capacitor is required for best filtering and should be placed between
PVIN and PGND as close as possible to those pins. For most applications, a 10-μF capacitor is sufficient, though
a larger value reduces input current ripple.
The architecture of the TPS62097 allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, TI recommends to
use X7R or X5R dielectrics. The recommended typical output capacitor value is 22 μF and can vary over a wide
range as outlined in Table 9-4.
Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance.
Choose the right capacitor carefully in combination with considering its package size and voltage rating. Ensure
that the input effective capacitance is at least 5 μF and the output effective capacitance is at least 10 μF.
14
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9.2.3 Application Performance Curves
100
100
90
90
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 3.6 V, unless otherwise noted.
80
70
60
1m
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
10m
100m
Load (A)
1
80
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0
5
0.5
D001
100
100
90
90
80
70
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 2.7 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
10m
100m
Load (A)
1
0
5
0.5
D003
1
Load (A)
1.5
2
D004
VOUT = 1.8 V
Figure 9-4. Efficiency, PWM/PSM Mode (2.0 MHz)
Figure 9-5. Efficiency, Forced PWM Mode (2.0 MHz)
100
100
90
90
Efficiency (%)
Efficiency (%)
D002
80
VOUT = 1.8 V
80
70
80
70
VIN = 4.2 V
VIN = 5.0 V
60
1m
2
Figure 9-3. Efficiency, Forced PWM Mode (2.0 MHz)
Efficiency (%)
Efficiency (%)
Figure 9-2. Efficiency, PWM/PSM Mode (2.0 MHz)
60
1m
1.5
VOUT = 1.2 V
VOUT = 1.2 V
70
1
Load (A)
VIN = 4.2 V
VIN = 5.0 V
60
10m
100m
Load (A)
1
5
0
D005
VOUT = 3.3 V
0.5
1
Load (A)
1.5
2
D006
VOUT = 3.3 V
Figure 9-6. Efficiency, PWM/PSM Mode (2.0 MHz)
Figure 9-7. Efficiency, Forced PWM Mode (2.0 MHz)
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1.0
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
1.0
0.5
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
1m
10m
100m
Load (A)
1
0.5
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
1m
5
10m
D007
VOUT = 1.2 V
D008
5x106
Switching Frequency (Hz)
Output Voltage Accuracy (%)
5
Figure 9-9. Load Regulation, Forced PWM Mode
(2.0 MHz)
1.0
0.5
0.0
-0.5
TA = -40°C
TA = 25°C
TA = 85°C
-1.0
2.5
3.0
3.5
106
105
104
10
4.0
4.5
Input Voltage (V)
5.0
5.5
1m
6.0
VOUT = 1.2 V
IOUT = 500 mA
2.5
2.5
Switching Frequency (MHz)
3.0
2.0
1.5
1.0
IOUT = 1 A
IOUT = 2 A
VOUT = 1.2 V
3.5
4.0
4.5
Input Voltage (V)
100m
Load (A)
1
5
D010
5.0
5.5
6.0
2.0
1.5
1.0
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
0.5
2.5
3.0
D011
MODE = High after PWM/PSM Selection
Figure 9-12. Switching Frequency, Forced PWM
Mode (2.0 MHz)
MODE = AGND
Figure 9-11. Switching Frequency, PWM/PSM Mode
(2.0 MHz)
3.0
3.0
10m
D009
Figure 9-10. Line Regulation, Forced PWM Mode
(2.0 MHz)
0.5
2.5
VIN = 3.3 V
VIN = 5.0 V
3
VOUT = 1.2 V
Switching Frequency (MHz)
1
VOUT = 1.2 V
Figure 9-8. Load Regulation, PWM/PSM Mode (2.0
MHz)
16
100m
Load (A)
VOUT = 1.2 V
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
6.0
D012
RMode = 8.2 kΩ
Figure 9-13. Switching Frequency, Forced PWM
Mode (1.5 MHz)
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Switching Frequency (MHz)
3.0
VSW
2V/DIV
2.5
2.0
VOUT
10mV/DIV
AC
1.5
1.0
ICOIL
200mA/DIV
2A OFFSET
IOUT = 0 A
IOUT = 1 A
IOUT = 2 A
0.5
2.5
3.0
3.5
Time - 200ns/DIV
4.0
4.5
Input Voltage (V)
VOUT = 1.2 V
5.0
5.5
D016
6.0
D013
VOUT = 1.2 V
IOUT = 2 A
MODE = Open
Figure 9-14. Switching Frequency, Forced PWM
Mode (2.5 MHz)
Figure 9-15. Output Ripple, PWM Operation (2.0
MHz)
IOUT
2A/DIV
VSW
2V/DIV
VOUT
100mV/DIV
AC
VOUT
20mV/DIV
AC
ICOIL
2A/DIV
ICOIL
300mA/DIV
7LPH
V ',9
7LPH
V ',9
D017
VOUT = 1.2 V
IOUT = 30 mA
D018
VOUT = 1.2 V
Figure 9-16. Output Ripple, Power Save Operation
Figure 9-17. Load Transient, PWM/PSM Mode (2.0
MHz)
IOUT
2A/DIV
VEN
2V/DIV
VOUT
100mV/DIV
AC
VOUT
500mV/DIV
ICOIL
2A/DIV
ICOIL
300mA/DIV
7LPH
IOUT = 0 A to 2 A, 1 A / µs
7LPH
V ',9
V ',9
D020
D019
VOUT = 1.2 V
IOUT = 0 A to 2 A, 1 A / µs
Figure 9-18. Load Transient, Forced PWM Mode
(2.0 MHz)
VOUT = 1.2 V
ROUT = No Load
Figure 9-19. Startup and Shutdown without Load
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Short
Recovery
VEN
2V/DIV
VOUT
500mV/DIV
VOUT
500mV/DIV
ICOIL
2A/DIV
ICOIL
1A/DIV
7LPH
7LPH
V ',9
V ',9
D022
D021
VOUT = 1.2 V
VOUT = 1.2 V
ROUT = 0.6 Ω (2 A)
ROUT = 0.8 Ω (1.5 A) with 1-ms short
Figure 9-21. Short Circuit Protection, HICCUP
Figure 9-20. Startup and Shutdown with Load
9.2.4 Coincidental Voltage Tracking
TPS6209718
VIN
2.5V to 6.0V
C1
10µF
PVIN
SW
AVIN
VOS
L1
1.0µH
VOUT1
1.8V
C2
22µF
EN
VEN
C3
10nF
SS/TR
FB
MODE
PG
AGND PGND
TPS62097
C4
10µF
R1
0.5k
PVIN
SW
AVIN
VOS
L1
1.0µH
VOUT2
1.2V
C5
22µF
EN
R2
1k
SS/TR
FB
MODE
PG
R3
10k
R4
20k
AGND PGND
Figure 9-22. 1.8-V and 1.2-V Coincidental Voltage Tracking Schematic
9.2.4.1 Design Requirements
For this design example, use the following as the input parameters.
Table 9-5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 6 V
Output voltage 1
1.8 V
Output voltage 2
1.2 V
Output voltage 2 follows output voltage 1 coincidentally.
18
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9.2.4.2 Detailed Design Procedure
Set 1 kΩ for R2 and 0.5 kΩ for R1. Connect the two converters as shown in Figure 9-22. Set up two converters
in forced PWM mode.
9.2.4.3 Application Performance Curve
TA = 25°C, VIN = 5.0 V, unless otherwise noted.
VEN
2V/DIV
VOUT1
500mV/DIV
VOUT2
500mV/DIV
Time - 1ms/DIV
D023
VOUT1 = 1.8 V
VOUT2 = 1.2 V
Figure 9-23. Coincidental Tracking Waveform
9.2.5 Switching Frequency Selection
TPS6209718
VIN
2.5V to 6.0V
C1
10µF
PVIN
SW
AVIN
VOS
C3
10nF
MODE
R4
C2
22µF
VOUT
1.8V/2A
VIN
EN
SS/TR
L1
1.0µH
FB
R3
100k
PG
POWER GOOD
AGND PGND
Figure 9-24. Switching Frequency Selection by an External Resistor
9.2.5.1 Design Requirements
For this design example, use the following as the input parameters.
Table 9-6. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 6 V
Output voltage 1
1.8 V
Switching Frequency Selection
1.5 MHz, 2.0 MHz, or 2.5 MHz
9.2.5.2 Detailed Design Procedure
Set 8.2 kΩ and 75 kΩ for 1.5-MHz, 2.0-MHz, and 2.5-MHz switching frequency. R4 uses the standard E24 series
resistor values.
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9.2.5.3 Application Performance Curves
TA = 25°C, VIN = 5.0, unless otherwise noted.
100
80
60
Efficiency (%)
6SXULRXV 2XWSXW 1RLVH G% 9
70
50
40
30
90
20
1.5MHz (FPWM)
2.0MHz (FPWM)
2.5MHz (FPWM)
1.5MHz (FPWM)
2.0MHz (FPWM)
2.5MHz (FPWM)
10
0
0
1
2
3
4
5
6
Frequency (Hz)
VOUT = 1.8 V
7
8
9
10
80
2.5
3
3.5
4
4.5
Input Voltage (V)
5
D024
IOUT = 1 A
Figure 9-25. Spurious Output Noise with Different
Switching Frequency
VOUT = 1.8 V
5.5
6
D025
IOUT = 1 A
Figure 9-26. Efficiency with Different Switching
Frequency
10 Power Supply Recommendations
The devices are designed to operate from an input voltage supply range between 2.5 V and 6 V. The average
input current of the TPS62097 is calculated as:
IIN =
1 VOUT ´ IOUT
´
h
VIN
(6)
Ensure that a power supply has a sufficient current rating for the application.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
TI recommends to place all components as close as possible to the IC. Specifically, the input capacitor
placement must be closest to the PVIN and PGND pins of the device.
The low side of the input and output capacitors must be connected directly to the PGND pin to avoid a ground
potential shift.
Use the terminal of the input capacitor as the common node for AVIN and PVIN, AGND, and PGND. It helps
reduce the noise coupling into the internal analog circuit blocks. Do not use a solid plane pour to connect
these nodes.
Use wide and short traces for the main current paths to reduce the parasitic inductance and resistance.
The sense trace connected to VOS pin is a signal trace. Special care should be taken to avoid noise being
induced. By a direct routing, parasitic inductance can be kept small. Keep the trace away from SW nodes.
Refer to the Figure 11-1 for an example of component placement, routing, and thermal design.
11.2 Layout Example
VIN
C1
Single Point
Ground
EN
PG
SS/TR
R4 C3
SW
AVIN
PVIN
L1
FB
AGND
VOS
PGND
MODE
C2
R1
R2
VOUT
GND
Figure 11-1. TPS62097 PCB Layout
11.2.1 Thermal Information
Implementation of integrated circuits in low-profile and fine pitch surface mount packages typically requires
special attention to power dissipation. Many system dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Section 7.4 provides the thermal metric of the device on the TPS62097 EVM after considering the PCB design of
real applications. The big copper planes connecting to the pads of the IC on the PCB board improve the thermal
performance of the device. For more details on how to use the thermal parameters, see the application notes:
Thermal Characteristics Application Notes SZZA017 and SPRA953.
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS6209718RWKR
ACTIVE
VQFN-HR
RWK
11
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZGB5
TPS6209718RWKT
ACTIVE
VQFN-HR
RWK
11
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZGB5
TPS6209733RWKR
ACTIVE
VQFN-HR
RWK
11
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZGC5
TPS6209733RWKT
ACTIVE
VQFN-HR
RWK
11
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZGC5
TPS62097RWKR
ACTIVE
VQFN-HR
RWK
11
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZFZ5
TPS62097RWKT
ACTIVE
VQFN-HR
RWK
11
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZFZ5
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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