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TPS62120, TPS62122
SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
TPS6212x 15-V, 75-mA Highly Efficient Buck Converter
1 Features
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
Wide Input Voltage Range: 2 V to 15 V
Up to 96% Efficiency
Power Save Mode With 11-µA Quiescent Current
Output Current 75 mA
Output Voltage Range: 1.2 V to 5.5 V
Up to 800-kHz Switch Frequency
Synchronous Converter, No External Rectifier
Low Output Ripple Voltage
100% Duty Cycle for Lowest Dropout
Small SOT 8-Pin (TPS62120) and 2-mm × 2-mm
DFN 6-Pin (TPS62122) Package
Internal Soft Start
Power Good Open Drain Output (TPS62120)
Open-Drain Output for Output Discharge
(TPS62120)
2.5-V Rising and 1.85-V Falling UVLO Thresholds
The wide operating input voltage range of 2 V to 15 V
supports energy harvesting, battery powered and as
well 9-V or 12-V line powered applications.
With its advanced hysteretic control scheme, the
converter provides power save mode operation. At
light loads the converter operates in pulse frequency
modulation (PFM) mode and transitions automatically
in pulse width modulation (PWM) mode at higher load
currents. The power save mode maintains high
efficiency over the entire load current range. The
hysteretic control scheme is optimized for low output
ripple voltage in PFM mode in order to reduce output
noise to a minimum. The device consumes only 10µA quiescent current from VIN in PFM mode
operation.
In shutdown mode, the device is turned off.
An open-drain power good output is available in the
TPS62120 and indicates once the output voltage is in
regulation.
2 Applications
The TPS62120 has an additional SGND pin which is
connected to GND during shutdown mode. This
output can be used to discharge the output capacitor.
•
•
•
•
The TPS6212x operates over an free air temperature
range of –40°C to 85°C. The TPS62120 is available
in a small 8-pin SOT-23 package and the TPS62122
in a 2 mm × 2 mm 6-pin DFN package.
Low Power RF Applications
Ultra Low Power Microprocessors
Energy Harvesting
Industrial Measuring
Device Information(1)
3 Description
The TPS6212x device is a highly efficient
synchronous step-down DC-DC converter optimized
for low-power applications. The device supports up to
75-mA output current and allows the use of tiny
external inductors and capacitors.
PART NUMBER
TPS62120
2.90 mm × 1.63 mm
TPS62122
SON (6)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Efficiency vs Output Current
VOUT = 1.8 V
up to 75 mA
L 22 mH
VIN = 8 V
R1
EN
VIN = 5.5 V
90
SW
300 kW
CIN
100
FB
4.7 mF
Cff
22 pF
R2
240 kW
GND
VOUT
SGND
PG
COUT
4.7 mF
80
Efficiency - %
VIN
BODY SIZE (NOM)
SOT-23 (8)
Typical Application Schematic
VIN = 2.5 V to 15 V
PACKAGE
TPS62120
VIN = 10 V
VIN = 15 V
VIN = 12 V
70
60
50
VO = 5 V,
R pullup 100kW
PWR GOOD
L = 18 mH,
LPS3015,
CO = 4.7 mF
40
30
0.1
1
10
IO - Output Current - mA
100
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62120, TPS62122
SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Applications ................................................ 12
9.3 System Examples ................................................... 20
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Examples................................................... 22
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2010) to Revision A
•
2
Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
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SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
5 Device Comparison Table
(1)
(2)
PART NUMBER
ACTIVE DISCHARGE SWITCH
POWER GOOD
VOUT
TPS62120 (1)
yes
Open-Drain
adjustable
TPS62122 (2)
no
no
adjustable
The DCN package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.
The DRV package is available in tape on reel. Add R suffix to order quantities of 3000 parts per reel, T suffix for 250 parts per reel.
6 Pin Configuration and Functions
SW
1
VOUT
2
FB
3
TH E
ER XP
M OS
A ED
L
PA
D
DRV Package
6-Pin SON
Top View
6
GND
5
VIN
4
EN
DCN Package
8-Pin SOT-23
Top View
VIN
1
8
VOUT
GND
2
7
SW
EN
3
6
PG
SGND
4
5
FB
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DFN
SOT-23
EN
4
3
I
Pulling this pin to high activates the device. Low level shuts it down. This pin must be terminated.
FB
3
5
I
This is the feedback pin for the regulator. Connect external resistor-divider to this pin.
GND
6
2
PWR
PG
—
6
O
This pin is available in TPS62120 only.
Open-drain power good output. Connect this terminal through a pullup resistor to a voltage rail up
to 5.5 V or leave it open. This pin can sink 500 µA.
GND supply pin.
SGND
—
4
I
This pin is available in TPS62120 only.
Open-drain output which is turned on during shutdown mode (EN = 0) or VIN is below the UVLO
threshold. The output connects the SGND pin to GND through an internal MOSFET with typical
370-Ω RDS(ON). When the device is enabled (EN = 1), this output is high impedance. To discharge
the output capacitor during shutdown mode, connect this pin to VOUT (output capacitor) or leave it
open.
SW
1
7
O
This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor to
this terminal. Do not tie this pin to VIN, VOUT or GND.
VIN
5
1
PWR
2
8
I
Exposed
Thermal
Pad
—
—
VOUT
—
VIN power supply pin.
This pin must be connected to the output capacitor.
Exposed thermal pad available only in DRV package option. This pad must be connected to GND.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Voltage at VIN (2)
Voltage at SW
PIN
MIN
MAX
UNIT
–0.3
17
V
dynamically during switching t < 10 µs
17
V
–0.3
6
–0.3
VIN +0.3,
but ≤17
V
Voltage on FB Pin
–0.3
3.6
V
Voltage at PG, VOUT, SGND (2)
–0.3
6
V
0.5
mA
Maximum operating junction temperature, TJ
–40
125
°C
Storage temperature, Tstg
–65
150
°C
VI
Voltage at EN PIN (2)
IIN
(1)
(2)
static DC
Current into PG pin
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal GND.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Supply voltage VIN, device in operation
Output current capability
NOM
2
VIN = 2 V, VOUT = 1.8 V, DCRL = 0.7 Ω
25
VIN ≥ 2.5 V, VOUT = 1.8 V, DCRL = 0.7 Ω
75
MAX
15
UNIT
V
mA
Effective inductance
10
22
Effective output capacitance
1.0
2
Output voltage
1.2
5.5
V
–40
85
°C
–40
125
°C
Operating ambient temperature TA
(1)
, (unless otherwise noted)
Operating junction temperature, TJ
(1)
4
33
µH
33
µF
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (RθJA), as given by the following equation: TA(max) = TJ(max) – (RθJA × PD(max)).
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SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
7.4 Thermal Information
THERMAL METRIC (1)
TPS62120
TPS62122
DCN [SOT-23]
DRV [DFN]
8 PINS
6 PINS
114.4
°C/W
UNIT
RθJA
Junction-to-ambient thermal resistance
259.7
RθJC(top)
Junction-to-case(top) thermal resistance
114.1
73.7
°C/W
RθJB
Junction-to-board thermal resistance
185.8
201.9
°C/W
ψJT
Junction-to-top characterization parameter
21.6
0.8
°C/W
ψJB
Junction-to-board characterization parameter
121.6
94.9
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
n/a
122.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC PackageThermal Metrics application
report, SPRA953
7.5 Electrical Characteristics
VIN = 8 V, VOUT = 1.8 V, EN = VIN, TJ = –40°C to 85°C, typical values are at TJ = 25°C (unless otherwise noted), CIN = 4.7 µF,
L = 22 µH, COUT = 4.7 µF
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
2
15
UNIT
SUPPLY
Input voltage range (1)
VIN
IQ
Device operating
Quiescent current
IOUT = 0 mA, device not switching, EN = VIN,
regulator sleeps
11
IOUT = 0 mA, device switching, VIN = 8 V, VOUT = 1.8
V
13
IActive
Active mode current consumption
VIN = 5.5 V = VOUT, TJ = 25°C, high-side MOSFET
switch fully turned on
ISD
Shutdown current
EN = GND, VOUT = SW = 0 V, VIN = 3.6 V
VUVLO
Undervoltage lockout threshold
V
18
µA
240
275
µA
0.3
1.2
µA
Falling VIN
1.85
1.95
Rising VIN
2.5
2.61
0.8
1.1
V
0
50
nA
(2)
V
ENABLE, THRESHOLD
VIH TH
Threshold for detecting high EN
2 V ≤ VIN ≤ 15 V, rising edge
VIL TH HYS
Threshold for detecting low EN
2 V ≤ VIN ≤ 15 V, falling edge
IIN
Input bias current, EN
EN = GND or VIN
0.4
0.6
V
POWER SWITCH
VIN = 3.6 V
High-side MOSFET ON-resistance
2.3
3.4
1.75
2.5
VIN = 3.6 V
1.3
2.5
VIN = 8 V
1.2
1.75
250
400
VIN = 8 V
RDS(ON)
Low-side MOSFET ON-resistance
Ω
ILIMF
Forward current limit MOSFET highside
VIN = 8 V, open loop
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
700
ns
60
ns
0.8
V
200
mA
REGULATOR
tONmin
Minimum ON time
VIN = 3.6 V, VOUT = 1.8 V
tOFFmin
Minimum OFF time
VIN = 3.6 V, VOUT = 1.8 V
VREF
Internal reference voltage
VFB
Feedback FB voltage comparator
threshold
Referred to 0.8-V internal reference
Feedback FB voltage line regulation
IOUT = 50 mA
Input bias current FB
VFB = 0.8 V
IIN
(1)
(2)
(3)
(3)
–2.5%
0% 2.5%
0.04
0
%/V
50
nA
The typical required supply voltage for startup is 2.5 V. The part is functional down to the falling UVLO (undervoltage lockout) threshold.
Shutdown current into VIN pin, includes internal leakage.
VOUT +1 V ≤ VIN ; VOUT ≤ 5.5 V
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Electrical Characteristics (continued)
VIN = 8 V, VOUT = 1.8 V, EN = VIN, TJ = –40°C to 85°C, typical values are at TJ = 25°C (unless otherwise noted), CIN = 4.7 µF,
L = 22 µH, COUT = 4.7 µF
PARAMETER
TEST CONDITIONS
MIN
tStart
Regulator start-up time
Time from active EN to device starts switching, VIN =
2.6 V
tRamp
Output voltage ramp time
Time to ramp up VOUT = 1.8 V, no load
ILK_SW
Leakage current into SW pin
VOUT = VIN = VSW = 1.8 V, EN = GND, device in
shutdown mode
(4)
TYP MAX
50
150
120
300
1
1.5
UNIT
µs
µA
POWER GOOD OUTPUT (TPS62120)
VTHPG
Power good threshold voltage
VOL
Output low voltage
VH
ILKG
TPGDL
Rising VFB feedback voltage
93%
95%
97%
Falling VFB feedback voltage
87%
90%
93%
Current into PG pin I = 500 µA, VOUT > 1.5 V
165
mV
Current into PG pin I = 100 µA, 1.2 V < VOUT < 1.5 V
50
Output high voltage
Open drain output, external pull up resistor
5.5
V
Leakage current into PG pin
V(PG) = 1.8 V, EN = high, FB = 0.85 V
0
50
nA
Leakage into VOUT pin
V(OUT) = 1.8 V
0
50
nA
Internal power good comparator delay
time
VOUT = 1.8 V
2
5
µs
50
nA
SGND OPEN DRAIN OUTPUT (TPS62120)
RDS(ON)
NMOS drain source resistance
SGND = 1.8 V, VIN = 2 V
370
ILKG
Leakage current into SGND pin
EN = VIN, SGND = 1.8 V
0
(4)
6
Ω
Maximum value not production tested.
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SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
7.6 Typical Characteristics
3.5
20
16
TA = 85°C
2.5
Iq - Quiescent current - mA
RDSon - Low side Switch Resistance - W
18
3
TA = 60°C
TA = 25°C
TA = -40°C
2
1.5
1
TA = 85°C
14
TA = 60°C
12
TA = 25°C
10
8
TA = -40°C
6
Device enabled and
UVLO rising threshold
has been tripped
4
0.5
2
0
0
0
2
4
6
8
10
VI - Input Voltage - V
12
14
0
16
2
4
6
8
10
VI - Input Voltage - V
800
TA = 60°C
1.2
1
TA = 25°C
0.8
TA = -40°C
0.6
500
0.2
100
6
8
10
VI - Input Voltage - V
12
14
VOUT = 3.3 V,
0
0
16
VIN = 12 V
VIN = 15 V
10
20
30
40
50
IO - Output Current - mA
60
Figure 4. Switch Frequency vs Output Current IOUT
(VOUT = 2 V)
900
VIN = 9 V
L = 22 mH LQH3NPN,
COUT = 4.7 mF
VIN = 3 V
300
200
4
VIN = 9 V
400
0.4
2
VIN = 5 V
600
Figure 3. Shutdown Current vs VIN
VOUT = 5.0 V,
VIN = 7 V
800
700
L = 18 mH LPS3015,
COUT = 4.7 mF
VIN = 12 V
700
VIN = 5 V
600
f - Frequency - kHz
f - Frequency - kHz
80
L = 18 mH LPS3015,
COUT = 4.7 mF
700
f - Frequency - kHz
ISD - Shutdown Current - mA
TA = 85°C
1.4
VIN = 12 V
500
VIN = 15 V
400
300
400
300
100
100
20
30
40
50
IO - Output Current - mA
60
70
Figure 5. Switch Frequency vs Output Current IOUT
(VOUT = 3.3 V)
80
VIN = 7 V
500
200
10
VIN = 9 V
600
200
0
0
70
VIN = 7 V
VOUT = 2 V,
800
16
900
1.6
900
14
Figure 2. Quiescent Current vs VIN
Figure 1. Low-Side Switch Resistance RDS(ON) vs VIN
1.8
0
0
12
0
0
VIN = 15 V
10
20
30
40
50
IO - Output Current - mA
60
70
80
Figure 6. Switch Frequency vs Output Current IOUT
(VOUT = 5 V)
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8 Detailed Description
8.1 Overview
The TPS6212x synchronous step-down converter family uses an unique hysteretic PFM/PWM controller scheme
which enables switching frequencies of up to 800 kHz, excellent transient response and AC load regulation at
operation with small output capacitors.
At high load currents the converter operates in quasi fixed frequency pulse width modulation (PWM) mode
operation and at light loads in pulse frequency modulation (PFM) mode to maintain highest efficiency over the full
load current range. In PFM mode, the device generates a single switch pulse to ramp the inductor current and
charge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to
achieve a quiescent current of typically 10 µA. During this time, the load current is supported by the output
capacitor. The duration of the sleep period depends on the load current and the inductor peak current.
A significant advantage of TPS6212x compared to other hysteretic controller topologies is its excellent DC and
AC load regulation capability in combination with low output voltage ripple over the entire load range which
makes this part well suited for audio and RF applications.
8.2 Functional Block Diagram
VIN
Voltage
Reference
VREF
0.80 V
VIN
UVLO
Peak Current
Limit Comparator
VUVLO
Limit
High Side
EN
Softstart
VIN
PMOS
Min. On Time
VOUT
Min. OFF Time
Control
Logic
Gate Driver
Anti
Shoot-Through
SW
VREF
NMOS
VOUT
FB
Feedback
Comparator
Integrated
Divider in
fixed output
voltage versions
Note
PG
1
PG
FB
VTHPG
Thermal
Shutdown
ZeroCurrent
Comparator
GND
Note 1
Output Discharge
SGND
/EN
UVLO
PG Comparator
(1)
8
Function available in TPS62120
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8.3 Feature Description
8.3.1 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. The circuit prevents
the converter from turning on the high-side MOSFET switch or low-side MOSFET under undefined conditions.
The UVLO threshold is set to 2.5 V typical for rising VIN and 1.85 V typical for falling VIN. The hysteresis between
rising and falling UVLO threshold ensures proper start-up even with high-impedance sources. Fully functional
operation is permitted for an input voltage down to the falling UVLO threshold level. The converter starts
operation again once the input voltage trips the rising UVLO threshold level.
8.3.2 Enable and Shutdown
The device starts operation when EN pin is set high and the input voltage VIN has tripped the UVLO threshold for
rising VIN. It starts switching after the regulator start-up time tStart of typically 50 µs has expired and enters the
soft start as previously described. For proper operation, the EN pin must be terminated and must not be left
floating.
EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.3 µA.
In this mode, the high-side and low-side MOSFET switches as well as the entire internal-control circuitry are
switched off.
In TPS62120 the internal N-MOSFET at pin SGND is activated and connects SGND to GND.
8.3.3 Power Good Output
The Power Good Output is an open-drain output available in TPS62120. The circuit is active once the device is
enabled. It is driven by an internal comparator connected to the FB voltage and internal reference. The PG
output provides a high level (open-drain high impedance) once the feedback voltage exceeds typical 95% of its
nominal value. The PG output is driven to low level once the feedback voltage falls below typical 90% of its
nominal value. The PG output is high (high impedance) with an internal delay of typically 2 µs. A pullup resistor is
needed to generate a high level and limit the current into the PG pin to 0.5 mA. The PG pin can be connected
through pullup resistors to a voltage up to 5.5 V.
The PG output is pulled low if the device is enabled but the input voltage is below the UVLO threshold or the
device is turned into shutdown mode.
8.3.4 SGND Open-Drain Output
This is an NMOS open-drain output with a typical RDS(ON) of 370 Ω and can be used to discharge the output
capacitor. The internal NMOS connects SGND pin to GND once the device is in shutdown mode or VIN falls
below the UVLO threshold during operation. SGND becomes high impedance once the device is enabled and VIN
is above the UVLO threshold. If SGND is connected to the output, the output capacitor is discharged through
SGND.
8.3.5 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the high-side and low-side MOSFETs are turned off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis.
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8.4 Device Functional Modes
8.4.1 Soft Start
The TPS6212x has an internal soft-start circuit which controls the ramp-up of the output voltage and limits the
inrush current during start-up. This limits input voltage drop when a battery or a high-impedance power source is
connected to the input of the converter.
The soft-start system generates a monotonic ramp up of the output voltage with a ramp of typically 15 mV/µs and
reaches an output voltage of 1.8 V in typically 170 µs after EN pin was pulled high. The TPS6212x is able to start
into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage
to its nominal value.
During start-up the device can provide an output current of half of the high-side MOSFET switch current limit
ILIMF. Large output capacitors and high load currents may exceed the current capability of the device during startup. In this case the start-up ramp of the output voltage will be slower.
8.4.2 Main Control Loop
The feedback comparator monitors the voltage on the FB pin and compares it to an internal 800-mV reference
voltage.
The feedback comparator trips once the FB voltage falls below the reference voltage. A switching pulse is
initiated and the high-side MOSFET switch is turned on. The switch remains turned on at least for the minimum
on-time TONmin of typical 700 ns until the feedback voltage is above the reference voltage or the inductor current
reaches the high-side MOSFET switch current limit ILIMF. Once the high-side MOSFET switch turns off, the lowside MOSFET switch is turned on and the inductor current ramps down. The switch is turned on at least for the
minimum off time TOFFmin of typically 60 ns. The low-side MOSFET switch stays turned on until the FB voltage
falls below the internal reference and trips the FB comparator again. This will turn on the high-side MOSFET
switch for a new switching cycle.
If the feedback voltage stays above the internal reference the low-side MOSFET switch is turned on until the
zero current comparator trips and indicates that the inductor current has ramped down to zero. In this case, the
load current is much lower than the average inductor current provided during one switching cycle. The regulator
turns the low-side and high-side MOSFET switches off (high impedance state) and enters a sleep cycle with
reduced quiescent current of typically 10 uA until the output voltage falls below the internal reference voltage and
the feedback comparator trips again. This is called PFM mode and the switching frequency depends on the load
current, input voltage, output voltage and the external inductor value.
Once the high-side switch current limit comparator has tripped its threshold of ILIMF, the high-side MOSFET
switch is turned off and the low-side MOSFET switch is turned on until the inductor current has ramped down to
zero.
The minimum on time TONmin for a single pulse can be estimated to:
V
TON = OUT ´ 1.3 μs
VIN
(1)
Therefore the peak inductor current in PFM mode is approximately:
(VIN - VOUT ) ´ T
ILPFMpeak =
ON
L
(2)
The transition from PFM mode to PWM mode operation and back occurs at a load current of approximately 0.5 ×
ILPFMpeak.
With:
TON = High-side MOSFET switch on time [µs]
VIN = Input voltage [V]
VOUT = Output voltage [V]
L = Inductance [µH]
ILPFMpeak = PFM inductor peak current [mA]
The maximum switch frequency can be estimated to:
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Device Functional Modes (continued)
fSWmax »
1
= 770 kHz
1.3 μs
(3)
8.4.3 100% Duty Cycle Low-Dropout Operation
The device will increase the on time of the high-side MOSFET switch once the input voltage comes close to the
output voltage in order to keep the output voltage in regulation. This will reduce the switch frequency.
With further decreasing input voltage VIN the high-side MOSFET switch is turned on completely. In this case the
converter provides a low input-to-output voltage difference. This is particularly useful in applications with widely
variable supply voltage to achieve longest operation time by taking full advantage of the whole supply voltage
span.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
Vinmin = Voutmax + Ioutmax ´ (RDSONmax + R L )
where
•
•
•
•
IOUTmax = maximum output current
RDS(ON)max = maximum P-channel switch RDS(ON)
RL = DC resistance of the inductor
VOUTmax = nominal output voltage plus maximum output voltage tolerance
(4)
8.4.4 Short-Circuit Protection
The TPS6212x integrates a high-side MOSFET switch current limit ILIMF to protect the device against short
circuit. The current in the high-side MOSFET switch is monitored by current limit comparator and once the
current reaches the limit of ILIMF , the high-side MOSFET switch is turned off and the low-side MOSFET switch is
turned on to ramp down the inductor current. The high-side MOSFET switch is turned on again once the zero
current comparator trips and the inductor current has become zero. In this case, the output current is limited to
half of the high-side MOSFET switch current limit 0.5 × ILIMF.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS6212x device is a highly efficient synchronous step-down DC-DC converter optimized for low-power
applications. With its wide input voltage range, the device also fits for energy harvesting applications to convert
electrical power from electromagnetic transducers.
9.2 Typical Applications
9.2.1 TPS62120 With Open-Drain Output
VIN = 2 V to 15 V
TPS62120
VIN
SW
R1
EN
CIN
4.7 µ F
VOUT 1.2 V - 5 V
up to 75mA
L 18 mH/22 mH
COUT
4.7 mF
Cff
FB
R2
GND
VOUT
SGND
PG
Rpullup
PWR GOOD
L = 18 µ H LPS3015 Coilcraft
22 mH LQH3NPN Murata
CIN: 4.7µF GRM21B series X5R (0805size) 25V Murata
COUT: 4.7µF GRM188 sereis X5R (0603size) 6.3V Murata
Figure 7. Standard Circuit for TPS62120 With Open-Drain Output
9.2.1.1 Design Requirements
The device operates over an input voltage range from 2 V to 15V. The output voltage is adjustable using an
external feedback divider network.
The design guideline provides a component selection to operate the device within the Recommended Operating
Conditions.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Output Voltage Setting
The output voltage can be calculated to:
(
VOUT = VREF ´ 1 +
R1 =
(VV
OUT
REF
R1
R2
) with an internal reference voltage VREF typical 0.8 V
)
- 1 ´ R2
(5)
To minimize the current through the feedback divider network, R2 should be within the range of 82 kΩ to 360 kΩ.
The sum of R1 and R2 should not exceed approximately 1 MΩ, to keep the network robust against noise. An
external feedforward capacitor Cff is required for optimum regulation performance. R1 and Cff places a zero in the
feedback loop.
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Typical Applications (continued)
1
= 25 kHz
2 ´ p ´ R1 ´ Cf f
fz =
(6)
The value for Cff can be calculated as:
1
C ff =
2 ´ p ´ R1 ´ 25 kHz
(7)
Table 1 shows a selection of suggested values for the feedback divider network for most common output
voltages.
Table 1. Suggested Values for Feedback Divider Network
VOLTAGE SETTING (V)
3.06
3.29
2.00
1.80
1.20
5.00
R1 [kΩ]
510
560
360
300
180
430
R2 [kΩ]
180
180
240
240
360
82
Cff [pF]
15
22
22
22
27
15
9.2.1.2.2 Output Filter Design (Inductor and Output Capacitor)
The TPS6212x operates with effective inductance values in the range of 10 µH to 33 µH and with effective output
capacitance in the range of 1 µF to 33 µF. The device is optimized to operate for an output filter of L = 22 µH and
COUT = 4.7 µF. Larger or smaller inductor and capacitor values can be used to optimize the performance of the
device for specific operation conditions. For more details, see Checking Loop Stability.
9.2.1.2.3 Inductor Selection
The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be
estimated according to Equation 8.
Equation 9 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 9. This is
recommended because during heavy load transient the inductor current will rise above the calculated value. A
more conservative way is to select the inductor saturation current according to the high-side MOSFET switch
current limit ILIMF.
(VIN - VOUT )
DIL =
´ TON
L
(8)
ΔI
ILmax = Ioutmax + L
2
where
•
•
•
•
TON = See Equation 1
L = Inductor value
ΔIL = Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
(9)
In DC-DC converter applications, the efficiency is essentially affected by the inductor AC resistance (that is,
quality factor) and by the inductor DCR value. To achieve high efficiency operation, care should be taken in
selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value
produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased
inductance usually results in an inductor with lower saturation current.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following frequencydependent components:
• the losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• additional losses in the conductor from the skin effect (current displacement at high frequencies)
• magnetic field losses of the neighboring windings (proximity effect)
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radiation losses
The following inductor series from different suppliers have been used with the TPS6212x converters.
Table 2. List of Inductors
INDUCTANCE (µH)
DIMENSIONS (mm3)
INDUCTOR TYPE
22
3 × 3 × 1.5
LQH3NPN
Murata
18/22
3 × 3 × 1.5
LPS3015
Coilcraft
SUPPLIER
9.2.1.2.4 Output Capacitor Selection
The unique hysteretic PFM/PWM control scheme of the TPS6212x allows the use of ceramic capacitors.
Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. The
output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their
wide variation in capacitance over temperature, become resistive at high frequencies.
At light load currents the converter operates in power save mode and the output voltage ripple is dependent on
the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the
voltage ripple in PFM mode and tighten DC output accuracy in PFM mode.
9.2.1.2.5 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a 4.7 µF to 10 µF ceramic capacitor is recommended. The voltage rating
and DC bias characteristic of ceramic capacitors need to be considered. The input capacitor can be increased
without any limit for better input voltage filtering.
For specific applications like energy harvesting a tantalum or tantalum polymer capacitor can be used to achieve
a specific DC-DC converter input capacitance. Tantalum capacitors provide much better DC bias performance
compared to ceramic capacitors. In this case a 1-µF or 2.2-µF ceramic capacitor should be used in parallel to
provide low ESR.
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce large ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 3 shows a list of input and output capacitors.
Table 3. List of Capacitors
CAPACITANCE
(µF)
SIZE
CAPACITOR TYPE
USAGE
SUPPLIER
4.7
0603
GRM188 series 6.3 V X5R
COUT
Murata
2.2
0603
GRM188 series 6.3 V X5R
COUT
Murata
4.7
0805
GRM21Bseries 25 V X5R
CIN
Murata
10
0805
GRM21Bseries 16 V X5R
CIN
Murata
8.2
B2 (3.5 × 2.8 × 1.9)
20TQC8R2M (20 V)
CIN
Sanyo
9.2.1.2.6 Checking Loop Stability
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
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As a next step in the evaluation of the regulation loop, the load transient response is tested. During application of
the load transient and the turn on of the high-side MOSFET switch, the output capacitor must supply all of the
current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) × ESR, where ESR is the
effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error
signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the
damping factor of the circuitry is directly related to several resistive parameters (for example, MOSFET RDS(on))
which are temperature dependent, the loop stability analysis should be done over the input voltage range, load
current range, and temperature range
9.2.1.3 Application Curves
All graphs have been generated using the circuit as shown in Figure 7 unless otherwise noted.
100
100
IO = 10 mA
VIN = 5.5 V
95
VO = 5 V,
IO = 25 mA
IO = 50 mA
90
VIN = 8 V
90
VIN = 10 V
VIN = 15 V
IO = 5 mA
85
VIN = 12 V
Efficiency - %
Efficiency - %
80
L = 18 mH, LPS3015
CO = 4.7mF
70
60
IO = 1 mA
80
75
IO = 0.1mA
70
65
50
VO = 5 V,
60
L = 18 mH,
LPS3015,
CO = 4.7 mF
40
30
0.1
55
50
1
10
IO - Output Current - mA
5
100
Figure 8. Efficiency vs Output Current IOUT (VOUT = 5 V)
6
7
8
9
10
11
VI - Input Voltage - V
13
14
15
Figure 9. Efficiency vs Input Voltage VIN (VOUT = 5 V)
100
100
IO = 25 mA
90
VO = 3.3 V,
IO = 50 mA
L = 18 mH,
LPS3015,
CO = 4.7 mF
90
IO = 10 mA
VIN = 5 V VIN = 3.5 V
80
VIN = 9 V
VIN = 12 V
70
IO = 5 mA
80
VIN = 7 V
Efficiency - %
Efficiency - %
12
VIN = 15 V
60
IO = 1 mA
70
IO = 0.1 mA
60
50
VO = 3.3 V,
L = 18 mH,
LPS3015,
CO = 4.7 mF
40
30
0.1
50
40
1
10
IO - Output Current - mA
100
Figure 10. Efficiency vs Output Current IOUT (VOUT = 3.3 V)
3
4
5
6
7
8
9
10
VI - Input Voltage - V
11
12
13
14
15
Figure 11. Efficiency vs Input Voltage VIN (VOUT = 3.3 V)
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VIN = 3.5 V
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100
VIN = 7 V
VIN = 5 V
IO = 25 mA
90
VO = 3 V,
IO = 50 mA
L = 18 mH,
LPS3015,
CO = 4.7 mF
90
80
IO = 1 mA
80
Efficiency - %
Efficiency - %
VIN = 9 V
VIN = 12 V
70
VIN = 15 V
60
IO = 5 mA
IO = 10 mA
70
IO = 0.1 mA
60
50
VO = 3 V,
L = 18 mH,
LPS3015,
CO = 4.7 mF
40
30
0.1
1
10
IO - Output Current - mA
50
40
100
3
Figure 12. Efficiency vs Output Current IOUT (VOUT = 3 V)
100
VIN = 4 V
5
6
7
8
9
10
VI - Input Voltage - V
11
12
13
14
15
Figure 13. Efficiency vs Input Voltage VIN (VOUT = 3 V)
100
VIN = 2.5 V
VO = 2 V,
IO = 25 mA
VIN = 6 V
90
4
IO = 50 mA
L = 18 mH,
LPS3015,
CO = 4.7 mF
90
IO = 10 mA
80
VIN = 12 V
VIN = 10 V
VIN = 8 V
Efficiency - %
Efficiency - %
80
70
VIN = 15 V
60
IO = 1 mA
IO = 5 mA
70
60
50
IO = 0.1 mA
VO = 2 V,
L = 18 mH,
LPS3015,
CO = 4.7 mF
40
30
0.1
1
10
IO - Output Current - mA
50
40
2
100
Figure 14. Efficiency vs Output Current IOUT (VOUT = 2 V)
VIN = 5 V
90
VIN = 3 V
4
5
6
7
8
9
10
11
VI - Input Voltage - V
12
13
14
15
Figure 15. Efficiency vs Input Voltage VIN (VOUT = 2 V)
100
VIN = 4 V
3
100
VIN = 2 V
VO = 1.2 V,
90
IO = 10 mA
80
IO = 25 mA
L = 18 mH,
LPS3015,
CO = 4.7 mF
IO = 50 mA
80
VIN = 8 V
60
Efficiency - %
Efficiency - %
70
VIN = 10 V
VIN = 12 V
50
VIN = 15 V
40
70
IO = 1 mA
50
30
VO = 1.2 V,
20
10
0
0.1
1
10
IO - Output Current - mA
30
100
Figure 16. Efficiency vs Output Current IOUT (VOUT = 1.2 V)
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IO = 0.1 mA
40
L = 18 mH,
LPS3015,
CO = 4.7 mF
IO = 5 mA
60
20
2
3
4
5
6
7
8
9
10
11
VI - Input Voltage - V
12
13
14
15
Figure 17. Efficiency vs Input Voltage VIN (VOUT = 1.2 V)
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2.06
3.09
VOUT = 3 V,
VIN = 15 V
VIN = 12 V
3.03
VIN = 10 V
3
VIN = 3.5 V
L = 18 mH LPS3015,
COUT = 4.7 mF
2.04
VO - Output Voltage DC - V
VO - Output Voltage DC - V
3.06
VOUT = 2 V,
L = 18 mH LPS3015,
COUT = 4.7 mF
VIN = 4 V V = 5 V
IN
VIN = 7 V
2.97
2.94
VIN = 9 V
2.02
VIN = 12 V
VIN = 15 V
2
VIN = 2.5 V V = 3 V V = 5 V
IN
IN
VIN = 7 V
1.98
1.96
2.91
0.01
0.1
1
IO - Output Current - mA
10
100
Figure 18. 3.0-V Output Voltage DC Regulation
1.94
0.01
0.1
1
IO - Output Current - mA
10
100
Figure 19. 2.0-V Output Voltage DC Regulation
50
VOUT = 2 V,
45
L = 18 mH,
COUT = 4.7 mF
VO - Ripple Peak to Peak - mV
40
35
30
VIN = 7 V
25
VIN = 9 V
VIN = 12 V
VIN = 15 V
20
15
10
5
VIN = 2.5 V
0
0
10
VIN = 3 V
20
VIN = 5 V
30
40
50
IO - Output Current - mA
60
70
80
Figure 20. VOUT 2.0-V Output Ripple Voltage Peak to Peak
Figure 21. Typical Operation IOUT 60mA
Figure 22. Typical Operation IOUT 10mA
Figure 23. Line Transient Response for 3-V Output Voltage
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Figure 24. Load Transient Response for 3-V Output
Voltage
Figure 25. AC Load Regulation Performance for 3-V Output
Voltage
VIN = 10V
VIN = 5V
VIN = 10V
VIN = 3.3V
18
VIN = 5V
Load = 68R
L = 22uH (LQH32PN)
COUT = 4.7uF (0603)
VOUT = 1.8V
VIN = 3.3V
Load = 68R
L = 22uH (LQH32PN)
COUT = 10uF (0805)
VOUT = 1.8V
Figure 26. TPS62120 Spurious Output Noise
COUT = 4.7 µF
Figure 27. TPS62120 Spurious Output Noise
COUT = 10 µF
Figure 28. AC Load Regulation Performance for 1.8-V
Output Voltage
Figure 29. Output Discharge With SGND Pin Connected to
VOUT
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Figure 30. Startup VOUT = 3 V
Figure 31. Power Good Output During Startup
Figure 32. Startup VOUT 1.8 V
Figure 33. Output Overload Protection
Figure 34. Input Voltage Ramp Up/Down
Figure 35. Startup From a High-Impedance Source
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9.2.2 Standard Circuit for TPS62122
Beside the power good open drain output (PG pin) and the open drain output for output discharge (SGND pin)
the TPS62122 provides the same functionality as the TPS62120.
TPS62122
VIN = 2 V to 15 V
VIN
SW
R1
EN
CIN
4.7 µ F
VOUT 1.2 V - 5 V
up to 75mA
L 18 mH/22 mH
COUT
4.7 mF
Cff
FB
R2
GND
VOUT
L = 18 µ H LPS3015 Coilcraft
22 mH LQH3NPN Murata
CIN: 4.7µF GRM21B series X5R (0805size) 25V Murata
COUT: 4.7µF GRM188 sereis X5R (0603size) 6.3V Murata
Figure 36. Standard Circuit for TPS62122
9.3 System Examples
The TPS6212x is operating with a wide input voltage range from 2 V to 15 V. An open-drain power good output
and an additional SGND pin is available in the TPS62120 for output voltage regulation and to discharge the
output capacitor.
9.3.1 TPS62120 1.8-V Output Voltage Configuration
VOUT 1.8 V
25 mA
TPS62120
VIN = 2 V to 15 V
L 22 µH
VIN
CIN
4.7 µF
EN
SW
R1
300 kW
FB
Cff
22pF
COUT
4.7 µF
R2
240 kW
GND
VOUT
SGND
PG
Rpullup100 kW
PWR GOOD
Figure 37. TPS62120 1.8-V Output Voltage Configuration
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System Examples (continued)
9.3.2 TPS62120 3.06-V Output Voltage Configuration
VOUT 3.06 V
75 mA
TPS62120
VIN = 3.5 V to 15 V
L 22 µH
SW
VIN
R1
510 kW
EN
CIN
4.7 µF
FB
COUT
4.7 µF
Cff
22 pF
R2
180 kW
GND
VOUT
Rpullup100 kW
SGND
PWR GOOD
PG
Figure 38. TPS62120 3.06-V Output Voltage Configuration
9.3.3 TPS62122 2.0-V Output Voltage Configuration
VOUT = 2.0 V
IOUT = 25 mA
TPS62122
VIN = 2.1 V to 15 V
L 22 µH
SW
VIN
R1
360 kW
EN
CIN
4.7 µF
FB
Cff
22 pF
COUT
4.7 µF
R2
240 kW
GND
VOUT
Figure 39. TPS62122 2.0-V Output Voltage Configuration
9.3.4 TPS62120 1.8-V VOUT Configuration Powered From a High-Impedance Source
High Impedance
Source
VOUT 1.8 V
100 µA
TPS62120
L 22 µH
VIN
SW
1 kW
DC
12 V
EN
CIN
10 µF
R1
300 kW
FB
Cff
22 pF
COUT
4.7 µF
R2
240 kW
GND
VOUT
SGND
PG
Rpullup100 kW
PWR GOOD
Figure 40. TPS62120 1.8-V VOUT Configuration Powered From a High-Impedance Source
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Product Folder Links: TPS62120 TPS62122
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10 Power Supply Recommendations
The TPS6212x device family has no special requirements for its input power supply. The output current of the
input power supply needs to be rated according to the supply voltage, output voltage, and output current of the
TPS6212x.
11 Layout
11.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues, as well
as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins
as well as the inductor and output capacitor.
Use a common Power GND node and a different node for the signal GND to minimize the effects of ground
noise. Keep the common path to the GND PIN, which returns the small signal components and the high current
of the output capacitors as short as possible to avoid ground noise. The FB divider network and the VOUT line
must be connected to the output capacitor. The VOUT pin of the converter should be connected through a short
trace to the output capacitor. The FB line must be routed away from noisy components and traces (for example,
SW line).
11.2 Layout Examples
10.5 mm
GND
VIN
VOUT
COUT
L
CIN
7.9 mm
GND
R2 R1 CFF RPG
EN
PG
SGND
VOUT
Figure 41. PCB Layout - DCN Package
22
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Product Folder Links: TPS62120 TPS62122
TPS62120, TPS62122
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SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
Layout Examples (continued)
11.1 mm
GND
VOUT
8.1 mm
CFF
R2
FB
R1
VIN
COUT
EN
FB
CIN
L
GND
Figure 42. PCB Layout - DRV Package
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: TPS62120 TPS62122
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TPS62120, TPS62122
SLVSAD5A – JULY 2010 – REVISED AUGUST 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62120
Click here
Click here
Click here
Click here
Click here
TPS62122
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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Product Folder Links: TPS62120 TPS62122
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62120DCNR
ACTIVE
SOT-23
DCN
8
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
QTX
TPS62120DCNT
ACTIVE
SOT-23
DCN
8
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
QTX
TPS62122DRVR
ACTIVE
WSON
DRV
6
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
OFZ
TPS62122DRVT
ACTIVE
WSON
DRV
6
250
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
OFZ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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