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TPS62201DBVT

TPS62201DBVT

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    SOT23-5

  • 描述:

    IC REG BUCK 1.5V 300MA SOT23-5

  • 数据手册
  • 价格&库存
TPS62201DBVT 数据手册
Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 TPS6220x High-Efficiency, SOT23 Step-Down, DC-DC Converter 1 Features 3 Description • The TPS6220x devices are a family of high-efficiency synchronous step-down converters ideally suited for portable systems powered by 1-cell Li-Ion or 3-cell NiMH/NiCd batteries. The devices are also suitable to operate from a standard 3.3-V or 5-V voltage rail. 1 • • • • • • • • • • • High-Efficiency Synchronous Step-Down Converter With up to 95% Efficiency 2.5-V to 6-V Input Voltage Range Adjustable Output Voltage Range From 0.7 V to VI Fixed Output Voltage Options Available Up to 300-mA Output Current 1-MHz Fixed-Frequency PWM Operation Highest Efficiency Over Wide Load Current Range Due to Power Save Mode 15-µA Typical Quiescent Current Soft Start 100% Duty Cycle Low-Dropout Operation Dynamic Output-Voltage Positioning Available in a 5-Pin SOT23 Package 2 Applications • • • • • • PDAs and Pocket PCs Cellular Phones and Smart Phones Low Power DSP Supplies Digital Cameras Portable Media Players Portable Equipment With an output voltage range of 6 V down to 0.7 V and up to 300 mA output current, the devices are ideal to power low voltage DSPs and processors used in PDAs, pocket PCs, and smart phones. Under nominal load current, the devices operate with a fixed switching frequency of typically 1 MHz. At light load currents, the part enters the power save mode operation; the switching frequency is reduced and the quiescent current is typically only 15 µA; therefore, it achieves the highest efficiency over the entire load current range. The TPS6220x needs only three small external components. Together with the SOT23 package, a minimum system solution size is achieved. An advanced fast response voltage mode control scheme achieves superior line and load regulation with small ceramic input and output capacitors. Device Information(1) PART NUMBER TPS6220x SOT-23 (5) 1 C1 4.7 mF VI SW 2 GND 3 4 EN FB (Fixed Output Voltage Version) 2.90 mm × 1.60 mm Efficiency vs Load Current 100 VO 1.8 V / 300 mA C2 10 mF 95 VO = 1.8 V 90 VI = 2.7 V 85 80 Efficiency − % VI 2.5 V − 6 V L1 5 10 mH BODY SIZE (NOM) (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Schematic TPS62202 PACKAGE VI = 3.7 V 75 VI = 5 V 70 65 60 55 50 45 40 0.010 0.100 1 10 100 1000 IL −Load Current − mA 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 3 3 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information ................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 7 7.1 7.2 7.3 7.4 Overview ................................................................... Functional Block Diagram ......................................... Feature Description................................................... Device Functional Modes.......................................... 7 8 8 9 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application .................................................. 11 8.3 System Examples ................................................... 15 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 11.6 Device Support...................................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (May 2006) to Revision F Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed the format of this data sheet to the new SDA format. No markup for changes. .................................................... 1 2 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 www.ti.com SLVS417F – MARCH 2002 – REVISED JUNE 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View VI 1 GND 2 EN 3 5 SW 4 FB Pin Functions PIN NAME NO. I/O DESCRIPTION EN 3 I This is the enable pin of the device. Pulling this pin to ground forces the device into shutdown mode. Pulling this pin to Vin enables the device. This pin must not be left floating and must be terminated. FB 4 I This is the feedback pin of the device. Connect this pin directly to the output if the fixed output voltage version is used. For the adjustable version an external resistor divider is connected to this pin. The internal voltage divider is disabled for the adjustable version. GND 2 — Ground SW 5 I/O Connect the inductor to this pin. This pin is the switch pin and is connected to the internal MOSFET switches. VI 1 I Supply voltage pin 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltages (2) VI Voltages on pins SW, EN, FB (2) MIN MAX UNIT –0.3 7.0 V –0.3 VCC +0.3 V PD Continuous power dissipation TJ Operating junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) (2) See Thermal Information Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 3 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VI Supply voltage 2.5 6.0 VO Output voltage for adjustable output voltage version 0.7 VI IO Output current L Inductor (1) 300 4.7 (1) UNIT V V mA 10 µH 4.7 µF CI Input capacitor CO Output capacitor (1) TA Operating ambient temperature 40 85 °C TJ Operating junction temperature 40 125 °C (1) 10 µF See Application and Implementation for further information. 6.4 Thermal Information TPS6220x THERMAL METRIC (1) DBV [SOT-23] UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 220 °C/W RθJC(top) Junction-to-case (top) thermal resistance 125 °C/W RθJB Junction-to-board thermal resistance 36 °C/W ψJT Junction-to-top characterization parameter 14 °C/W ψJB Junction-to-board characterization parameter 35 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 www.ti.com SLVS417F – MARCH 2002 – REVISED JUNE 2015 6.5 Electrical Characteristics VI = 3.6 V, VO = 1.8 V, IO = 200 mA, EN = VIN, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI Input voltage 6 V IQ Operating quiescent current IO = 0 mA, Device is not switching 2.5 15 30 µA Shutdown supply current EN = GND 0.1 1 µA 2 V Undervoltage lockout threshold 1.5 EN high level input voltage 1.3 ENABLE V(EN) I(EN) V EN low level input voltage EN input bias current 0.4 V EN = GND or VIN 0.01 0.1 µA VIN = VGS = 3.6 V 530 690 VIN = VGS = 2.5 V 670 850 VIN = VGS = 3.6 V 430 540 VIN = VGS = 2.5 V 530 660 POWER SWITCH P-channel MOSFET on-resistance rds(ON) N-channel MOSFET on-resistance mΩ mΩ Ilkg_(P) P-channel leakage current VDS = 6.0 V 0.1 1 Ilkg_(N) N-channel leakage current VDS = 6.0 V 0.1 1 µA I(LIM) P-channel current limit 2.5 V < Vin < 6.0 V 480 670 mA 1000 1500 kHz 380 µA OSCILLATOR fS Switching frequency 650 OUTPUT VO Adjustable output voltage Vref Reference voltage Feedback voltage 0.7 VIN V 0.5 (1) Fixed output voltage (1) VO TPS62200 TPS62200 VI = 3.6 V to 6 V, IO = 0 mA Adjustable VI = 3.6 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62207 VI = 2.5 V to 6 V, IO = 0 mA 1.2 V VI = 2.5 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62201 VI = 2.5 V to 6 V, IO = 0 mA 1.5 V VI = 2.5 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62204 VI = 2.5 V to 6 V, IO = 0 mA 1.6 V VI = 2.5 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62202 VI = 2.5 V to 6 V, IO = 0 mA 1.8 V VI = 2.5 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62208 VI = 2.5 V to 6 V, IO = 0 mA 1.875 V VI = 2.5 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62205 VI = 2.7 V to 6 V, IO = 0 mA 2.5 V VI = 2.7 V to 6 V, 0 mA ≤ IO ≤ 300 mA TPS62203 VI = 3.6 V to 6 V, IO = 0 mA 3.3 V VI = 3.6 V to 6 V, 0 mA ≤ IO ≤ 300 mA V 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% 0% 3% –3% 3% Line regulation VI = 2.5 V to 6 V, IO = 10 mA Load regulation IO = 100 mA to 300 mA Ilkg Leakage current into SW pin Vin > Vout, 0 V ≤ Vsw ≤ Vin 0.1 1 µA Ilkg(Rev) Reverse leakage current into pin SW Vin = open, EN = GND, VSW = 6 V 0.1 1 µA (1) 0.26 %/V 0.0014 %/mA For output voltages ≤ 1.2 V, a 22-µF output capacitor value is required to achieve a maximum output voltage accuracy of 3% while operating in power save mode (PFM mode). Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 5 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com 6.6 Typical Characteristics Table 1. Table of Graphs FIGURES vs Load current Figure 6, Figure 7, Figure 8 vs Input voltage Figure 9 No load quiescent current vs Input voltage Figure 1 fs Switching frequency vs Temperature Figure 10 Vo Output voltage vs Output current Figure 11 rds(on) - P-channel switch, vs Input voltage Figure 2 rds(on) - N-channel rectifier switch vs Input voltage η Efficiency IQ rds(on) Figure 3 Line transient response Figure 12 Load transient response Figure 13 Power save mode operation Figure 14 Start-up Figure 15 0.8 0.7 TA = 85°C 20 r ds(on) − P-Channel Switch − W N0 Load Quiescent Current − m A 25 TA = 25°C 15 TA = −40°C 10 5 0 2.50 TA = 85°C 0.6 TA = 25°C 0.5 TA = −40°C 0.4 0.3 3 3.50 4 4.50 5 5.50 0.2 2.5 6 3 VI − Input Voltage − V 3.5 4 4.5 5 VI − Input Voltage − V 5.5 6 Figure 2. rds(on) P-Channel Switch vs Input Voltage Figure 1. No Load Quiescent Current vs Input Voltage rDS(on) N-Channel Switch — W 0.8 0.7 0.6 TA = 85°C 0.5 TA = 25°C 0.4 TA = −40°C 0.3 0.2 2.5 3 3.5 4 4.5 5 VI − Input Voltage − V 5.5 6 Figure 3. rds(on) N-Channel Switch vs Input Voltage 6 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 www.ti.com SLVS417F – MARCH 2002 – REVISED JUNE 2015 7 Detailed Description 7.1 Overview The TPS6220x device is a synchronous step-down converter operating with typically 1-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents and in power save mode operating with pulse frequency modulation (PFM) at light load currents. During PWM operation the converter uses a unique fast response, voltage mode, controller scheme with input voltage feed forward. This achieves good line and load regulation and allows the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal (S), the P-channel MOSFET switch is turned on, and the inductor current ramps up until the comparator trips and the control logic turns off the switch. The current limit comparator also turns off the switch in case the current limit of the P-channel switch is exceeded. Then the N-channel rectifier switch is turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off the N-channel rectifier and turning on the P-channel switch. The GM amplifier and input voltage determines the rise time of the Sawtooth generator; therefore any change in input voltage or output voltage directly controls the duty cycle of the converter. This gives a very good line and load transient regulation. Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 7 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com 7.2 Functional Block Diagram VI Current Limit Comparator + _ Undervoltage Lockout Bias Supply + _ Soft Start V I REF Skip Comparator REF 1 MHz Oscillator V(COMP) P-Channel Power MOSFET Comparator S + _ R Sawtooth Generator Driver Shoot-Through Logic Control Logic Comparator High SW N-Channel Power MOSFET Comparator Low Comparator Low 2 Load Comparator + _ Comparator High + Gm _ Comparator Low Comparator Low 2 EN R1 Compensation VREF = 0.5 V + _ R2 See Note FB GND For the adjustable version (TPS62200), the internal feedback divider is disabled and the FB pin is directly connected to the internal GM amplifier. 7.3 Feature Description 7.3.1 Undervoltage Lockout The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. 7.3.2 Dynamic Voltage Positioning As described in the power save mode operation sections and as detailed in Figure 4, the output voltage is typically 0.8% above the nominal output voltage at light load currents, as the device is in power save mode. This gives additional headroom for the voltage drop during a load transient from light load to full load. During a load transient from full load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel rectifier switch. 8 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 www.ti.com SLVS417F – MARCH 2002 – REVISED JUNE 2015 Feature Description (continued) 7.3.3 Soft Start The TPS6220x has an internal soft start circuit that limits the inrush current during start-up. This prevents possible voltage drops of the input voltage in case a battery or a high-impedance power source is connected to the input of the TPS6220x. The soft start is implemented as a digital circuit increasing the switch current in steps of typically 60 mA, 120 mA, 240 mA, and then the typical switch current limit of 480 mA. Therefore the start-up time mainly depends on the output capacitor and load current. Typical start-up time with a 10-µF output capacitor and 200-mA load current is 800 µs. 7.3.4 Low Dropout Operation 100% Duty Cycle The TPS6220x offers a low input to output voltage difference, while still maintaining operation with the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly useful in battery powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation, depending on the load current and output voltage, can be calculated as: Vinmin = Voutmax + Ioutmax ´ (rds (ON)max + RL ) where • • • • Ioutmax = maximum output current plus inductor ripple current. rds(ON)max = maximum P-channel switch rds(ON). RL = DC resistance of the inductor. Voutmax = nominal output voltage plus maximum output voltage tolerance. (1) 7.3.5 Enable Pulling the enable low forces the part into shutdown, with a shutdown quiescent current of typically 0.1 µA. In this mode, the P-channel switch and N-channel rectifier are turned off, the internal resistor feedback divider is disconnected, and the whole device is in shutdown mode. If an output voltage, which could be an external voltage source or super capacitor, is present during shutdown, the reverse leakage current is specified under Electrical Characteristics. For proper operation the enable pin must be terminated and must not be left floating. Pulling the enable high starts up the TPS6220x with the soft start as previously described. 7.4 Device Functional Modes 7.4.1 Power Save Mode Operation As the load current decreases, the converter enters the power save mode operation. During power save mode, the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. Two conditions allow the converter to enter the power save mode operation. One is when the converter detects the discontinuous conduction mode. The other is when the peak switch current in the P-channel switch goes below the skip current limit. The typical skip current limit can be calculated as Vin Iskip £ 66 mA + 160 W (2) During the power save mode, the output voltage is monitored with the comparator by the thresholds comparator low and comparator high. As the output voltage falls below the comparator low threshold set to typically 0.8% above Vout nominal, the P-channel switch turns on. The P-channel switch is turned off as the peak switch current is reached. The typical peak switch current can be calculated: Vin Ipeak = 66 mA + 80 W (3) Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 9 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com Device Functional Modes (continued) The N-channel rectifier is turned on and the inductor current ramps down. As the inductor current approaches zero, the N-channel rectifier is turned off and the P-channel switch is turned on again, starting the next pulse. The converter continues these pulses until the comparator high threshold (set to typically 1.6% above Vout nominal) is reached. The converter enters a sleep mode, reducing the quiescent current to a minimum. The converter wakes up again as the output voltage falls below the comparator low threshold again. This control method reduces the quiescent current typically to 15 µA and reduces the switching frequency to a minimum, thereby achieving the high converter efficiency. Setting the skip current thresholds to typically 0.8% and 1.6% above the nominal output voltage at light load current results in a dynamic output voltage achieving lower absolute voltage drops during heavy load transient changes. This allows the converter to operate with a small output capacitor of just 10 µF and still have a low absolute voltage drop during heavy load transient changes. See Figure 4 for detailed operation of the power save mode. PFM Mode at Light Load 1.6% Comparator High 0.8% Comparator Low VO Comparator Low 2 PWM Mode at Medium to Full Load Figure 4. Power Save Mode Thresholds and Dynamic Voltage Positioning The converter enters the fixed frequency PWM mode again as soon as the output voltage falls below the comparator low 2 threshold. 10 Submit Documentation Feedback Copyright © 2002–2015, Texas Instruments Incorporated Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 www.ti.com SLVS417F – MARCH 2002 – REVISED JUNE 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS6220x devices are a family of high-efficiency synchronous step-down converters ideally suited for portable systems powered by 1-cell Li-Ion or 3-cell NiMH/NiCd batteries. The devices are also suitable to operate from a standard 3.3-V or 5-V voltage rail. 8.2 Typical Application TPS62200 VI 2.5 V − 6 V C3 4.7 mF VI SW R1 470k GND EN L1 10 mH C1 33 pF C4 10 mF VO 1.8 V / 300 mA FB R2 180k C2 100 pF Figure 5. Typical Application Circuit for the Adjustable Output Voltage 8.2.1 Design Requirements The Detailed Design Procedure provides a component selection to operate the device within the Recommended Operating Conditions. 8.2.2 Detailed Design Procedure 8.2.2.1 Adjustable Output Voltage Version When the adjustable output voltage version TPS62200 is used, the output voltage is set by the external resistordivider. See Figure 5. The output voltage is calculated as: R1 ö æ Vout = 0.5 V ´ ç 1 + ÷ R2 è ø where • R1 + R2 ≤ 1 MΩ and internal reference voltage V(ref)typ = 0.5 V. (4) R1 + R2 should not be greater than 1 MΩ for reasons of stability. To keep the operating quiescent current to a minimum, the feedback resistor-divider should have high impedance with R1+R2 ≤ 1 MΩ. Because of the high impedance and the low reference voltage of Vref = 0.5 V, the noise on the feedback pin (FB) needs to be minimized. Using a capacitive divider C1 and C2 across the feedback resistors minimizes the noise at the feedback without degrading the line or load transient performance. C1 and C2 should be selected as: 1 C1 = 2 ´ p ´ 10 kHz ´ R1 where • R1 = upper resistor of voltage divider. Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62200 TPS62201 TPS62202 TPS62203 TPS62204 TPS62205 TPS62207 TPS62208 11 TPS62200, TPS62201, TPS62202, TPS62203 TPS62204, TPS62205, TPS62207, TPS62208 SLVS417F – MARCH 2002 – REVISED JUNE 2015 www.ti.com Typical Application (continued) • C1 = upper capacitor of voltage divider. (5) For C1 a value should be chosen that comes closest to the calculated result. R1 C2 = ´ C1 R2 where • • R2 = lower resistor of voltage divider. C2 = lower capacitor of voltage divider. (6) For C2 the selected capacitor value should always be selected larger than the calculated result. For example, in Figure 5 for C2, 100 pF are selected for a calculated result of C2 = 86.17 pF. If quiescent current is not a key design parameter, C1 and C2 can be omitted, and a low-impedance feedback divider must be used with R1+R2
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