TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
QFN-10
www.ti.com
CSP-8
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
500-mA, 3-MHz SYNCHRONOUS STEP-DOWN CONVERTER
IN CHIP SCALE PACKAGING
FEATURES
1
•
•
•
•
•
•
•
•
Up to 93% Efficiency at 3-MHz Operation
Up to 500-mA Output Current at VI = 2.7 V
3-MHz Fixed Frequency Operation
Best in Class Load and Line Transient
Complete 1-mm Component Profile Solution
-0.5% / +1.3% PWM DC Voltage Accuracy Over
Temperature
35-ns Minimum On-Time
Power-Save Mode Operation at Light Load
Currents
Fixed and Adjustable Output Voltage
Only 86-µA Quiescent Current
100% Duty Cycle for Lowest Dropout
Synchronizable On the Fly to External
Clock Signal
Integrated Active Power-Down Sequencing
(TPS6232x only)
Available in a 10-Pin QFN (3 x 3 mm), 8-Pin
NanoFree™, and NanoStar™ (CSP) Packaging
APPLICATIONS
•
•
•
•
•
•
Cell Phones, Smart-Phones
WLAN and Bluetooth™ Applications
Micro DC-DC Converter Modules
PDAs, Pocket PCs
USB-Based DSL Modems
Digital Cameras
TPS62303YZD
2.7 V . . 6 V
VI
C1
4.7 µF
A2 VIN
B2 EN
L1
SW B1
D1 1 µH
VOUT
C2
C1 MODE/SYNC
ADJ
D2
A1 GND
FB
C2
DESCRIPTION
The TPS623xx device is a high-frequency
synchronous step-down dc-dc converter optimized for
battery-powered portable applications. Intended for
low-power applications, the TPS623xx supports up to
500-mA load current and allows the use of tiny, low
cost chip inductor and capacitors.
The device is ideal for mobile phones and similar
portable applications powered by a single-cell Li-Ion
battery or by 3-cell NiMH/NiCd batteries. With an
output voltage range from 5.4 V down to 0.6 V, the
device supports the low-voltage TMS320™ DSP
family, processors in smart-phones, PDAs as well as
notebooks, and handheld computers.
The TPS62300 operates at 3-MHz fixed switching
frequency and enters the power-save mode operation
at light load currents to maintain high efficiency over
the entire load current range. For low noise
applications, the device can be forced into fixed
frequency PWM mode by pulling the MODE/SYNC
pin high. The device can also be synchronized to an
external clock signal in the range of 3 MHz. In the
shutdown mode, the current consumption is reduced
to less than 1 µA.
The TPS623xx is available in a 10-pin leadless
package (3 x 3 mm QFN) and an 8-pin chip-scale
package (CSP).
100
VI = 3.6 V,
VO = 1.8 V
90
80
VO
1.8 V/500 mA
4.7 µF
Efficiency − %
•
•
•
•
•
•
234
70
60
50
40
30
20
Figure 1. Smallest Solution Size Application
(Fixed Output Voltage)
L = 2.2 µH,
CO = 4.7 µF
10
0
0.1
1
10
100
1k
IO − Load Current − mA
Figure 2. Efficiency vs Load Current
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree, NanoStar, TMS320 are trademarks of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc.
PowerPAD is a trademark of Texas Instsruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PART
NUMBER
OUTPUT
VOLTAGE
TPS62300
Adjustable
TPS62301
TPS62302
TPS62303
TPS62304
-40°C to 85°C
(2)
2
1.6 V
1.8 V
1.2 V
PACKAGE
ORDERING (1) (2)
PACKAGE
MARKING
2.4 V
QFN-10
TPS62300DRC
AMN
2.4 V
CSP-8
TPS62300YZD
N/A
2.4 V
QFN-10
TPS62301DRC
AMO
2.4 V
CSP-8
TPS62301YZD
N/A
2.4 V
QFN-10
TPS62302DRC
AMQ
2.4 V
CSP-8
TPS62302YZD
N/A
2.4 V
QFN-10
TPS62303DRC
AMR
2.4 V
CSP-8
TPS62303YZD
N/A
2.4 V
QFN-10
TPS62304DRC
AMS
2.4 V
CSP-8
TPS62304YZD
N/A
2.4 V
QFN-10
TPS62305DRC
ANU
TPS62305
1.875 V
2.4 V
CSP-8
TPS62305YZD
N/A
TPS62311
1.5 V
2V
CSP-8
TPS62311YZD
N/A
TPS62313
1.8 V
2V
CSP-8
TPS62313YZD
N/A
TPS62315
1.875 V
2V
CSP-8
TPS62315YZ
N/A
2.4 V
QFN-10
TPS62320DRC
AMX
TPS62320
Adjustable
2.4 V
CSP-8
TPS62320YZD
N/A
2.4 V
CSP-8
TPS62320YED
N/A
2.4 V
QFN-10
TPS62321DRC
AMY
2.4 V
CSP-8
TPS62321YZD
N/A
2.4 V
CSP-8
TPS62321YED
N/A
TPS62321
(1)
1.5 V
UNDERVOLTAGE
LOCKOUT
1.5 V
The YZD, YED and YZ packages are available in tape and reel. Add a R suffix (e.g. TPS62300YxDR) to order quantities of 3000 parts.
Add a T suffix (e.g. TPS62300YxDT) to order quantities of 250 parts. The DRC package is available in tape and reel. Add a R suffix
(e.g. TPS62300DRCR) to order quantities of 3000 parts.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Voltage at VIN, AVIN (2)
Voltage at SW
VI
-0.3 V to 7 V
(2)
-0.3 V to 7 V
Voltage at FB, ADJ
Voltage at EN, MODE/SYNC
-0.3 V to 3.6 V
(2)
Voltage at VOUT (2)
IO
Continuous output current
Power dissipation
TA
Operating temperature range
TJ (max) Maximum operating junction temperature
Tstg
ESD
rating (3)
Storage temperature range
(2)
(3)
0.3 V to 5.4 V
500 mA
Internally limited
-40°C to 85°C
150°C
-65°C to 150°C
Human body model at AVIN, FB, ADJ, EN, MODE_SYNC, VOUT
2 kV
Human body model at VIN, SW
1 kV
Charge device model
(1)
-0.3 V to VI + 0.3 V
1.5 kV
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
3
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
DISSIPATION RATINGS (1)
RθJA (2)
POWER RATING
FOR TA≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
DRC
49°C/W
2050 mW
21 mW/°C
YZD
250°C/W
400 mW
4 mW/°C
YED
250°C/W
400 mW
4 mW/°C
YZ
250°C/W
400 mW
4 mW/°C
PACKAGE
(1)
(2)
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = [TJ(max)-TA] / θJA
This thermal data is measured with low-K board (1 layer board according to JESD51-7 JEDEC standard).
ELECTRICAL CHARACTERISTICS
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VI
Input voltage range
Operating
quiescent
current
IQ
I(SD)
2.7
Undervoltage
lockout threshold
V
86
105
µA
IO = 0 mA. PFM mode enabled, device not switching
86
120
µA
IO = 0 mA. Switching with no load
(MODE/SYNC = VIN)
3.6
EN = GND
IO = 0 mA. PFM mode enabled, device not switching
TPS6231x
TPS6230x
TPS6231x
TPS6232x
mA
0.1
1
µA
TPS6230x
TPS6232x
2.40
2.55
V
TPS6231x
2.00
2.20
V
Shutdown current
UVLO
6
TPS6230x
TPS6232x
ENABLE, MODE/SYNC
V(EN)
EN high-level input voltage
1.2
V
V(MODE/SYNC)
MODE/SYNC high-level input voltage
1.3
V
V(EN),
V(MODE/SYNC)
EN, MODE/SYNC low-level input
voltage
I(EN),
I(MODE/SYNC)
EN, MODE/SYNC input leakage
current
0.4
V
1
µA
EN, MODE/SYNC = GND or VIN
0.01
VI = V(GS) = 3.6 V
420
750
mΩ
VI = V(GS) = 2.8 V
520
1000
mΩ
1
µA
VI = V(GS) = 3.6 V
330
750
mΩ
VI = V(GS) = 2.8 V
400
1000
mΩ
30
50
1
µA
780
890
mA
POWER SWITCH
TPS6230x
TPS6231x
TPS6232x
rDS(on)
P-channel MOSFET
on resistance
Ilkg
P-channel leakage current, PMOS
V(DS) = 6 V
rDS(on)
N-channel MOSFET on resistance
R(DIS)
Discharge resistor for power-down
sequence (TPS6232x only)
Ilkg
N-channel leakage current, NMOS
V(DS) = 6 V
P-MOS current limit
2.7 V ≤ VI ≤ 6 V
N-MOS current limit - sourcing
2.7 V ≤ VI ≤ 6 V
550
720
890
mA
N-MOS current limit - sinking
2.7 V ≤ VI ≤ 6 V
–460
–600
–740
mA
Input current limit under short-circuit
conditions
VO = 0 V
Thermal shutdown
Thermal shutdown hysteresis
4
Submit Documentation Feedback
670
Ω
390
mA
150
°C
20
°C
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
VI = 3.6 V, VO = 1.6 V, EN = VI, MODE/SYNC = GND, L = 1 µH, CO = 10 µF, TA = -40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3
OSCILLATOR
fSW
Oscillator frequency
2.65
3.35
MHz
f(SYNC)
Synchronization range
2.65
3.35
MHz
Duty cycle of external clock signal
20%
80%
0.6
5.4
OUTPUT
VO
Adjustable output
voltage range
TPS62300
TPS62320
V(FB)
Regulated feedback
voltage
TPS62300
TPS62320
A(PT)
DC power train amplification
(VO/V(ADJ))
ton(MIN)
Minimum on-time (P-channel
MOSFET)
0.4
1.496
I(FB)
TPS62300
TPS62320
Adjustable output
voltage (1)
TPS62300
TPS62320
Fixed output voltage
VO
V(FB) > 0.4 V
Feedback input bias
current
Adjustable output
voltage dc accuracy (1)
Fixed output voltage
dc accuracy
(1)
700
1000
700
1000
V(FB) = 0.4 V
ns
kΩ
1300
1
–2%
+2%
TPS62304
-2%
+2.5%
TPS62305
TPS62315
–2%
+2.7%
TPS6230x
TPS62311
TPS62313
TPS6232x
2.7 V ≤ VI ≤ 6 V, 0 mA ≤ IO(DC) ≤ 500 mA
PFM/PWM mode operation
TPS62300
TPS62320
TA = 25°C
–0.5%
+1.3%
–40°C ≤ TA ≤ 85°C
–0.5%
+1.3%
TPS6230x
TPS62311
TPS62313
TPS6232x
TA = 25°C
–0.5%
+1.3%
–40°C ≤ TA ≤ 85°C
–0.5%
+1.3%
TA = 25°C
-0.5%
+1.8%
–40°C ≤ TA ≤ 85°C
-0.5%
+1.8%
TA = 25°C
–0.3%
+1.7%
–40°C ≤ TA ≤ 85°C
–0.5%
TPS62304
PWM mode operation,
VI = 3.6 V, No Load
kΩ
nA
+2%
+2%
DC output voltage load regulation
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.001
–0.002
%/mA
DC output voltage load regulation
(power train in direct drive mode)
V(ADJ) externally forced to 1.067 V,
IO = 0 mA to 500 mA, MODE/SYNC = VI
–0.0003
–0.0006
%/mA
DC output voltage line regulation
VI = VO + 0.5 V (min 2.7 V) to
6 V, IO = 100 mA, MODE/SYNC = VI
0.11
0.2
%/V
DC output voltage line regulation
(power train in direct drive mode)
V(ADJ) externally forced to 1.067 V,
VI = VO + 0.5 V (min 2.7 V) to 6 V
IO = 100 mA, MODE/SYNC = VI
0.035
0.1
%/V
150
200
µV/µs
Integrator slew rate
Ilkg
1.504
–2%
TPS62305
TPS62315
ΔVO
V
35
Resistance into VOUT sense pin
Resistance into ADJ pin
1.5
V
100
Power-save mode ripple voltage
IO = 1 mA, MODE/SYNC = GND
0.025 VO
Start-up time
IO = 200 mA, Time from active EN to VO
250
VP-P
Leakage current into SW pin
VI > VO, 0 V ≤ V(SW) ≤ VIN, EN = GND
0.1
1
Reverse leakage current into SW pin
VI = open, V(SW) = 6 V, EN = GND
0.1
1
µs
µA
Output voltage specification for the adjustable version does not include tolerance of external voltage programming resistors.
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
5
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
PIN ASSIGNMENTS
TPS6230x, TPS6232x
FIXED OUTPUT VOLTAGE (QFN-10)
(TOP VIEW)
TPS62300, TPS62320
QFN-10
(TOP VIEW)
SW
PGND
MODE/SYNC
AGND
VOUT
VIN
AVIN
EN
ADJ
FB
TPS6230x, TPS6231x, TPS6232x
CSP-8
(TOP VIEW)
GND
A1
A2
VIN
SW
B1
B2
EN
MODE/SYNC
C1
C2
ADJ
VOUT
D1
D2
FB
SW
PGND
MODE/SYNC
AGND
VOUT
VIN
AVIN
EN
NC
NC
TPS6230x, TPS6231x, TPS6232x
CSP-8
(BOTTOM VIEW)
VIN
A2
A1
GND
EN
B2
B1
SW
ADJ
C2
C1
MODE/SYNC
FB
D2
D1
VOUT
TERMINAL FUNCTIONS
TERMINAL
NO.
QFN
NO.
CSP
I/O
VIN
1
A2
I
Supply voltage for output power stage.
AVIN
2
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
EN
3
I
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin to VI enables the device. This pin must not be left floating and must be
terminated.
NAME
ADJ
4
B2
C2
I/O
DESCRIPTION
This is the internal reference voltage used to regulate VO. This pin is not connected on fixed output
voltage version of TPS6230xDRC and TPS6232xDRC. Do not connect ADJ pin on fixed output
voltage version of TPS6230xYZD, TPS6231xYZD, TPS6231xYZ and TPS6232xYxD.
On TPS62300 and TPS62320, this pin can also be used as an external control input. The output
voltage is 1.5x the applied voltage at ADJ.
FB
5
D2
I
This is the feedback pin of the device. For the adjustable version, an external resistor divider is
connected to this pin. The internal voltage divider is disabled for the adjustable version. This pin is
not connected on fixed output voltage version of TPS6230xDRC and TPS6232xDRC. Do not
connect the FB pin on the fixed output voltage version of TPS6230xYZD, TPS6231xYZD,
TPS6231xYZ and TPS6232xYxD.
VOUT
6
D1
I
Output feedback sense input. Connect VOUT to the converter’s output.
AGND
7
Analog ground. Connect to PGND via the PowerPAD™ underneath IC.
Input for synchronization to external clock signal. This pin must not be left floating and must be
terminated. Synchronizes the converter switching frequency to an external clock signal
MODE/SYNC
8
C1
PGND
9
A1
SW
10
B1
I
MODE/SYNC = LOW (GND): The device is operating in fixed frequency pulse width modulation
mode (PWM) at high-load currents and in pulse frequency modulation mode (PFM) at light load
currents.
MODE/SYNC = HIGH (VIN): Low-noise mode enabled, fixed frequency PWM operation forced.
PowerPAD™
6
Power ground.
I/O
This is the switch pin of the converter and is connected to the drain of the internal Power
MOSFETs.
N/A
Internally connected to PGND.
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
MODE/SYNC
EN
VIN
N-MOS Current Limit
Compator
Undervoltage
Lockout
Bias Supply
AVIN
_
Soft-Start
VREF = 0.4 V
Band Gap
Power-Save
Mode
3-MHz
Oscillator + PLL
Sawtooth
Generator
Thermal
Shutdown
Comp Low
2R
C
R
-
VOUT
-
+
+
+
VREF
A
R2
_
REF
P-MOS Current Limit
Compator
-
+
-
SW
Gate Driver
2C
FB
REF
+
Switching
Logic
RAMP HEIGHT
0.1 VIN
:
+
R(DIS)
+
_
+
-
+
+
A(DC) = 3
Mid-, High-Frequency
Zero-Pole Pair
Anti
Shoot-Through
Summing
Comparator
EN
P
TPS6232x
Only
P
R1
VOUT
See note A
Comparator Low
ADJ
A
-1.5% V OUT(NOMINAL)
+
_
PGND
AGND
NOTE A:
PARAMETER MEASUREMENT INFORMATION
U1
1
2.7 V . . 6 V
VI
C1
2
3
8
VIN
AVIN
EN
SW
VOUT
ADJ
MODE/SYNC FB
7 AGND
A
10
L1
VO
1.6 V/500 mA
6
C2
4 R1
10 mF
5
PGND 9
A
R2
A
List of Components:
U1 = TPS6230x
L1 = FDK MIPW3226 Series
C1, C2 = X5R/X7R
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
7
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
η
Efficiency
vs Load current
3, 4, 5, 6
vs Input voltage
7
Line transient response
8
Load transient response
9, 10, 11, 12,
13, 14, 15, 16
VO
DC output voltage
vs Load current
17
VFB
Regulated feedback voltage
vs Temperature
18
IQ
No load quiescent current
vs Input voltage
19
fs
Switching frequency
vs Temperature
20
Duty cycle jitter
rDS(on)
21
P-channel MOSFET rDS(on)
vs Input voltage
22
N-channel MOSFET rDS(on)
vs Input voltage
23
PWM operation
24
Power-save mode operation
25
Dynamic voltage management
26, 27
Start-up
28, 29
Power down (TPS6232x)
30
EFFICIENCY
vs
LOAD CURRENT
100
VI = 3.6 V,
VO = 1.8 V
90
EFFICIENCY
vs
LOAD CURRENT
100
PFM/PWM Operation
L = 2.2 mH
90
PFM/PWM Operation
L = 0.9 mH
60
50
40
PWM Operation
L = 2.2 mH
70
Efficiency − %
70
Efficiency − %
PFM/PWM Operation
L = 2.2 mH
80
80
60
40
30
20
20
10
10
1
10
100
IO − Load Current − mA
Figure 3.
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1000
PWM Operation
L = 0.9 mH
50
30
0
0.1
8
VI = 3.6 V,
VO = 1.6 V
0
0.1
1
10
100
IO − Load Current − mA
1000
Figure 4.
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
90
PFM/PWM Operation
L = 2.2 mH
80
90
80
70
60
Efficiency − %
Efficiency − %
70
PWM Operation
L = 2.2 mH
50
40
30
60
PWM Operation
L = 0.9 mH
50
40
30
20
20
VI = 3.6 V,
VO = 1.2 V
10
0
PFM/PWM Operation
L = 2.2 mH
0.1
1
10
100
IO − Load Current − mA
VI = 5 V,
VO = 3.3 V
10
0
1000
0.1
1
10
100
IO − Load Current − mA
Figure 5.
Figure 6.
EFFICIENCY
vs
INPUT VOLTAGE
LINE TRANSIENT RESPONSE
1000
IO = 400 mA
80
Efficiency − %
70
IO = 1 mA
60
IO = 10 mA
50
VO = 1.6 V
L = 0.9 mH, CO = 10 mF
V O = 10 mV/div − 1.6 V Offset
IO = 100 mA
90
VI = 1 V/div − 3.6 V Offset
100
40
30
20
PFM/PWM Operation
VO = 1.8 V
10
0
2.7 3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6
VI − Input Voltage − V
Figure 7.
Copyright © 2004–2007, Texas Instruments Incorporated
t − Time − 100 ms/div
Figure 8.
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TPS62315, TPS62320, TPS62321
9
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
IO = 10 to 400 mA Load Step
MODE/SYNC = HIGH
L = 0.9 mH, CO = 10 mF
IO = 10 to 100 mA Load Step
IO = 10 to 400 mA Load Step
t − Time − 2 ms/div
t − Time − 50 ms/div
Figure 9.
Figure 10.
MODE/SYNC = HIGH
L = 0.9 mH, CO = 10 mF
IO = 400 to 10 mA Load Step
IO = 100 to 10 mA Load Step
t - Time - 2 ms/div
Figure 11.
10
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I O = 100 mA/div
VI = 3.6 V,
VO = 1.6 V
LOAD TRANSIENT RESPONSE
IN PFM MODE
V O = 10 mV/div - 1.6 V Offset
I O = 50 mA or 200 mA/div
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
VI = 3.6 V,
VO = 1.6 V
L = 0.9 mH, CO = 10 mF
PFM Operation
V O = 20 mV/div − 1.6 V Offset
IO = 10 to 100 mA Load Step
VI = 3.6 V,
VO = 1.6 V
V O = 10 mV/div − 1.6 V Offset
MODE/SYNC = HIGH
L = 0.9 mH, CO = 10 mF
I O = 50 mA or 200 mA/div
VI = 3.6 V,
VO = 1.6 V
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
V O = 10 mV/div − 1.6 V Offset
I O = 50 mA or 200 mA/div
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
t − Time − 50 ms/div
Figure 12.
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
IO = 10 to 400 mA Load Step
MODE/SYNC = HIGH
L = 0.9 mH, CO = 4.7 mF
IO = 10 to 100 mA Load Step
IO = 10 to 400 mA Load Step
t - Time - 2 ms/div
t - Time - 50 ms/div
Figure 13.
Figure 14.
MODE/SYNC = HIGH
L = 0.9 mH, CO = 4.7 mF
IO = 400 to 10 mA Load Step
IO = 100 to 10 mA Load Step
t - Time - 2 ms/div
Figure 15.
Copyright © 2004–2007, Texas Instruments Incorporated
IO = 100 mA/div
VI = 3.6 V,
VO = 1.6 V
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
VO = 20 mV/div - 1.6 V Offset
IO = 50 mA or 200 mA/div
LOAD TRANSIENT RESPONSE IN
PFM OPERATION
VI = 3.6 V,
VO = 1.6 V
L = 0.9 mH, CO = 4.7 mF
PFM Operation
VO = 20 mV/div - 1.6 V Offset
IO = 10 to 100 mA Load Step
VI = 3.6 V,
VO = 1.6 V
VO = 20 mV/div - 1.6 V Offset
MODE/SYNC = HIGH
L = 0.9 mH, CO = 4.7 mF
IO = 50 mA or 200 mA/div
VI = 3.6 V,
VO = 1.6 V
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
VO = 10 mV/div - 1.6 V Offset
IO = 50 mA or 200 mA/div
LOAD TRANSIENT RESPONSE IN
PWM OPERATION
t - Time - 50 ms/div
Figure 16.
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11
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
OUTPUT VOLTAGE
vs
LOAD CURRENT
1.628
REGULATED FEEDBACK VOLTAGE
vs
TEMPERATURE
406
VI = 3.6 V, VO = 1.6 V,
L = 2.2 mH
V(FB) - Regulated Feedback Voltage - mV
TPS62300
VO − Output Voltage − V
1.618
1.608
PWM Operation
1.598
1.588
PFM/PWM Operation
1.578
1
10
100
IO − Load Current − mA
404.5
404
403.5
403
VI = 2.7 V
402.5
402
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 85
TA - Ambient Temperature - 5C
Figure 17.
Figure 18.
QUIESCENT CURRENT
vs
INPUT VOLTAGE
OSCILLATOR FREQUENCY
vs
INPUT VOLTAGE
96
3.3
94
3.25
92
90
TA = 855C
TA = 255C
88
86
84
80
2.7
TA = −405C
3.2
TA = −405C
3.15
TA = 255C
3.1
TA = 855C
3.05
3
MODE/SYNC = HIGH
2.95
3
VI = 3.6 V
VI = 4.2 V
1000
82
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
VI − Input Voltage − V
Figure 19.
12
405
f s − Oscillator Frequency − MHz
I Q− Quiescent Current − µ A
1.568
0.1
405.5
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6
2.9
2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7
VI − Input Voltage − V
6
Figure 20.
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
P-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
DUTY CYCLE JITTER
700
IO = 320 mA
SW - 1 V/div
TRIGGER ON RISING EDGE
rDS(on) − Static Drain-Source On-Resistance − m Ω
VI = 3.6 V, VO = 1.6 V,
L = 0.9 mH, CO = 10 mF
MODE/SYNC = HIGH
TA = 855C
550
500
TA = 255C
450
400
350
300
TA = −405C
250
200
150
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 22.
N-CHANNEL rDS(ON)
vs
INPUT VOLTAGE
PWM OPERATION
I L − 200 mA/div
Figure 21.
550
500
TA = 855C
400
IO = 200 mA
5.5
350
TA = 255C
300
L = 0.9 mH, CO = 10 mF
250
TA = −405C
200
VI = 3.6 V, VO = 1.6 V
150
2.5
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 23.
Copyright © 2004–2007, Texas Instruments Incorporated
5.5
6
6
VO − 10 mV/div − 1.6 V Offset
450
600
SW − 2 V/div
rDS(on) − Static Drain-Source On-Resistance − mΩ
t - Time - 25 ns/div
650
t − Time − 200 ns/div
Figure 24.
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TPS62315, TPS62320, TPS62321
13
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
DYNAMIC VOLTAGE MANAGEMENT
L = 0.9 mH, CO = 10 mF
IO = 40 mA
V(ADJ) = 1 V
L = 0.9 mH, CO = 10 mF,
MODE/SYNC = LOW
RL = 270 W
t − Time − 20 ms/div
DYNAMIC VOLTAGE MANAGEMENT
START-UP
VO = 1.5 V
VI = 3.6 V,
VO = 1.6 V,
IO = 0 mA
VO − 1 V/div
VI = 3.6 V,
VO = 1 V / 1.5 V
EN − 2 V/div
Figure 26.
RL = 5 W
L = 0.9 mH, CO = 10 mF,
MODE/SYNC = HIGH
t − Time − 20 ms/div
Figure 27.
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VADJ − 2 V/div
V(ADJ) = 1 V
I L − 200 mA/div
VO = 1 V
ADJ − 500 mA/div
VO − 200 mV/div
VO = 1 V
Figure 25.
V(ADJ) = 0.67 V
I L − 500 mA/div
VO = 1.5 V
ADJ − 500 mA/div
VO − 200 mV/div
VI = 3.6 V, VO = 1.6 V
t − Time − 2 ms/div
14
VI = 3.6 V,
VO = 1 V / 1.5 V
V(ADJ) = 0.67 V
I L − 500 mA/div
VO − 20 mV/div − 1.6 V Offset
I L − 200 mA/div
POWER-SAVE MODE OPERATION
L = 2.2 mH, CO = 4.7 mF,
t − Time − 50 ms/div
Figure 28.
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
POWER DOWN (TPS62321)
L = 2.2 mH, CO = 4.7 mF,
EN − 2 V/div
VI = 3.6 V,
VO = 1.5 V,
IO = 0 mA
VO − 500 mV/div
V(ADJ) − 2 V/div
VO − 1 V/div
VI = 3.6 V,
VO = 1.6 V,
IO = 320 mA
I L − 200 mA/div
EN − 2 V/div
START-UP
L = 0.9 mH, CO = 10 mF
t − Time − 400 ms/div
t − Time − 50 ms/div
Figure 29.
Figure 30.
DETAILED DESCRIPTION
OPERATION
The TPS6230x, TPS6231x, and TPS6232x are synchronous step-down converters typically operating with a
3-MHz fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents,
the converter operates in power-save mode with pulse frequency modulation (PFM). The operating frequency is
set to 3 MHz and can be synchronized on-the-fly to an external oscillator.
During PWM operation, the converter uses a unique fast response, voltage mode, controller scheme with input
voltage feed-forward. This achieves best-in-class load and line response and allows the use of tiny inductors and
small ceramic input and output capacitors. At the beginning of each switching cycle, the P-channel MOSFET
switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the
switch.
The device integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. When the current in the N-channel MOSFET is above the
N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The current limit in the N-channel MOSFET is important for small duty-cycle operation when the current in the
inductor does not decrease because of the P-channel MOSFET current limit delay, or because of start-up
conditions where the output voltage is low.
Copyright © 2004–2007, Texas Instruments Incorporated
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15
TPS62300, TPS62301, TPS62302
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
POWER-SAVE MODE
With decreasing load current, the device automatically switches into pulse skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically, the switching losses are
minimized, and the device runs with a minimum quiescent current and maintaining high efficiency.
In power-save mode, the converter only operates when the output voltage trips below a set threshold voltage
(-1.5% VO(NOMINAL)). It ramps up the output voltage with several pulses and goes into power-save mode once the
output voltage exceeds the nominal output voltage. As a consequence, the average output voltage is slightly
lower than its nominal value in the power-save mode operation.
The output current at which the PFM/PWM transition occurs is approximated by Equation 1:
V
V *V
I
O
I
+ O
PFMńPWM
V
2
L
f sw
I
• IPFM/PWM : output current at which PFM/PWM transition occurs
• fSW : switching frequency (3-MHz typical)
• L : inductor value
(1)
VO(NOMINAL)
3-MHz Operation
Comp Low Thershold
−1.5% VO(NOMIAL)
Figure 31. Power-Save Mode Threshold
MODE SELECTION AND FREQUENCY SYNCHRONIZATION
The MODE/SYNC pin is a multipurpose pin which allows mode selection and frequency synchronization.
Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converter
operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
which maintains high efficiency over a wide load current range.
Pulling the MODE/SYNC pin high forces the converter to operate in the PWM mode even at light load currents.
The advantage is that the converter operates with a fixed frequency that allows simple filtering of the switching
frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the power-save
mode during light loads. For additional flexibility, it is possible to switch from power-save mode to forced PWM
mode during operation. This allows efficient power management by adjusting the operation of the converter to
the specific system requirements.
The TPS6230x, TPS6231x, and TPS6232x can also be synchronized to an external 3-MHz clock signal by the
MODE/SYNC pin. During synchronization, the mode is set to fixed-frequency operation and the P-channel
MOSFET turnon is synchronized to the falling edge of the external clock. This creates the ability for multiple
converters to be connected together in a master-slave configuration for frequency matching of the converters
(see the application section for more details, Figure 37).
SOFT START
The TPS6230x, TPS6231x, and TPS6232x have an internal soft-start circuit that limits the inrush current during
start-up. This prevents possible input voltage drops when a battery or a high-impedance power source is
connected to the input of the converter. The soft start is implemented as a digital circuit increasing the switch
current in steps of typically 195 mA, 390 mA, 585 mA, and the typical switch current limit of 780 mA.
The current limit transitions to the next step every 256 clocks (≈88µs). To be able to switch from 390 mA to 585
mA current limit step, the output voltage needs to be higher than 0.5 x VO(NOM), otherwise, the parts continues to
operate at the 390-mA current limit. This mechanism is used to limit the output current under short-circuit
conditions. Therefore, the start-up time mainly depends on the output capacitor and load current.
16
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TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
LOW-DROPOUT OPERATION 100% DUTY CYCLE
In 100% duty cycle mode, the TPS6230x, TPS6231x, and TPS6232x offer a low input-to-output voltage
difference. In this mode, the P-channel MOSFET is constantly turned on. This is particularly useful in
battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain regulation, depending on the load current and output
voltage, can be calculated as:
• VI(MIN) = VO(MAX) + IO(MAX) x (rDS(on) MAX + RL)
• IO(MAX) : Maximum output current
• rDS(on) MAX : Maximum P-channel switch rDS(on)
• RL : DC resistance of the inductor
• VO(MAX) : nominal output voltage plus maximum output voltage tolerance
ENABLE
The device starts operation when EN is set high and starts up with the soft start as previously described.
Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.1 µA. In
this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected,
and the entire internal-control circuitry is switched off. When an output voltage is present during shutdown mode,
which can be caused by an external voltage source or super capacitor, the reverse leakage is specified under
electrical characteristics. For proper operation, the EN pin must be terminated and must not be left floating.
In addition, the TPS6232x devices integrate a resistor, typically 35 Ω, to actively discharge the output capacitor
when the device turns off. The required time to discharge the output capacitor at VO depends on load current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the
converter from turning on the switch or rectifier MOSFET under undefined conditions.
The TPS6231x devices have a UVLO threshold set to 2 V (typical). Fully functional operation is permitted down
to 2.4 V input voltage. EN is set low for input voltages lower than 2.4 V to avoid the possibility of misoperation.
TPS6231x devices are to be considered where the user requires direct control of the turn-off sequence as part of
a larger power management system.
SHORT-CIRCUIT PROTECTION
As soon as the output voltage falls below 50% of the nominal output voltage, the converter current limit is
reduced by 50% of the nominal value. Because the short-circuit protection is enabled during start-up, the device
does not deliver more than half of its nominal current limit until the output voltage exceeds 50% of the nominal
output voltage. This needs to be considered when a load acting as a current sink is connected to the output of
the converter.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds typically 150°C, the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature falls below typically 130°C again.
Copyright © 2004–2007, Texas Instruments Incorporated
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17
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
APPLICATION INFORMATION
ADJUSTABLE OUTPUT VOLTAGE
When the adjustable output voltage versions, TPS62300 or TPS62320, are used, the output voltage is set by the
external resistor divider (see Figure 32).
The output voltage is calculated as:
V
O
+ 1.5
V
ǒ1 ) R1
Ǔ with an internal reference voltage Vref typical + 0.4 V
R2
ref
(2)
To keep the operating quiescent current to a minimum, it is recommended that R2 be set in the range of 75 kΩ to
130 kΩ. Route the FB line away from noise sources, such as the inductor or the SW line.
TPS62300
L1
SW 10
VOUT 6
3 EN
4 R1
ADJ
8 MODE/SYNC
5
FB
7 AGND
PGND 9
1 VIN
2 AVIN
2.7 V . . 6 V
VI
C1
4.7 mF
A
A
C2
VO
1.6 V/500 mA
4.7 mF
R2
A
Figure 32. Adjustable Output Voltage Version
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The TPS6230x, TPS6231x, and TPS6232x series of step-down converters have internal loop compensation.
Therefore, the external L-C filter must be selected to work with the internal compensation.
The device has been designed to operate with inductance values between a minimum of 0.7 µH and maximum of
6.2 µH. The internal compensation is optimized to operate with an output filter of L = 1 µH and CO = 10 µF. Such
an output filter has its corner frequency at:
1
1
ƒc +
+
+ 50.3 kHz
2p L C
2p Ǹ1 mH 10 mF
O
(3)
Ǹ
Operation with a higher corner frequency (e.g., L = 1 µH, CO = 4.7 µF) is possible. However, it is recommended
the loop stability be checked in detail. Selecting a larger output capacitor value (e.g., 22 µF) is less critical
because the corner frequency moves to lower frequencies with fewer stability problems. The possible output filter
combinations are listed in Table 1.
Regardless of the inductance value, operation is recommended with 10-µF output capacitor in applications with
high-load transients (e.g., ≥ 1600 mA/µs).
Table 1. Output Filter Combinations
INDUCTANCE (L)
OUTPUT CAPACITANCE (CO)
1 µH
≥ 4.7 µF (ceramic capacitor)
2.2 µH
≥ 2.2 µF (ceramic capacitor)
The inductor value also has an impact on the pulse skipping operation. The transition into power-save mode
begins when the valley inductor current goes below a level set internally. Lower inductor values result in higher
ripple current which occurs at lower load currents. This results in a dip in efficiency at light load operations.
18
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TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
INDUCTOR SELECTION
Even though the inductor does not influence the operating frequency, the inductor value has a direct effect on the
ripple current. The selected inductor has to be rated for its dc resistance and saturation current. The inductor
ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO.
V
V *V
DI
I
O
DI + O
DI
+I
) L
L
L(MAX)
O(MAX)
2
V
L ƒ sw
I
(4)
with: fSW = switching frequency (3 MHz typical)
L = inductor value
ΔIL = peak-to-peak inductor ripple current
IL(MAX) = maximum inductor current
Normally, it is advisable to operate with a ripple of less than 30% of the average output current. Accepting larger
values of ripple current allows the use of low inductances, but results in higher output voltage ripple, greater core
losses, and lower output current capability.
The total losses of the coil consist of both the losses in the DC resistance (R(DC)) and the following
frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
The following inductor series from different suppliers have been used with the TPS6230x, TPS6231x, and
TPS6232x converters.
Table 2. List of Inductors
MANUFACTURER
SERIES
DIMENSIONS
FDK
MIPW3226
3.2 x 2.6 x 1 = 8.32 mm3
MIPSA2520
2.5 x 2.0 x 1.2 = 6 mm3
LQM2HP
2.5 x 2.0 x 1.2 = 6 mm3
LQ CB2016
2 x 1.6 x 1.6 = 5.12 mm3
LQ CB2012
2 x 1.2 x 1.2 = 2.88 mm3
LQ CBL2012
2 x 1.2 x 1 = 2.40 mm3
TDK
VLF3010AT
2.8 x 2.6 x 1 = 7.28 mm3
Coilcraft
LPS3010
3.3 x 3.3 x 1 = 10.89 mm3
JFE
32R1560
3.2 x 2.5 x 0.6 = 4.8 mm3
Murata
Taiyo Yuden
OUTPUT CAPACITOR SELECTION
The advanced fast-response voltage mode control scheme of the TPS6230x, TPS6231x, and TPS6232x allows
the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple
and are recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric
capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.
At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the
voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the
output capacitor:
DV
O
V
+ O
V
I
V *V
I
O
L ƒ sw
ǒ
8
1
C
O
ƒsw
Ǔ
) ESR
, maximum for high V
I
(5)
At light loads, the device operates in power-save mode and the output voltage ripple is independent of the output
capacitor value. The output voltage ripple is set by the internal comparator thresholds and propagation delays.
The typical output voltage ripple is 1.5% of the nominal output voltage VO.
Copyright © 2004–2007, Texas Instruments Incorporated
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TPS62315, TPS62320, TPS62321
19
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
INPUT CAPACITOR SELECTION
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required to prevent large voltage transients that can cause misbehavior of the device or interferences with other
circuits in the system. For most applications, a 2.2-µF or 4.7-µF capacitor is sufficient.
Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce
ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even
damage the part.
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VO(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR
is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error
signal used by the regulator to return VO to its steady-state value.
During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
PROGRAMMING THE OUTPUT VOLTAGE WITH A DAC
On TPS62300 and TPS62320 devices, the output voltage can be dynamically programmed to any voltage
between 0.6 V and VI (or 5.4 V whichever is lower) with an external DAC driving the ADJ and FB pins (see
Figure 33). The output voltage is then equal to A(PT) x V(DAC) with a Power Train amplification A(PT) typical = 1.5.
When the output voltage is driven low, the converter reduces its output quickly in forced PWM mode, boosting
the output energy back to the input. If the input is not connected to a low-impedance source capable of absorbing
the energy, the input voltage can rise above the absolute maximum voltage of the part and get damaged. The
faster VO is commanded low, the higher is the voltage spike at the input.
For best results, ramp the ADJ/FB signal as slow as the application allows. To avoid over-slew of the regulation
loop of the converter, avoid abrupt changes in output voltage of > 300 mV/µs (depending on VI , output voltage
step size and L/C combination). If ramp control is unavailable, an RC filter can be inserted between the DAC
output and ADJ/FB pins to slow down the control signal.
TPS62300
1 VIN
2 AVIN
VI
CI
SW 10
VOUT 6
VO = 1.5 x V(DAC)
L
CO
3 EN
ADJ 4
8 MODE/SYNC FB 5
7 AGND
A
PGND 9
RF
CF
V(DAC)
10 kW
A
A
Figure 33. Filtering the DAC Voltage
20
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6230x, TPS6231x, and TPS6232x devices demand careful attention to PCB layout. Care must be taken in
board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor
line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance,
impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold on
Figure 34.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (VOUT) should be connected right to the output capacitor and routed away from
noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring
connected to the reference ground. The voltage setting resistive divider should be placed as close as possible to
the AGND pin of the IC.
TPS62300
1 VIN
SW
2 AVIN
VOUT
3 EN
ADJ
8 MODE/SYNC FB
VI
C1
7 AGND
10
L1
VO
6
C2
4 R1
5
PGND 9
R2
Figure 34. Layout Diagram
GND
VO
VO sense signal
VI
EN
Figure 35. Suggested QFN Layout (Top)
Copyright © 2004–2007, Texas Instruments Incorporated
MODE / SYNC
GND
Figure 36. Suggested QFN Layout (Bottom)
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TPS62315, TPS62320, TPS62321
21
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
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SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS6230x, TPS6231x, and TPS6232x devices is
125°C. The thermal resistance of the 8-pin CSP package (YZD, YZ and YED) is RθJA = 250°C/W. Specified
regulator operation is specified to a maximum ambient temperature TA of 85°C. Therefore, the maximum power
dissipation is about 160 mW. More power can be dissipated if the maximum ambient temperature of the
application is lower, or if the PowerPAD™ package (DRC) is used.
T
*T
J(MAX)
A
P
+
+ 125°C * 85°C + 160 mW
D(MAX)
R
250°CńW
qJA
(6)
CHIP SCALE PACKAGE DIMENSIONS
The TPS6230x, TPS6231x, and TPS6232x are also available in an 8-bump chip scale package (YZD, YZ
NanoFree™ and YED, NanoStar™). The package dimensions are given as:
• D = 1.970 ±0.05 mm
• E = 0.970 ±0.05 mm
22
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
APPLICATION EXAMPLES
TPS62303YZD
A2
2.7 V − 6 V
C
V IN
B2
IN
10 µF
C1
A1
VIN
VOUT
EN
SW
MODE/SYNC
ADJ
FB
GND
D1
L1
B1
V OUT
C
C2
1
Ch1
Ch2
1.8 V / 500 mA
10 µF
D2
Ch4
TPS62304YZD
A2
B2
C1
1G08
A1
Low: None Synchronized Operation
PFM/PWM Automatic Switch
High: Synchronized Operation
Forced 3 MHz Fixed Frequency Operation
VIN
SW
EN
VOUT
MODE/SYNC
ADJ
FB
GND
B1
L2
V
C2
D1
OUT
1.2 V / 500 mA
10 µF
Ch3
C2
Ch1: SW (1.8-V Output), Ch2: IL1
Ch3: SW (1.2-V Output), Ch4: IL2
D2
List of Components:
L1, L2 = Taiyo Yuden LQ CB2016
CIN, C1, C2, = X5R/X7R Ceramic Capacitor
Figure 37. Dual, Out-of-Phase, 3-MHz, 500-mA Step-Down Regulator
Features Less Than 50-mm2 Total Solution Size
EN
22 nF
Fast Start−Up LDO
10 kΩ
VIN
2.2 MΩ
VOUT
GND
TPS62300YZD
2.7 V . . 6 V
A2
C
V IN
VOUT(LDO) = 0.98 x VOUT(NOM)
EN
EN
IN
10 µF
B2
VIN
VOUT
EN
SW
VOUT
B1
C1 MODE/SYNC ADJ
C2
A1 GND
D2
FB
VO
D1
L1
1 µH
C1
1.8 V / 500 mA
IL1
10 µF
VI = 2.8 V,
RL = 10 W
Ch1: VO
Ch3: Inductor Current: IL1
Ch3: EN − External Control Signal
List of Components:
L1 = Taiyo Yuden LQ CB2016
CIN, C1 = X5R/X7R Ceramic Capacitor
Figure 38. Speed-Up Circuitry for Fast Turnon Time
Copyright © 2004–2007, Texas Instruments Incorporated
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
23
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
www.ti.com
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
TPS62300
VIN
VIN
1.8
VOUT
L1
CI
EN
10 µF
SW
R1
MODE/SYNC
2.2 µH
ADJ
9.5 kΩ
GND
2.85 V
FB
R2
8.2 kΩ
DAC6571
VDD
I2C I/F
SDA
SCL
VDAC
1.6
VOUT
C1
4.7 µF
V O− Output Voltage − V
2.7 V − 6 V
Default Voltage =
R1
1.5 x Vref x 1+
R2
( )
1.4
1.2
1
0.8
0.6
0.4
DAC Control Range
VO = 1.5 x 0.98 x V(DAC)
0.2
A0
GND
0
0
0.2
0.4 0.6
0.8
1
1.2
V(DAC) − Control Voltage − V
1.4
List of Components:
L1 = Wuerth Elektronik WE-TPC XS
CI , C1, = X5R/X7R Ceramic Capacitor
Figure 39. Dynamic Voltage Management Using I2C I/F
24
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Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS62300DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMN
Samples
TPS62301DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMO
Samples
TPS62302DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMQ
Samples
TPS62303DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMR
Samples
TPS62304DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMS
Samples
TPS62305DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ANU
Samples
TPS62320DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMX
Samples
TPS62321DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
AMY
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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