TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
3A Processor Supply with I2C Compatible Interface and Remote Sense
Check for Samples: TPS62360, TPS62361B, TPS62362, TPS62363
FEATURES
DESCRIPTION
•
•
The TPS6236x are a family of high-frequency
synchronous step down dc-dc converter optimized for
battery-powered portable applications for a small
solution size. With an input voltage range of 2.5V to
5.5V, common battery technologies are supported.
The device provides up to 3A peak load current,
operating at 2.5MHz typical switching frequency.
1
2
•
•
•
•
•
•
3A Peak Output Current
Highest Efficiency:
– Low RDS,on Switch and Active Rectifier
– Power Save Mode for Light Loads
I2C High Speed Compatible Interface
Programmable Output Voltage for Digital
Voltage Scaling
– TPS62360/62: 0.77V to 1.4V, 10mV Steps
– TPS62361B/63: 0.5V to 1.77V, 10mV Steps
Excellent DC/AC Output Voltage Regulation
– Differential Load Sensing
– Precise DC Output Voltage Accuracy
– DCS-Control™ Architecture for Fast and
Precise Transient Regulation
Multiple Robust Operation/Protection
Features:
– Soft Start
– Programmable Slew Rate at Voltage
Transition
– Over Temperature Protection
– Input Under Voltage Detection and Lockout
Available in 16-Bump, 2mm x 2mm NanoFree™
Package
Low External Device Count: < 25mm2 Solution
Size
•
•
•
Dynamic Voltage Scale Compliant Processors
and DSPs, Memory
SmartReflex™ Compliant Power Supply
Cell Phones, Smart Phones, Feature Phones
Tablets, Netbooks, Clamshells
2.5V .. 5.5V
TPS6236x
VIN
AVIN
EN
The TPS6236x devices offer high efficiency step
down conversion. The area of highest efficiency is
extended towards low output currents to increase the
efficiency while the processor is operating in retention
mode, as well as towards highest output currents
increasing the battery on-time.
The 2mm x 2mm package and the low number of
required external components lead to a tiny solution
size of less than 25mm2.
1mm
0.47uH / 1µH
COUT
SENSE+
0.1µF
The devices focus on a high output voltage accuracy.
The differential sensing and the DCS-Control™
architecture achieve precise static and dynamic,
transient output voltage regulation.
SW
SW
10µF 0.1µF
VDD
SCL
SDA
The TPS6236x supports low-voltage DSPs and
processor cores in smart-phones and handheld
computers including latest submicron processes.
Dedicated hardware input pins allow simple
transitions to performance operating points and
retention modes of processors.
The robust architecture and multiple safety features
allow perfect system integration.
APPLICATIONS
•
The devices convert to an output voltage range of
0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V
(TPS62361B/63), programmable via I2C interface in
10mV steps. Dedicated inputs allow fast voltage
transition to address processor performance
operating points.
LOAD
SENSE-
PGND
PGND
VSEL0
VSEL1 AGND PGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DCS-Control, NanoFree, SmartReflex are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
(2)
DEVICE SPECIFIC FEATURES (1)
PART NUMBER
PACKAGE MARKING
PACKAGE
Output Voltage Range
Output Voltage Presets
TPS62360 (2)
See PACKAGE
SUMMARY Section
CSP-16
VOUT = 0.77V to 1.4V, 10mV Steps
1.40V, 1.00V, 1.40V, 1.10V
TPS62361B (2)
See PACKAGE
SUMMARY Section
CSP-16
VOUT = 0.5V to 1.77V, 10mV Steps
0.96V, 1.40V, 1.16V, 1.16V
TPS62362 (2)
See PACKAGE
SUMMARY Section
CSP-16
VOUT = 0.77V to 1.4V, 10mV Steps
1.23V, 1.00V, 1.20V, 1.10V
TPS62363 (2)
See PACKAGE
SUMMARY Section
CSP-16
VOUT = 0.5V to 1.77V, 10mV Steps
1.20V, 1.36V, 1.50V, 1.00V
Contact the factory to check availability of other output voltage or feature versions.
The YZH package is available in tape and reel. Add R suffix (e.g. TPS62360YZHR) to order quantities of 3000 parts per reel, T suffix for
250 parts per reel (e.g. TPS62360YZHT). For the most current package and ordering information, see the Package Option Addendum at
the end of this document, or visit the device product folder on ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Voltage range (2)
Continuous RMS VIN / SW current per Pin
Temperature range
ESD rating (4)
MAX
VIN, AVIN, SW pin
–0.3
7
V
EN, VSEL0, VSEL1, SENSE+
–0.3
(VAVIN+0.3V)
V
SENSE–
–0.3
0.3
V
SCL, SDA
–0.3
(VDD+0.3V)
V
VDD
–0.3
3.6
V
1275
mA
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
Machine model
200
V
Charge device model
500
V
2
kV
(3)
Human body model
(1)
(2)
(3)
(4)
2
UNIT
MIN
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In order to be consistent with the TI reliability requirement for the silicon chips (100K Power-On-Hours at 105°C junction temperature),
the current should not continuously exceed 1275mA in the VIN pin and 2550mA in the SW pins so as to prevent electromigration failure
in the solder. See THERMAL AND DEVICE LIFE TIME INFORMATION.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
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TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
THERMAL INFORMATION
TPS6236x
THERMAL METRIC (1)
YZH
UNITS
16 PINS
Junction-to-ambient thermal resistance (2)
θJA
94.8
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
60
ψJT
Junction-to-top characterization parameter (5)
3.2
ψJB
Junction-to-board characterization parameter (6)
57
θJCbot
Junction-to-case (bottom) thermal resistance (7)
n/a
(1)
(2)
(3)
(4)
(5)
(6)
(7)
25
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
IOUT ≤ 2.5A
2.5
5.5
V
IOUT > 2.5A
3
5.5
V
VIN
Input voltage range, VIN
IOUT,avg
Continuous output current (1)
trf
Rising and falling signal transition time at EN, VSELx
TA
Operating ambient temperature (2)
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
(1)
(2)
2.5
30
A
mV/µs
The TPS6236x device is designed to provide 3A according to typical application processor load profiles. Drawing more than 2.5A
permanently might impact the device life time. See THERMAL AND DEVICE LIFE TIME INFORMATION for details.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max))
ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
VIN
Input voltage range at VIN, AVIN
VDD
I2C and registers supply voltage range
ISD(AVIN)
Shutdown current into AVIN
ISD(VIN)
ISD(VDD)
Shutdown current into VIN
Shutdown current into VDD
Copyright © 2011–2012, Texas Instruments Incorporated
2.5
5.5
V
1.15
3.6
V
EN = LOW, VDD = 0V
EN = LOW,
VDD = 0V
0.65
5
µA
TA = 25°C
0.5
1
µA
TA = 85°C
1
3
µA
2
EN = LOW, I C bus idle
0.01
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µA
3
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
56
µA
Forced PWM
mode
(Test Mode)
180
µA
Input voltage falling, EN = High
2.3
EN = HIGH,
IOUT = 0mA,
not switching
PFM mode
IQ
Operating quiescent current into (AVIN
+ VIN)
VUVLO
Under voltage lock out at AVIN
Input voltage rising, EN = Low
1.3
V
VUVLO,HYST(AVIN)
Under voltage lock out hysteresis at
AVIN
Input voltage rising
110
mV
VDD,UVLO
Under voltage lock out at VDD
Input voltage falling
VUVLO,HYST(VDD)
Under voltage lock out hysteresis at
VDD
Input voltage rising
IVDD
Input current at VDD
0.7
I2C not active
2
I C active (r/w)
0.92
2.45
1.1
V
V
50
mV
0
µA
0.02
1
mA
LOGIC INTERFACE
VIH
High-level input voltage at EN, VSEL0,
VSEL1
VIL
Low-level input voltage at EN, VSEL0,
VSEL1
VIH,I2C
High-level input voltage at SCL, SDA
VIL,I2C
Low-level input voltage at SCL, SDA
ILKG
Logic input leakage current at EN,
VSEL0, VSEL1, SDA, SCL
Internal pulldown resistors
disabled
0.05
µA
RPD
Pull down resistance at EN, VSEL0,
VSEL1
Internal pulldown resistors
enabled
300
kΩ
I2C clock frequency
1.2
V
0.4
0.7x VDD
V
V
0.3x VDD
V
Fast mode
400
kHz
High speed mode
3.4
MHz
POWER SWITCH
High side MOSFET switch
VIN = 3.6V
25
44
75
mΩ
Low side MOSFET switch
VIN = 3.6V
25
32
50
mΩ
High side MOSFET forward current limit VIN = 3.6V
3.0
3.6
4.3
A
Low side MOSFET forward current limit
VIN = 3.6V
2.6
3
3.8
A
Low side MOSFET negative current
limit
VIN = 3.6V, PWM mode
2.2
2.5
2.9
A
fSW
Nominal switching frequency
PWM mode
2.5
MHz
TJEW
Die temperature early warning
120
°C
TJSD
Thermal shutdown
150
°C
TJSD,HYST
Thermal shutdown hysteresis
20
°C
tON,min
Minimum on time
120
ns
RDS(on)
ILIMF
OUTPUT
VOUT
Output voltage range
Output voltage accuracy
4
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10mV
increments
TPS62360/62
0.77
1.4
0.5
1.77
TPS62360/62:
VIN = 2.5V ..
5.5V
VOUT = 0.77V ..
1.4V
No load, Forced
PWM,
VOUT = [0.77V,
1.3V]
TJ = 85°C
-0.5%
+0.5%
TPS62361B/63:
VIN = 2.7V ..
5.5V
VOUT = 0.5V ..
1.77V
No load, Forced
PWM,
TJ = -40 ..
150°C
-1%
TPS62361B/63
±0.5%
V
+1%
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit
of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C.
PARAMETER
TEST CONDITIONS
Line regulation
IOUT = 1A, forced PWM
Load regulation
VOUT = 1.2V, forced PWM
tStart
Start-up time
Time from active EN to
VOUT = 1.4V,
COUT < 100µF, RMP[2:0] = 000,
IOUT = 0mA
RSense
Input resistance between Sense+,
Sense–
Ramp timer
Copyright © 2011–2012, Texas Instruments Incorporated
MIN
TYP
MAX
UNIT
< 0.1
%/V
< 0.05
%/A
1
ms
2.2
RMP[2:0] = 000
32
RMP[2:0] = 001
16
RMP[2:0] = 010
8
RMP[2:0] = 011
4
RMP[2:0] = 100
2
RMP[2:0] = 101
1
RMP[2:0] = 110
0.5
RMP[2:0] = 111
0.25
MΩ
mV/µs
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5
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
I2C INTERFACE TIMING REQUIREMENTS (1) (2)
PARAMETER
f(SCL)
TEST CONDITIONS
SCL clock frequency
Bus free time between a STOP and
START condition
tBUF
MAX
UNIT
Standard mode
MIN
100
kHz
Fast mode
400
kHz
High-speed mode (write operation), CB – 100 pF
max
3.4
MHz
High-speed mode (read operation), CB – 100 pF
max
3.4
MHz
High-speed mode (write operation), CB – 400 pF
max
1.7
MHz
High-speed mode (read operation), CB – 400 pF
max
1.7
MHz
Standard mode
4.7
μs
Fast mode
1.3
μs
4
μs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
4.7
μs
Fast mode
1.3
μs
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
4
μs
Standard mode
tHD, tSTA
tLOW
Hold time (repeated) START condition
Low period of the SCL clock
Standard mode
tHIGH
High period of the SCL clock
tSU, tSTA
tSU, tDAT
Setup time for a repeated START
condition
Data setup time
Fast mode
600
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
μs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
High-speed mode
tHD, tDAT
tRCL
Data hold time
Rise time of SCL signal
tRCL1
Rise time of SCL signal after a repeated
START condition and after an
acknowledge bit
10
0
3.45
μs
Fast mode
0
0.9
μs
High-speed mode, CB – 100 pF max
0
70
ns
High-speed mode, CB – 400 pF max
0
150
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
10
80
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
tFCL
(1)
(2)
6
Fall time of SCL signal
ns
Standard mode
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
High-speed mode, CB – 100 pF max
10
40
ns
High-speed mode, CB – 400 pF max
20
80
ns
S/M = standard mode; F/M = fast mode
Specified by design. Not tested in production.
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Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
I2C INTERFACE TIMING REQUIREMENTS(1)(2) (continued)
PARAMETER
tRDA
TEST CONDITIONS
Rise time of SDA signal
MIN
MAX
UNIT
Standard mode
20 + 0.1 CB
1000
ns
Fast mode
20 + 0.1 CB
300
ns
10
80
ns
High-speed mode, CB – 100 pF max
High-speed mode, CB – 400 pF max
tFDA
Fall time of SDA signal
20
160
ns
Standard mode
20 + 0.1 CB
300
ns
Fast mode
20 + 0.1 CB
300
ns
ns
High-speed mode, CB – 100 pF max
10
80
High-speed mode, CB – 400 pF max
20
160
tSU, tSTO
Setup time for STOP condition
CB
ns
4
μs
Fast mode
600
ns
High-speed mode
160
Standard mode
Capacitive load for SDA and SCL
ns
400
pF
I2C TIMING DIAGRAMS
SDA
tsu;DAT
tf
tr
tLOW
tf
thd;STA
thd;STA
tBUF
tr
SCL
thd;STA
tsu;STO
thd;DAT
HIGH
Sr
S
P
S
Figure 1. Serial Interface Timing for F/S Mode
tfDA
Sr P
trDA
SDAH
thd;DAT
tsu;STA
tsu;DAT
thd;STA
tsu;STO
SCLH
Sr
tfCL
tfCL1
See Note A
tHIGH
tLOW
tfCL
tLOW
trCL1
tHIGH
See Note A
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
Figure 2. Serial Interface Timing for H/S Mode
Copyright © 2011–2012, Texas Instruments Incorporated
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
DEVICE INFORMATION
PIN ASSIGNMENTS
(TOP VIEW)
(BOTTOM VIEW)
AVIN
AGND
VSEL1
VIN
A1
A2
A3
A4
SENSE+
EN
SW
SW
B1
B2
B3
B4
PGND
PGND
SENSE- VSEL0
C1
C2
C3
C4
VDD
SDA
SCL
PGND
D1
D2
D3
D4
A4
A3
A2
A1
B4
B3
B2
B1
C4
C3
C2
C1
D4
D3
D2
D1
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
AVIN
A1
I
Analog Supply Voltage Input.
AGND
A2
–
Analog Ground Connection.
EN
B2
I
Device Enable Logic Input. Logic HIGH enables the device, logic LOW disables the device and turns it into
shutdown. The pin must be terminated to either HIGH or LOW if the internal pull down resistor is deactivated.
VDD
D1
I
I2C Logic and Registers supply voltage. For resetting the internal registers, this connection must be pulled below
its UVLO level.
SCL
D3
I/O
I2C clock signal.
SDA
D2
I/O
I2C data signal.
VSEL0
C2
I
VSEL1
A3
I
B3
–
SW
B4
Output Settings Selection Logic Inputs. Predefined register settings can be chosen for setting output voltage and
mode. The pins must be terminated to logic HIGH or LOW if the internal pull down resistors are deactivated.
Inductor connection
SENSE+
B1
I
Positive Output Voltage Remote Sense. Must be connected closest to the load supply node.
SENSE–
C1
I
Negative Output Voltage Remote Sense. Must be connected closest to the load ground node.
A4
I
Power Supply Voltage Input.
C3
–
VIN
PGND
C4
Power Ground Connection.
D4
8
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TPS62362, TPS62363
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
ramp
Softstart
AVIN
AGND
direct control
&
compensation
comparator
error
amplifier
Analog
Circuit
Supply
Differential
Sense
SENSE+
SENSE-
Thermal
Shutdown
DCS-CONTROL
TM
REF
EN
VDD
SCL
RDISCHARGE
I2C
Interface
High Side
Current Limit
VIN
SDA
Bandgap
Control
Logic
High Side
P-MOS
Gate
Driver
2
SW
Under
Voltage
Shutdown
Low Side
N-MOS
PGND
3
VSEL0
Low Side
Current Limit
VSEL1
Copyright © 2011–2012, Texas Instruments Incorporated
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs. Output Current (Power Save and Forced
PWM Mode)
η
Efficiency
VOUT = 1.1V
Figure 6
VOUT = 1.0V
Figure 7
VOUT = 0.9V
Figure 8
Figure 9
IOUT = 1000mA
Figure 11
IOUT = 100mA
Figure 12
IOUT = 10mA
Figure 13
VOUT = 1.5V, TA =
25°C
Figure 14
VOUT = 1.2V, TA =
25°C
Figure 15
VOUT = 0.9V, TA =
25°C
Figure 16
VOUT = 0.6V, TA =
25°C
Figure 17
VOUT = 0.5V, IOUT =
0mA
Figure 18
VOUT = 1.5V, IOUT =
0mA
Figure 19
VOUT = 0.5V, IOUT =
1000mA
Figure 20
VOUT = 1.5V, IOUT =
1000mA
Figure 21
IOUT = 10mA
Figure 22
IOUT = 200mA
Figure 23
IOUT = 1000mA
Figure 24
IOUT = 3000mA
Figure 25
IOUT = 0mA
Figure 26
IOUT = 1000mA
Figure 27
IOUT = 5mA to 200mA
Figure 28
IOUT = 5mA to 1000mA
Figure 29
IOUT = 200mA to
1000mA
Figure 30
IOUT = 1000mA to
3000mA
Figure 31
Line Transient Response
VIN = 3.2 to 4.2V
Figure 32
Shutdown Current at AVIN and
VIN
TA = [-40°C, 25°C,
125°C]
Figure 33
TA = [-40°C, 25°C,
125°C],
auto PFM/PWM
Figure 34
TA = [-40°C, 25°C,
125°C]
forced PWM
Figure 35
VOUT = 1.2V
Figure 36
vs. Output Current (Power Save and Forced
PWM Mode)
Startup
Into Load
Switching Wave forms
Output Voltage Ramp Control
Transition 0.6V .. 1.5V
Load Transient Response
Quiescent Current
vs. Input Voltage
vs. Input Voltage
fSW
Switching Frequency
vs. Output Current
ILIM
Current Limit
vs. Input Voltage
10
Figure 5
Figure 10
Into No Load
IQ
Figure 4
VOUT = 1.2V
IOUT = 3000mA
DC Output Voltage
ISD(VIN),
ISD(AVIN)
Figure 3
VOUT = 1.4V
VOUT = 0.6V
vs. Input Voltage (Power Save and Forced PWM
Mode)
VO
VOUT = 1.5V
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Figure 37
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 1.4V
100
100
90
90
80
80
70
70
60
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 1.5V
TPS62361B
VOUT = 1.5V
TA = 25°C
50
40
30
10
0
1m
10m
100m
Output Current (A)
1
TPS6236x
VOUT = 1.4V
TA = 25°C
50
40
30
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
60
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
10
0
1m
3
10m
100m
Output Current (A)
1
G002
Figure 3.
Figure 4.
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 1.2V
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 1.1V
100
100
90
90
80
80
70
70
60
Efficiency (%)
Efficiency (%)
G001
TPS6236x
VOUT = 1.2V
TA = 25°C
50
40
30
20
10
0
1m
10m
100m
Output Current (A)
1
60
TPS6236x
VOUT = 1.1V
TA = 25°C
50
40
30
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
10
3
0
1m
10m
100m
Output Current (A)
1
G003
Figure 5.
Copyright © 2011–2012, Texas Instruments Incorporated
3
3
G004
Figure 6.
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
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TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 0.9V
100
100
90
90
80
80
70
70
60
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 1.0V
TPS6236x
VOUT = 1.0V
TA = 25°C
50
40
30
10
0
1m
10m
100m
Output Current (A)
1
TPS6236x
VOUT = 0.9V
TA = 25°C
50
40
30
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
60
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
10
0
1m
3
10m
100m
Output Current (A)
1
3
G006
Figure 8.
EFFICIENCY
vs
OUTPUT CURRENT
VOUT = 0.6V
EFFICIENCY
vs
INPUT VOLTAGE
IOUT = 3A
100
100
90
90
80
80
70
70
60
Efficiency (%)
Efficiency (%)
G005
Figure 7.
TPS62361B
VOUT = 0.6V
TA = 25°C
50
40
30
10
0
1m
10m
100m
Output Current (A)
1
50
40
30
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
20
60
20
10
3
0
2.5
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 3A
TA = 25°C
3.0
3.5
4.0
4.5
Input Voltage (V)
G007
Figure 9.
12
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5.0
5.5
G008
Figure 10.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
EFFICIENCY
vs
INPUT VOLTAGE
IOUT = 100mA
100
100
90
90
80
80
70
70
60
60
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
INPUT VOLTAGE
IOUT = 1A
50
40
30
0
2.5
40
30
20
10
50
Forced PWM, VOUT = 1.0V
Forced PWM, VOUT = 1.1V
Forced PWM, VOUT = 1.4V
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
20
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
TPS6236x
IOUT = 1A
TA = 25°C
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
10
0
2.5
5.5
TPS6236x
IOUT = 100mA
TA = 25°C
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
G009
Figure 12.
EFFICIENCY
vs
INPUT VOLTAGE
IOUT = 10mA
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOUT = 1.5V
100
1.55
90
1.54
80
1.53
DC Output Voltage (V)
70
Efficiency (%)
G010
Figure 11.
Forced PWM, VOUT = 1.0V
Forced PWM, VOUT = 1.1V
Forced PWM, VOUT = 1.4V
Auto PFM/PWM, VOUT = 1.0V
Auto PFM/PWM, VOUT = 1.1V
Auto PFM/PWM, VOUT = 1.4V
60
50
40
1.52
1.51
1.50
1.49
30
1.48
20
1.47
10
0
2.5
TPS6236x
IOUT = 10mA
TA = 25°C
3.0
TPS62361B
VOUT = 1.5V
TA = 25°C
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
1.46
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
1.45
1m
10m
100m
Output Current (A)
1
G011
Figure 13.
Copyright © 2011–2012, Texas Instruments Incorporated
3
G012
Figure 14.
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
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TYPICAL CHARACTERISTICS (continued)
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOUT = 1.2V
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOUT = 0.9V
1.25
0.94
1.23
0.93
1.22
0.92
DC Output Voltage (V)
DC Output Voltage (V)
1.24
0.95
TPS6236x
VOUT = 1.2V
TA = 25°C
1.21
1.20
1.19
1.18
1.16
1.15
1m
10m
100m
Output Current (A)
1
0.91
0.90
0.89
0.88
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
1.17
TPS6236x
VOUT = 0.9V
TA = 25°C
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
0.87
0.86
3
0.85
1m
10m
100m
Output Current (A)
1
3
G013
Figure 16.
DC OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOUT = 0.6V
STARTUP INTO NO LOAD
VOUT = 0.5V
0.65
0.64
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
IOUT = 0A
VIN = 3.6V
VOUT = 0.5V
TPS62361B
VOUT = 0.6V
TA = 25°C
0.63
DC Output Voltage (V)
G014
Figure 15.
0.62
0.61
0.60
0.59
Inductor Current 200mA/Div
0.58
Forced PWM, VIN = 2.8V
Forced PWM, VIN = 3.6V
Forced PWM, VIN = 4.2V
Auto PFM/PWM, VIN = 2.8V
Auto PFM/PWM, VIN = 3.6V
Auto PFM/PWM, VIN = 4.2V
0.57
0.56
0.55
1m
10m
100m
Output Current (A)
1
EN 2V/DIV
3
Time Base - 20μs/Div
G017
G015
Figure 17.
14
VOUT 200mV/Div
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Figure 18.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
STARTUP INTO NO LOAD
VOUT = 1.5V
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
IOUT = 0A
VIN = 3.6V
VOUT = 1.5V
STARTUP INTO LOAD
VOUT = 0.5V
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
IOUT = 1A
VIN = 3.6V
VOUT = 0.5V
VOUT 1V/Div
VOUT 200mV/Div
Inductor Current 500mA/Div
Inductor Current 500mA/Div
EN 2V/DIV
EN 2V/DIV
Time Base - 20μs/Div
Time Base - 20μs/Div
G019
G018
Figure 19.
Figure 20.
STARTUP INTO LOAD
VOUT = 1.5V
SWITCHING WAVE FORMS
IOUT = 10mA
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
ILOAD = 1A
VIN = 3.6V
VOUT = 1.5V
VOUT 1V/Div
VOUT 10mV/Div w/ 1.2V Offset
Inductor Current 200mA/Div
Inductor Current 1A/Div
EN 2V/DIV
SW Pin 2V/Div
TPS62361B
IOUT = 10mA
Time Base - 20μs/Div
VIN = 3.6V
VOUT = 1.2V
Time Base - 4μs/Div
G021
G020
Figure 21.
Copyright © 2011–2012, Texas Instruments Incorporated
Figure 22.
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15
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SWITCHING WAVE FORMS
IOUT = 200mA
TPS62361B
IOUT = 200mA
VIN = 3.6V
VOUT = 1.2V
SWITCHING WAVE FORMS
IOUT = 1A
TPS62361B
IOUT = 1A
VIN = 3.6V
VOUT = 1.2V
VOUT 10mV/Div w/ 1.2V Offset
Inductor Current 200mA/Div w/ 200mA Offset
VOUT 10mV/Div w/ 1.2V Offset
Inductor Current 200mA/Div w/ 1A Offset
SW Pin 2V/Div
SW Pin 2V/Div
Time Base - 250ns/Div
Time Base - 250ns/Div
G023
G022
TPS62361B
IOUT = 3A
VIN = 3.6V
VOUT = 1.2V
Figure 23.
Figure 24.
SWITCHING WAVE FORMS
IOUT = 3A
OUTPUT VOLTAGE RAMP CONTROL
NO LOAD
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
VOUT 1V/Div w/ 0.6V Offset
VOUT 10mV/Div w/ 1.2V Offset
IOUT = 0A
VIN = 3.6V
VOUT = 0.6V to 1.5V
Inductor Current 200mA/Div w/ 3A Offset
Inductor Current
500mA/Div
VSEL0 2V/Div
SW Pin 2V/Div
Time Base - 20μs/Div
Time Base - 250ns/Div
G025
G024
Figure 25.
16
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Figure 26.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE RAMP CONTROL
IOUT = 1A
TPS62361B
RAMP[2:0] = 000 (32mV/μs)
LOAD TRANSIENT RESPONSE
IOUT RANGE: 5mA to 200mA
TPS62361B
CLOAD = 22μF
VOUT 1V/Div w/ 0.6V Offset
VIN = 3.6V
VOUT = 1.2V
VOUT 20mV/Div w/ 1.2V Offset
Inductor Current 500mA/Div
IOUT = 1A
VIN = 3.6V
VOUT = 0.6V to 1.5V
Inductor Current 200mA/Div
VSEL0 2V/Div
IOUT 100mA/Div
Time Base - 20μs/Div
Time Base - 100μs/Div
G026
G027
Figure 27.
Figure 28.
LOAD TRANSIENT RESPONSE
IOUT RANGE: 5mA to 1A
LOAD TRANSIENT RESPONSE
IOUT RANGE: 200mA to 1A
TPS62361B
CLOAD = 22μF
VIN = 3.6V
VOUT = 1.2V
TPS62361B
CLOAD = 22μF
VIN = 3.6V
VOUT = 1.2V
VOUT 50mV/Div w/ 1.2V Offset
VOUT 50mV/Div w/ 1.2V Offset
Inductor Current 500mA/Div
Inductor Current 500mA/Div
IOUT 1A/Div
IOUT 1A/Div
Time Base - 100μs/Div
Time Base - 100μs/Div
G028
Figure 29.
Copyright © 2011–2012, Texas Instruments Incorporated
G029
Figure 30.
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17
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE
IOUT RANGE: 1A to 3A
LINE TRANSIENT RESPONSE
VIN RANGE: 4.2V to 3.2V
TPS62361B
CIN = 100nF
TPS62361B
CLOAD = 22μF
VIN = 3.6V
VOUT = 1.2V
VOUT = 1.2V
CLOAD = 22μF
IOUT = 300mA
VIN 1V/Div w/ 4.2V Offset
VOUT 50mV/Div w/ 1.2V Offset
VOUT 20mV/Div w/ 1.2V Offset
Inductor Current 1A/Div
Inductor Current 200mA/Div
IOUT 2A/Div
Time Base - 100μs/Div
Time Base - 20μs/Div
G030
G031
Figure 31.
Figure 32.
SHUTDOWN CURRENT
vs
INPUT VOLTAGE
QUIESCENT CURRENT
vs
INPUT VOLTAGE
150
10
130
TPS6236x
MODE0 = 0 (Auto PFM/PWM)
EN = HIGH
1
Quiescent Current (µA)
Shutdown Current (µA)
110
TPS6236x
EN = LOW
0.1
90
70
50
0.01
AVIN, TA = −40°C
AVIN, TA = 25°C
AVIN, TA = 125°C
0.001
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
30
VIN, TA = −40°C
VIN, TA = 25°C
VIN, TA = 125°C
5.0
5.5
10
2.5
TA = −40°C, Auto PFM/PWM
TA = 25°C, Auto PFM/PWM
TA = 125°C, Auto PFM/PWM
3.0
3.5
4.0
4.5
Input Voltage (V)
G034
Figure 33.
18
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5.0
5.5
G035
Figure 34.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
300
1000
Switching Frequency (kHz)
Quiescent Current (µA)
250
10000
TPS6236x
MODE0 = 1 (Forced PWM)
EN = HIGH
200
150
100
TPS6236x
VOUT = 1.2V
VIN = 3.6V
10
1
50
0
2.5
100
TA = −40°C, Forced PWM
TA = 25°C, Forced PWM
TA = 125°C, Forced PWM
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
Auto PFM/PWM
Forced PWM
0.1
0.1
5.5
1
10
100
Output Current (mA)
1000 3000
G036
G037
Figure 35.
Figure 36.
FET CURRENT LIMIT
vs
INPUT VOLTAGE
4.0
3.8
3.6
FET Current Limit (A)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
2.5
High Side PMOS Current Limit
Low Side NMOS Current Limit
Negative NMOS Current Limit
TPS6236x
TA = 25°C
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
G038
Figure 37.
Copyright © 2011–2012, Texas Instruments Incorporated
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19
TPS62360, TPS62361B
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
TPS6236x
VIN
C2
C1
L
VIN
AVIN
EN
SW
SW
VDD
SENSE+
SENSE-
VOUT
C4
SCL
SDA
VDD
VSEL0
VSEL1
C3
PGND
PGND
AGND PGND
Table 1. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
TPS6236x
3A Processor Supply with I2C
Compatible Interface and Remote
Sense
Texas Instruments
L
1 μH, 4 mm x 4 mm x 2.1 mm
Coilcraft (XFL4020-102ME1.0)
C2, C4
10 μF, Ceramic, 6.3V, X5R
Murata (GRM188R60J106ME84D)
C1, C3
0.1 μF, Ceramic, 10V, X5R
Standard
20
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com
SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
DETAILED DESCRIPTION
The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for batterypowered portable applications. With an input voltage range of 2.5V to 5.5V, common battery technologies are
supported.
The device provides up to 3A peak load current, operating at 2.5MHz typical switching frequency.
The devices convert to an output voltage range of 0.77V to 1.4V (TPS62360 / TPS62362) and 0.5V to 1.77V
(TPS62361B / TPS62363), programmable via I2C interface in 10mV steps.
The TPS6236x supports low-voltage DSPs and processor cores in smart-phones and handheld computers,
including latest submicron processes and their retention modes and addresses digital voltage scaling
technologies such as SmartReflex™.
Output Voltages and Modes can be fully programmed via I2C. To address different performance operating points
and/or startup conditions, the device offers four output voltage / mode presets which can be chosen via
dedicated hardware input pins allowing simple and zero latency output voltage transition.
The devices focus on a high output voltage accuracy. The fully differential sensing and the DCS-Control™
architecture achieve precise static and dynamic, transient output voltage regulation. This accounts for stable
processor operation. Output voltage security margins can be kept small, resulting in an increased overall system
efficiency.
The TPS6236x devices offer high efficiency step down conversion. The area of highest efficiency is extended
towards low output currents to increase the efficiency while the processor is operating in retention mode, as well
as towards highest output currents reducing the power loss. This addresses the power profile of processors. High
efficiency conversion is required for low output currents to support the retention modes of processors, resulting in
an increased battery on-time. To address the processor maximum performance operating points with highest
output currents, high efficiency conversion is enabled as well to save the battery on-time and reduce input power.
The robust architecture and multiple safety features allow perfect system integration.
The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of
approximately less than 25 mm2.
OPERATION
The TPS6236x synchronous switched mode power converters are based on DCS-Control™, an advanced
regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control
architectures.
While a comparator stage provides excellent load transient response, an additional voltage loop ensures high DC
accuracy as well. The TPS6236x compensates ground shifts at the load by the differentially sensing the output
voltage at the point of load.
The internal ramp generator adds information about the load current and fast output voltage changes. The
internally compensated regulation network achieves fast and stable operation with low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation
depending on the input voltage. As the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to light loads. The transition from PWM to Power Save Mode is seamless and avoids output
voltage transients.
An internal current limit supports nominal output currents of up to 3A. The TPS6236x family offers both excellent
DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing
interference with RF circuits.
ENABLING AND DISABLING THE DEVICE
The device is enabled by setting the EN input to a logic high. Accordingly, a logic low disables the device. If the
device is enabled, the internal power stage will start switching and regulate the output voltage to the programmed
threshold. The EN input must be terminated unless the internal pull down resistor is activated.
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The I2C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin.
If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per
default, this feature is disabled. Programming the EN_DISC bit to a logic high will discharge the output capacitor
via a typ. 300Ω path on the SENSE+ pin.
SOFT START
The device incorporates an internal soft start circuitry that controls the ramp up of the output voltage after
enabling the device. This circuitry eliminates inrush current to avoid excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance.
During soft start, the output voltage is monotonically ramped up to the minimum programmable output voltage.
After reaching this threshold, the output voltage is further increased following the slope as programmed in the
ramp rate settings (see RAMP RATE CONTROLLING) until reaching the programmed output voltage. Once the
nominal voltage is reached, regular operation as described above will continue.
The device is able to start into a pre biased output capacitor as well.
PROGRAMMING THE OUTPUT
The TPS6236x devices offer four similar registers to program the output. Two dedicated hardware input pins,
VSEL0 and VSEL1, are implemented for choosing the active register. The logic state of VSEL0 and VSEL1
select the register whose settings are present at the output. The VSEL0 and VSEL1 pins must be terminated
unless the internal pull-down resistors are activated.
The registers have a certain initial default value (see Table 2) and can be readjusted via I2C during operation.
This allows a simple transition between several output options by triggering the dedicated input pins. At the same
time since the presets can be readjusted during operation, this offers highest flexibility.
Table 2. Output Presets
INPUT PINS
DEFAULT OPERATION MODE
DEFAULT OUTPUT VOLTAGE [V]
VSEL
1
VSEL
0
PRESET
I2C REGISTER
TPS62360, TPS62361B,
TPS62362, TPS62363
TPS62360
TPS62361B
TPS62362
TPS62363
0
0
SET0
0x00h – see Table 13, Table 14,
Table 15, Table 16
Power Save Mode
1.40
0.96
1.23
1.20
0
1
SET1
0x01h – see Table 17, Table 18,
Table 19, Table 20
Power Save Mode
1.00
1.40
1.00
1.36
1
0
SET2
0x02h – see Table 21, Table 22,
Table 23, Table 24
Power Save Mode
1.40
1.16
1.20
1.50
1
1
SET3
0x03h – see Table 25, Table 26,
Table 27, Table 28
Power Save Mode
1.10
1.16
1.10
1.00
Via the I2C interface and/or the four preset options, the following output parameters can be changed:
• Output voltage from 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V (TPS62361B/63) with 10mV granularity
• Mode of operation: Power Save Mode or forced PWM mode
The slope for transition between different output voltages (Ramp Rate) can be changed via I2C as well. The
slope applies for all presets globally. See RAMP RATE CONTROLLING for further details.
Since the output parameters can be changed by dedicated pins for selecting presets and by I2C, the following
use scenarios are feasible:
• Control the device via dedicated pins only, after programming the presets, to choose and change within the
programmed settings
• Program via I2C only. The dedicated input pins have fixed connections. Changes are conducted by changing
the preset values of the active register.
• Dedicated input pins and I2C mixed operation. The non active presets might be changed. The dedicated input
pins are used for the transition to the new output condition. Changes within an active preset via I2C are
feasible as well.
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DYNAMIC VOLTAGE SCALING
The output voltage can be adjusted dynamically. Each of the four output registers can be programmed
individually by setting OV[5:0] (TPS62360/62) and OV[6:0] (TPS62361B/63) respectively in the SET0, SET1,
SET2 and SET3 registers.
Table 3. TPS62360, TPS62362 Output Voltage Settings
for Registers SET0, SET1, SET2 and SET3
REGISTERS: SET0, SET1, SET2, SET3
OV[D5:D0]
OUTPUT VOLTAGE
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
00 0011
800 mV
…
…
11 1101
1380 mV
11 1110
1390 mV
11 1111
1400 mV
Table 4. TPS62361B, TPS62363 Output Voltage
Settings for Registers SET0, SET1, SET2 and SET3
REGISTERS: SET0, SET1, SET2, SET3
OV[D6:D0]
OUTPUT VOLTAGE
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
000 0011
530 mV
…
…
111 1101
1750 mV
111 1110
1760 mV
111 1111
1770 mV
If the output voltage is changed at the active register (selected by VSEL0 and VSEL1), these changes will apply
after the I2C command is sent.
POWER SAVE MODE AND FORCED PWM MODE
The TPS6236x devices feature a Power Save Mode to gain efficiency at light output current conditions. The
device automatically transitions in both directions between pulse width modulation (PWM) operation at high load
and pulse frequency modulation (PFM) operation at light load current. This maintains high efficiency at both light
and heavy load currents. In PFM Mode, the device generates single switching pulses when required to maintain
the programmed output voltage.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
The output current, at which the device transitions from PWM to PFM operation can be estimated as follows:
V - VOUT VOUT
1
IOUT,TRANS = IN
2
VIN
(f L)
(1)
With:
VIN = Input voltage
VOUT = Output Voltage
ƒ = Switching frequency, typ. 2.5 MHz
L = Inductor value
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The TPS6236x is optimized for low output voltage ripple. Therefore, the peak inductor current in PFM mode is
kept small and can be calculated as follows:
IL,PFM,peak =
t ON
´ (VIN - VOUT )
L
(2)
And:
t ON =
VOUT
´ 350ns + 20ns
VIN
(3)
With:
VIN = Input Voltage
VOUT = Output Voltage
tON = On-time of the High Side FET, from Equation 3
L = Inductor value
The TPS6236x offers a forced PWM mode as well. In this mode, the converter is forced in PWM mode even at
light load currents. This comes with the benefit that the converter is operating with lower output voltage ripple.
Compared to the PFM mode, the efficiency is lower during light load currents.
According to the output voltage, the Power Save Mode / forced PWM Mode can be programmed individually for
each preset via I2C by setting the MODE0 – MODE3 bit D7. Table 2 shows the factory presets after enabling the
I2C. For additional flexibility, the Power Save Mode can be changed at a preset that is currently active.
RAMP RATE CONTROLLING
If the output voltage is changed, the TPS6236x can actively control the voltage ramp rate during the transition.
An internal oscillator is embedded for high timing precision.
Figure 38 and Figure 39 show the operation principle. If the output voltage changes, the device will change the
output voltage through discrete steps with a programmable ramp rate resulting in a corresponding transition time.
The ramp up/down slope can be programmed via I2C interface (see Table 5).
Table 5. Ramp Rates
RMP [2:0]
RAMP RATE
[mV/µs]
[µs/10mV]
000
32
0.3125
001
16
0.625
010
8
1.25
011
4
2.5
100
2
5
101
1
10
110
0.5
20
111
0.25
40
For a transition of the output voltage from VOUT,A to VOUT,B and vice versa, the resulting ramp up/down slope can
be calculated as
ΔVOUT
mV
1
= 32
Δt
μs 2(RMP[2-0] )2
(4)
If the device is operating in forced PWM Mode, the device actively controls both the ramp up and down slope.
If Power Save Mode is activated, the ramp up phase follows the programmed slope.
To force the output voltage to follow the ramp down slope in Power Save Mode, the RAMP_PFM bit needs to be
set. This will force the converter to follow the ramp down slope during PFM operation as well.
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If the RAMP_PFM bit is not set in Power Save Mode, the slope can be less at low output currents since the
device does not actively source energy back from the output capacitor to the input or it might be sharper at high
output currents since the output capacitor is discharged quickly.
Output
Voltage
Output
Voltage
VOUT,B
VOUT,B
ΔVOUT
10 mV
VOUT,A
ΔVOUT
20 mV
VOUT,A
10 mV/Ramp Rate
20 mV/Ramp Rate
time
Δt
time
Δt
(TPS62360 / TPS62362)
(TPS62361B / TPS62363)
Figure 38. Ramp Up
Output
Voltage
Output
Voltage
VOUT,A
10 mV/Ramp Rate
VOUT,B
10 mV
ΔVOUT
20 mV/Ramp Rate
ΔVOUT
VOUT,B
20 mV
VOUT,A
time
Δt
(TPS62360 / TPS62362)
Δt
time
(TPS62361B / TPS62363)
Figure 39. Ramp Down
The TPS62360 and TPS62362 ramp the output voltage taking 10mV steps, while the TPS62361B and
TPS62363 ramp taking 20mV steps with a final 10mV step if required. The resulting slope remains equal for both
devices.
While the output voltage setpoint is changed in a digital stair step fashion, the connected output capacitor flattens
the steps to create a linear change in the output voltage.
SAFE OPERATION AND PROTECTION FEATURES
Inductor Current Limit
The inductor current limiting prevents the device from drawing high inductor current and excessive current from
the battery. Excessive current might occur with a shorted/saturated inductor or a heavy load/shorted output
circuit condition.
The incorporated inductor peak current limit measures the current while the high side power MOSFET is turned
on. Once the current limit is tripped, the high side MOSFET is turned off and the low side MOSFET is turned on
to ramp down the inductor current. This prevents high currents to be drawn from the battery.
Once the low side MOSFET is on, the low side forward current limit keeps the low side MOSFET on until the
current through it decreases below the low side forward current limit threshold.
The negative current limit acts if current is flowing back to the battery from the output. It works differently in PWM
and PFM operation. In PWM operation, the negative current limit prevents excessive current from flowing back
through the inductor to the battery, preventing abnormal voltage conditions at the switching node. In PFM
operation, a zero current limits any power flow back to the battery by preventing negative inductor current.
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Die Temperature Monitoring and Over Temperature Protection
The TPS6236x offers two stages of die temperature monitoring and protection.
The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that
the die temperature is in the higher range. If the device's junction temperature, TJ, exceeds 120°C typical, the
TJEW bit is set high. To avoid the thermal shutdown being triggered, the current drawn from the TPS6236x
should be reduced at this early stage.
The Over Temperature Protection feature disables the device if the temperature increases due to heavy load
and/or high ambient temperature. It monitors the device die temperature and, if required, triggers the device into
shutdown until the die temperature falls sufficiently.
If the junction temperature, TJ, exceeds 150°C typical, the device goes into thermal shutdown. In this mode, the
power stage is turned off. During thermal shutdown, the I2C interface remains operable. All register values are
kept.
For the thermal shutdown, a hysteresis of 20°C typical is implemented allowing the device to cool after the
shutdown is triggered. Once the junction temperature TJ cools down to 130°C typical, the device resumes
operation.
If a thermal shutdown has occurred, the TJTS bit is latched and remains a logic high as long as VDD and AVIN
are present and until the bit is reset by the host.
Input Under Voltage Protection
The input under voltage protection is implemented in order to prevent operation of the device for low input
voltage conditions. If the device is enabled, it prevents the device from switching if AVIN falls below the under
voltage lockout threshold. If the AVIN under voltage protection threshold is tripped, the device will go into under
voltage shutdown instantaneously, turning the power stage off and resetting all internal registers. The input under
voltage protection is also implemented on the VDD input. If the VDD under voltage protection threshold is
tripped, the device will reset all internal registers.
A under voltage lockout hysteresis of VUVLO,HYST(AVIN) at AVIN and VUVLO,HYST(VDD) at VDD is implemented.
The I2C compatible interface remains fully functional if AVIN and VDD are present. If the under voltage lockout of
AVIN or VDD is triggered during operation, all internal registers are reset to their default values. Figure 40 shows
the UVLO block diagram.
AVIN
external low
ohmic connection
AVIN
Under Voltage?
Device Shutdown
VIN
VDD
VDD
Under Voltage?
≥1
Register Reset,
2
I C I/F Disabled
Figure 40. UVLO State Chart
By connecting VIN and AVIN to the same potential, VIN is included in the under voltage monitoring. If a low pass
input filter is applied at AVIN (not mandatory for the TPS6236x), the delay and shift in the voltage level can be
calculated by taking the typical quiescent current IQ at AVIN. As an example, for IQ and 10Ω series resistance,
this results in a minimal static shift of approx. 560µV.
VIN and AVIN must be connected to the same source for proper device operation.
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APPLICATION INFORMATION
I2C INTERFACE
Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus
through open drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS6236x device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1Mbps)
• High-speed mode (3.4 Mbps)
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents remain intact as long as
VDD and AVIN are present in the specified range. Tripping the under voltage lockout of AVIN or VDD deletes the
registers and establishes the default values once the supply is present again.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode. The TPS6236x device supports 7-bit addressing. 10-bit addressing and general call addressing are
not supported.
Table 6 shows the TPS6236x devices and their assigned I2C addresses.
Table 6. I2C Address
I2C ADDRESS
DEVICE OPTION
HEXADECIMAL
CODED
BINARY CODED
TPS62360
(0x60)HEX
(110 0000)2
TPS62361B
(0x60)HEX
(110 0000)2
TPS62362
(0x60)HEX
(110 0000)2
TPS62363
(0x60)HEX
(110 0000)2
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should
recognize a start condition.
SDA
SCL
S
START condition
P
STOP condition
Figure 41. START and STOP Conditions
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The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
SDA
SCL
Data line stable;
data valid
Change of
data allowed
Figure 42. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the
addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
1
SCL
8
2
9
S
Clock Pulse for
Acknowledgment
START condition
Figure 43. Acknowledge on the I2C Bus
Recognize
repeated START
or STOP
Condition
Recognize START or
repeated START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Sr
Acknowledgment
Signal From Slave
SCL
S
or
1
Sr
2
7
8
9
ACK
1
2-8
9
ACK
Address
Clock Line Held Low While
Interrupts are Serviced
START or
repeated START
Condition
Sr
or
P
repeated START
or STOP
Condition
Figure 44. Bus Protocol
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HS-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
I2C UPDATE SEQUENCE
The TPS6236x requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, the TPS6236x device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I2C address selects the TPS6236x. The TPS6236x
performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
1
7
1
S
Slave Address
1
R/W A
8
1
8
1
1
Register Address
A
Data
A/A
P
“0” Write
A
A
S
Sr
P
From Master to Device
From Device to Master
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
=
=
=
=
=
Figure 45. Write Data Transfer Format in F/S-Mode
1
7
S
Slave Address
1
1
R/W A
8
1
1
7
Register Address
A
Sr
Slave Address
A
A
S
Sr
P
From Device to Master
R/W A
8
1
1
Data
A/A
P
“1” Read
“0” Write
From Master to Device
1
1
=
=
=
=
=
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
Figure 46. Read Data Transfer Format in F/S-Mode
F/S Mode
1
S
8
HS-Master Code
H/S Mode
1
1
7
A
Sr
Slave Address
1
1
R/W A
F/S Mode
8
1
8
1
1
Register Address
A
Data
A/A
P
Data Transferred
(n x Bytes + Acknowledge)
From Master to Device
From Device to Master
A
A
S
Sr
P
=
=
=
=
=
H/S Mode continues
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
Sr
Slave Address
Figure 47. Data Transfer Format in H/S-Mode
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Slave Address Byte
MSB
X
X
X
X
X
X
A1
LSB
A0
The slave address byte is the first byte received following the START condition from the master device.
Register Address Byte
MSB
0
0
0
0
0
D2
D1
LSB
D0
Following the successful acknowledgment of the slave address, the bus master will send a byte to the
TPS6236x, which will contain the address of the register to be accessed.
I2C REGISTER RESET
The I2C registers can be reset by pulling VDD below the VDD Under Voltage Level, VDD,UVLO. VDD can be used
as a hardware reset function to reset the registers to defaults, if VDD is supplied by a GPIO of the host. The
host's GPIO must be capable of driving IVDD,max.
Refer to the Input Under Voltage Protection section for details.
PULL DOWN RESISTORS
The EN, VSEL0 and VSEL1 inputs feature internal pull down resistors to discharge the potential if one of the pins
is not connected or is triggered by a high impedance source. See Figure 48. By default, the pull down resistors
are enabled.
EN /
VSELx
input
buffer
EN_internal /
VSELx_internal
RPD
PD_x
Figure 48. Pull Down Resistors at EN, VSEL0 and VSEL1 Pins
If a pin is read as a logic HIGH, its pull down resistor is disconnected dynamically to reduce power consumption.
To achieve lowest possible quiescent current or if external pull up/down resistors are employed, the internal pull
down resistors can be disabled individually at EN, VSEL0 and VSEL1 by I2C programming the registers PD_EN,
PD_VSEL0 and PD_VSEL1.
INPUT CAPACITOR SELECTION
The input capacitor is required to buffer the pulsing current drawn by the device at VIN and reducing the input
voltage ripple. The pulsing current is originated by the operation principles of a step down converter.
Low ESR input capacitors are required for best input voltage filtering and minimal interference with other system
components. For best performance, ceramic capacitors with a low ESR at the switching frequency are
recommended. X7R or X5R type capacitors should be used.
A ceramic input capacitor in the nominal range of CIN = 10µF to 22µF should be a good choice for most
application scenarios. In general, there is no upper limit for increasing the input capacitor.
For typical operation, a 10µF X5R type capacitor is recommended. DC bias effects reduce the effective
capacitance of MLCC capacitors as a function of the voltage applied. This effect needs to be factored in when
choosing an input capacitor by choosing the proper voltage rating. Table 7 shows a list of recommended
capacitors.
30
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 7. List of Recommended Capacitors
CAPACITANCE
[µF]
TYPE
DIMENSIONS
L x W x H [mm3]
MANUFACTURER
10
GRM188R60J106M
0603: 1.6 x 0.8 x 0.8
Murata
10
CL10A106MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
22
GRM188R60G226M
0603: 1.6 x 0.8 x 0.8
Murata
22
CL10A106MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
DECOUPLING CAPACITORS AT AVIN, VDD
Noise impacts can be reduced by buffering AVIN and VDD with a decoupling capacitor. It is recommended to
buffer AVIN and VDD with a X5R or X7R ceramic capacitor of at least 0.1µF connected between AVIN, AGND
and VDD, AGND respectively. The capacitor closest to the pin should be kept small (< 0.22µF) in order to keep a
low impedance at high frequencies. In general, there is no upper limit for the total capacitance.
Adding a low pass input filter at AVIN (e.g. by adding RLP = 10Ω resistor in series) is not mandatory for the
TPS6236x. It can be used if the supply rail at very noisy (e.g. by the use of a pre-regulator) to filter away
aggressive noise. See Figure 49.
TPS6236x
RLP
CVIN
CAVIN
VIN
AVIN
EN
VDD
SCL
SDA
SW
SW
SENSE+
COUT
SENSE-
VSEL0
VSEL1
AGND
PGND
PGND
PGND
Figure 49. Optional Low Pass Filter at AVIN
INDUCTOR SELECTION
The choice of the inductor type and value has an impact on the inductor ripple current, the transition point of
PFM to PWM operation, the output voltage ripple and accuracy. The subsections below support for choosing the
proper inductor.
Inductance Value
The TPS6236x is designed for best operation with a nominal inductance value of 1µH.
Inductances down to 0.47µH nominal may be used to improve the load transient behavior or to decrease the total
solution size. See OUTPUT FILTER DESIGN for details.
Depending on the inductance, using inductances lower than 1µH results in a higher inductor current ripple. It can
be calculated as:
V
1 - OUT
VIN
ΔIL = VOUT ´
L ´ ¦
(5)
With:
VIN = Input Voltage
VOUT = Output Voltage
ƒ = Switching frequency, typ. 2.5 MHz
L = Inductance
Inductor Saturation Current
The inductor needs to be selected for its current rating. To pick the proper saturation current rating, the maximum
inductor current can be calculated as:
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IL,MAX = IOUT,MAX +
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ΔIL
2
(6)
With:
ΔIL = Inductor ripple current (see Equation 5)
IOUT,MAX = Maximum output current
Since the inductance can be decreased by saturation effects and temperature impact, the inductor needs to be
chosen to have an effective inductance of at least 0.3µH under temperature and saturation effects.
Table 8 shows a list of inductors that have been used with the TPS6236x. Special care needs to be taken for
choosing the proper inductor, taking e.g. the load profile into account.
Table 8. List of Recommended Inductors
INDUCTANCE
[µH]
SATURATION
CURRENT
RATING (1)
(ΔL/L =30%,
typ)
[A]
TEMPERATURE
CURRENT
RATING (1)
(ΔT =40°C, typ)
[A]
DIMENSIONS
LxWxH
[mm3]
DC
RESISTANCE
[mΩ typ]
TYPE
MANUFACTURER
1.0
5.4
11.0
4.0 x 4.0 x 2.1
11
XFL4020-102ME1.0
Coilcraft
1.0
4.7
3.6
3.2 x 2.5 x 1.2
34
DFE322512C
Toko
1.0
6.0
4.1
4.4 x 4.1 x 1.2
38
SPM4012
TDK
1.0
4.7
3.8
3.2 x 2.5 x 1.2
35
PILE32251B1R0MS-11 (2)
Cyntec
1.0
4.5
7.0
4.15 x 4.0 x 1.8
24
PIMB042T-1R0MS11
Cyntec
1.0
4.2
3.7
2.5 x 2.0 x 1.2
38
DFE252012R -H1R0N (2)
Toko
0.47
6.6
11.2
4.0 x 4.0 x 1.5
8
XFL4015-471M
Coilcraft
0.47
5
4.5
2.5 x 2.0 x 1.2
23
PIFE25201BR47MS-11 (2)
Cyntec
0.47
5.2
4.4
2.5 x 2.0 x 1.2
27
DFE252012R -HR47N (3)
Toko
(1)
(2)
(3)
Excessive inductor temperature might result in a further effective inductance drop which might be below or close to the max. current limit
threshold, ILIM,max, depending on the inductor, use case and thermal board design. Proper saturation current rating must be verified,
taking into account the use scenario and thermal board layout.
Product preview, release planned for Q3/4 2012. Contact manufacturer for details.
Under development, typ. data might change. Contact manufacturer for schedule and details.
OUTPUT CAPACITOR SELECTION
The unique hysteretic control scheme allows the use of tiny ceramic capacitors. For best performance, ceramic
capacitors with low ESR values are recommended to achieve high conversion efficiency and low output voltage
ripple. For stable operation, X7R or X5R type capacitors are recommended.
The TPS6236x is designed to operate with a minimum output capacitor of 10µF for a 1µH inductor and 2x10µF
for a 0.47µH inductor, placed at the device's output. In addition, a 0.1µF capacitor can be added to the output to
reduce the high frequency content created by a very sudden load change. For stability, an overall maximum
output capacitance must not be exceeded. See OUTPUT FILTER DESIGN.
Table 7 shows a list of tested capacitors. The TPS6236x is not designed for use with polymer, tantalum, or
electrolytic output capacitors.
OUTPUT FILTER DESIGN
The inductor and the output capacitors create the output filter. The output capacitors consist of COUT and buffer
capacitors at the load, CLOAD. See Figure 50. Buffering the load by ceramic capacitors, CLOAD, improves the
voltage quality at the load input and the dynamic load step behavior. This is especially true if the trace between
the TPS6236x and the load is longer than the smallest possible.
32
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TPS6236x
L
SW
SW
COUT
LOAD
SENSE+
CLOAD
SENSE-
PGND
PGND
PGND
Figure 50. L, COUT and CLOAD Forming the Output Filter
Depending on the chosen inductor value, a certain minimum output capacitor COUT must be present. Also
depending on the chosen inductor value, a maximum output and buffer capacitor configuration (COUT + CLOAD)
must not be exceeded. Figure 51 shows the range of L, COUT and CLOAD that create a stable output filter.
L
1µH
MI
MAX
N(
Output filter range
(CO
UT
+C
)
)
T
C OU
LOA
D
0.47µH
10µF 20µF
COUT + CLOAD
100µF
200µF
Figure 51. Recommended L, COUT and CLOAD Combinations
Within the allowed output filter range, a certain filter can be chosen to improve further on application specific key
parameters.
The choice of the inductance, L, affects the inductor current ripple, output voltage ripple, the PFM to PWM
transition point and the PFM operation switching frequency.
The TPS6236x is designed for operation with a nominal inductance value of 1µH. Inductances down to 0.47µH
nominal may be used to improve the load transient behavior or to decrease the total solution size. This increases
the inductor current ripple (see Equation 5). As a consequence, the output voltage ripple is increased if the
output capacitance is kept constant. The increased inductor ripple current also causes higher peak inductor
currents (see Equation 6), requiring a higher saturation current rating. Furthermore, the PFM switching frequency
is decreased and the automatic PFM to PWM transition occurs at a higher output current (see Equation 1).
The choice of the output and buffer capacitance (COUT and CLOAD) affects the load step behavior, output voltage
ripple, PFM switching frequency and output voltage transition time.
A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as
decreasing the PFM switching frequency. For very large output filter combinations, the output voltage might be
slower than the programmed ramp rate at voltage transitions (see RAMP RATE CONTROLLING) because of the
higher energy stored on the output capacitance. At startup, the time required to charge the output capacitor to
0.5V might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor (see
ENABLING AND DISABLING THE DEVICE), this requires more time to settle VOUT down as a consequence of
the increased time constant τ = RDISCHARGE x (COUT + CLOAD).
For further performance or specific demands, these values might be tweaked. In any case, the loop stability
should be checked since the control loop stability might be affected. At light loads, if the device is operating in
PFM Mode, choosing a higher value minimizes the voltage ripple resulting in a better DC output accuracy.
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THERMAL AND DEVICE LIFE TIME INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Thermal performance can be enhanced by proper PCB layout. Wide power traces come with the ability to sink
dissipated heat. This can be improved further on multi layer PCB designs with vias to different layers.
Proper PCB layout with a focus on thermal performance results in a reduced junction-to-ambient thermal
resistance θJA and thereby reduces the device junction temperature, TJ.
The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at TJ = 105°C) is affected by
the junction temperature and the continuously drawn current at the VIN pin and the SW pins. In order to be
consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at TJ = 105°C), the
VIN pin current should not continuously exceed 1275mA and the SW pins current should not continuously
exceed 2550mA so as to prevent electromigration failure in the solder bump. Drawing 1150mA at VIN would, as
an example, be the case for typically IOUT = 2350mA, VOUT = 1.5V and VIN = 3.6V.
Exceeding the VIN pin / SW pins current rating might affect the device reliability. As an example, drawing current
peaks of IOUT = 3000mA with up to 10% of the application time over a base continuous output current of IOUT =
2000mA might reduce the Power-on-Hours to 90000 hours for conditions such as VIN = 2.7V, VOUT = 1.5V, TJ =
105°C. In this example, exceeding TJ = 105°C in combination with a higher peak output current duty cycle clearly
further affects the device life time.
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953).
PCB LAYOUT
The PCB layout is an important step to maintain the high performance of the TPS6236x. Both the high current
and the fast switching nodes demand full attention to the PCB layout to save the robustness of the TPS6236x
through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and
output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency.
Signal Routing Strategy
The TPS6236x is a mixed signal IC. Depending on the function of a pin or trace, different board layout strategies
must be addressed to achieve a good design. Due to the nature of a switching converter, some signals are
sensitive to influence from other signals (aggressors). The sense lines, SENSE+ and SENSE-, are sensitive to
the aggressors, which are high bandwidth I/O pins (SCL and SDA) and the switch node (SW) and their
connected traces. Special care must be taken to avoid cross-talk between between them.
The following recommendations need to be followed:
•
•
•
•
•
34
PGND, VIN and SW should be routed on thick layers. They must not surround inner signal layers which are
not able to withstand interference from noisy PGND, VIN and SW. They create a flux which is determined by
the switching frequency. The flux generated affects neighboring layers due to capacitive coupling across
layers.
AGND, AVIN and VDD must be isolated from noisy signals.
If crossing layers is required for PGND, VIN and SW, they must be dimensioned to support the high currents
to not cause high IR drops. In general, changing the layers frequently must be avoided.
Signal traces, and especially the sense lines (SENSE+ and SENSE-), must be kept away from noisy traces/
signals. Avoid capacitive coupling with neighboring noisy layers by cutting away the overlapping areas close
to signal traces. Special care must be taken for the sense lines to avoid inductive / capacitive cross-talk from
aggressors, both from noisy lines as well as external inductors which generate magnetic fields.
Care should be taken for a proper thermal layout. Wide traces, connecting through the layers with vias,
provides a proper thermal path to sink the heat energy created from the device and inductor.
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External Components Placement
The input capacitor at VIN must be placed closest to the IC for proper operation. The decoupling caps at AVIN
and VDD reduce noise impacts and should be placed as close to the IC as possible. The output filter, consisting
of COUT and L, converts the switching signal at SW to the noiseless output voltage. It should be placed as close
as possible to the device keeping the switch node small, for best EMI behavior.
Trace routing
Route the VIN trace wide and thick to avoid IR drops. The trace between the input capacitor's higher node and
VIN as well as the trace between the input capacitor's lower node and PGND must be kept as short as possible.
Parasitic inductance on these traces must be kept as tiny as possible for proper device operation.
AVIN and AGND should be isolated from noisy signals. Route the AGND to the star ground point where no IR
drop occurs. The input cap at AVIN isolates noise. Proceed with VDD and AGND in a similar manner.
The trace between the switch node, SW, must connect directly to the inductor followed by the output capacitors,
COUT. The switch node is an aggressor. Keeping this trace short reduces noise being radiated and improves EMI
behavior. The lower node of the output capacitor, COUT, needs to connect to the star ground point. The
TPS6236x supports the point of load concept (POL). Input caps at the POL do not need to be placed closest to
the IC; they should be placed close to the POL. Route the traces between the TPS6236x's output capacitor and
the load's input capacitors direct and wide to avoid losses due to the IR drop.
Connect the sense lines to the POL. This puts into practice the remote sensing concept, allowing the device to
regulate the voltage at the POL, compensating IR drops. If possible, make a Kelvin connection to the load
device. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND,
VIN, and SW, as well as high bandwidth signals such as the I2C bus. Avoid both capacitive as well as inductive
coupling by keeping the sense lines short, direct and close to each other. Run the lines in a quiet layer. Isolate
them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is
recommended.
The PGND nodes at CIN and COUT can be connected underneath the IC at the PGND pins (star point). Make sure
that small signal traces returning to the AGND do not share the high current path at PGND to CIN and COUT.
See Figure 52 for the recommended layout.
VIN
SW
PGND
star ground point
VOUT
Figure 52. Layout Suggestion (top view) with 3225 Inductor. Overall Solution Size: 27.5mm 2
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REGISTER SETTINGS
Overview
Table 9. TPS62360 Register Settings Overview
ADDRESS
REGISTER
REGISTER (default / reset values)
RESET /
DEFAULT
STATE
READ /
WRITE
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
DIS_TS
TJEW
TJTS
EN_DISC
RAMP_PFM
0x00h
SET0
0x111111
R/W
MODE0
OV0[5:0]
0x01h
SET1
0x010111
R/W
MODE1
OV1[5:0]
0x02h
SET2
0x111111
R/W
MODE2
OV2[5:0]
0x03h
SET3
0x100001
R/W
MODE3
0x04h
Ctrl
111xxxxx
R/W
PD_EN
0x05h
Temp
xxxxx000
R/W
0x06h
RmpCtrl
000xx00x
R/W
0x07h
(Reserved)
xxxxxxxx
0x08h
Chip_ID
0x09h
Chip_ID
100000xx
OV3[5:0]
PD_VSEL0
PD_VSEL1
RMP[2:0]
R
Table 10. TPS62361B Register Settings Overview
ADDRESS
REGISTER
REGISTER (default / reset values)
RESET /
DEFAULT
STATE
READ /
WRITE
MSB
D7
LSB
D6
D5
D4
D3
0x00h
SET0
00101110
R/W
MODE0
OV0[6:0]
0x01h
SET1
01011010
R/W
MODE1
OV1[6:0]
0x02h
SET2
01000010
R/W
MODE2
OV2[6:0]
0x03h
SET3
01000010
R/W
MODE3
OV3[6:0]
0x04h
Ctrl
111xxxxx
R/W
PD_EN
0x05h
Temp
xxxxx000
R/W
0x06h
RmpCtrl
000xx00x
R/W
0x07h
(Reserved)
xxxxxxxx
0x08h
Chip_ID
0x09h
Chip_ID
100001xx
PD_VSEL0
D2
D1
D0
DIS_TS
TJEW
TJTS
EN_DISC
RAMP_PFM
PD_VSEL1
RMP[2:0]
R
Table 11. TPS62362 Register Settings Overview
ADDRESS
36
REGISTER
REGISTER (default / reset values)
RESET /
DEFAULT
STATE
READ /
WRITE
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
DIS_TS
TJEW
TJTS
EN_DISC
RAMP_PFM
0x00h
SET0
0x101110
R/W
MODE0
OV0[5:0]
0x01h
SET1
0x010111
R/W
MODE1
OV1[5:0]
0x02h
SET2
0x101011
R/W
MODE2
OV2[5:0]
0x03h
SET3
0x100001
R/W
MODE3
0x04h
Ctrl
111xxxxx
R/W
PD_EN
0x05h
Temp
xxxxx000
R/W
0x06h
RmpCtrl
000xx00x
R/W
0x07h
(Reserved)
xxxxxxxx
0x08h
Chip_ID
0x09h
Chip_ID
100010xx
OV3[5:0]
PD_VSEL0
PD_VSEL1
RMP[2:0]
R
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 12. TPS62363 Register Settings Overview
ADDRESS
REGISTER
REGISTER (default / reset values)
RESET /
DEFAULT
STATE
READ /
WRITE
MSB
D7
LSB
D6
D5
D4
D3
0x00h
SET0
01000110
R/W
MODE0
OV0[6:0]
0x01h
SET1
01010011
R/W
MODE1
OV1[6:0]
0x02h
SET2
01100100
R/W
MODE2
OV2[6:0]
0x03h
SET3
00110010
R/W
MODE3
0x04h
Ctrl
111xxxxx
R/W
PD_EN
0x05h
Temp
xxxxx000
R/W
0x06h
RmpCtrl
000xx00x
R/W
0x07h
(Reserved)
xxxxxxxx
0x08h
Chip_ID
0x09h
Chip_ID
100001xx
D2
D1
D0
DIS_TS
TJEW
TJTS
EN_DISC
RAMP_PFM
OV3[6:0]
PD_VSEL0
PD_VSEL1
RMP[2:0]
R
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Register 0x00h Description: SET0
The register settings apply by choosing SET0 ( VSEL1 = LOW, VSEL0 = LOW).
Table 13. TPS62360 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT
NAME
D7
MODE0
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET0
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET0
Default: (111111)2 = 1.4V
D4
1
D5-D0
Output voltage
D3
1
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV0[5:0]
1
D1
1
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 14. TPS62361B Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE0
0
DESCRIPTION
Operation mode for SET0
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
0
D5
1
Output voltage for SET0
Default: (0101110)2 = 0.96V
D4
0
D6-D0
Output voltage
1
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV0[6:0]
1
D1
D0
38
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 15. TPS62362 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT
NAME
D7
MODE0
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET0
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET0
Default: (101110)2 = 1.23V
D4
0
D5-D0
Output voltage
D3
1
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV0[5:0]
1
D1
1
D0
LSB
0
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 16. TPS62363 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE0
0
DESCRIPTION
Operation mode for SET0
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
0
Output voltage for SET0
Default: (1000110)2 = 1.2V
D4
0
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV0[6:0]
1
D1
D0
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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Register 0x01h Description: SET1
The register settings apply by choosing SET1 ( VSEL1 = LOW, VSEL0 = HIGH).
Table 17. TPS62360 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT
NAME
D7
MODE1
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET1
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
0
Output voltage for SET1
Default: (010111)2 = 1.0V
D4
1
D5-D0
Output voltage
D3
0
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV1[5:0]
1
D1
1
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 18. TPS62361B Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE1
0
DESCRIPTION
Operation mode for SET1
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
0
Output voltage for SET1
Default: (1011010)2 = 1.4V
D4
1
D6-D0
Output voltage
1
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV1[6:0]
0
D1
D0
40
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 19. TPS62362 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT
NAME
D7
MODE1
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET1
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
0
Output voltage for SET1
Default: (010111)2 = 1.0V
D4
1
D5-D0
Output voltage
D3
0
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV1[5:0]
1
D1
1
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 20. TPS62363 Register 0x01h Description
REGISTER ADDRESS: 0x01h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE1
0
DESCRIPTION
Operation mode for SET1
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
0
Output voltage for SET1
Default: (1010011)2 = 1.36V
D4
1
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV1[6:0]
0
D1
D0
1
LSB
1
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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Register 0x02h Description: SET2
The register settings apply by choosing SET2 ( VSEL1 = HIGH, VSEL0 = LOW).
Table 21. TPS62360 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT
NAME
D7
MODE2
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET2
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET2
Default: (111111)2 = 1.4V
D4
1
D5-D0
Output voltage
D3
1
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV2[5:0]
1
D1
1
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 22. TPS62361B Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE2
0
DESCRIPTION
Operation mode for SET2
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
0
Output voltage for SET2
Default: (1000010)2 = 1.16V
D4
0
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV2[6:0]
0
D1
D0
42
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 23. TPS62362 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT
NAME
D7
MODE2
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET2
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET2
Default: (101011)2 = 1.2V
D4
0
D5-D0
Output voltage
D3
1
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV2[5:0]
0
D1
1
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 24. TPS62363 Register 0x02h Description
REGISTER ADDRESS: 0x02h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE2
0
DESCRIPTION
Operation mode for SET2
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
1
Output voltage for SET2
Default: (1100100)2 = 1.5V
D4
0
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV2[6:0]
1
D1
D0
0
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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Register 0x03h Description: SET3
The register settings apply by choosing SET3 ( VSEL1 = HIGH, VSEL0 = HIGH).
Table 25. TPS62360 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT
NAME
D7
MODE3
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET3
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET3
Default: (100001)2 = 1.1V
D4
0
D5-D0
Output voltage
D3
0
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV3[5:0]
0
D1
0
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 26. TPS62361B Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE3
0
DESCRIPTION
Operation mode for SET3
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
1
D5
0
Output voltage for SET3
Default: (1000010)2 = 1.16V
D4
0
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV3[6:0]
0
D1
D0
44
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Table 27. TPS62362 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT
NAME
D7
MODE3
DEFAULT
MSB
DESCRIPTION
0
Operation mode for SET3
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
x
Reserved for future use
D5
1
Output voltage for SET3
Default: (100001)2 = 1.1V
D4
0
D5-D0
Output voltage
D3
0
00 0000
770 mV
00 0001
780 mV
00 0010
790 mV
...
...
11 1111
1400 mV
D2
OV3[5:0]
0
D1
0
D0
LSB
1
VOUT = (xx xxxx)2 × 10mV + 770 mV
Table 28. TPS62363 Register 0x03h Description
REGISTER ADDRESS: 0x03h Read/Write
BIT
NAME
DEFAULT
MSB
D7
MODE3
0
DESCRIPTION
Operation mode for SET3
0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6
0
D5
1
Output voltage for SET3
Default: (0110010)2 = 1.0V
D4
1
D6-D0
Output voltage
0
000 0000
500 mV
000 0001
510 mV
000 0010
520 mV
...
...
111 1111
1770 mV
D3
D2
OV3[6:0]
0
D1
D0
1
LSB
0
VOUT = (xxx xxxx)2 × 10mV + 500 mV
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Register 0x04h Description: Ctrl
Table 29. TPS6236x Register 0x04h Description
REGISTER ADDRESS: 0x04h Read / Write
BIT
NAME
DEFAULT
MSB
DESCRIPTION
D7
PD_EN
1
EN internal pull down resistor
0 = disabled
1 = enabled
D6
PD_VSEL0
1
VSEL0 internal pull down resistor
0 = disabled
1 = enabled
D5
PD_VSEL1
1
VSEL1 internal pull down resistor
0 = disabled
1 = enabled
D4
x
Reserved for future use
D3
x
Reserved for future use
D2
x
Reserved for future use
x
Reserved for future use
x
Reserved for future use
D1
D0
LSB
Register 0x05h Description: Temp
Table 30. TPS6236x Register 0x05h Description
REGISTER ADDRESS: 0x05h Read/Write
BIT
NAME
D7
DEFAULT
MSB
DESCRIPTION
x
Reserved for future use
D6
x
Reserved for future use
D5
x
Reserved for future use
D4
x
Reserved for future use
D3
x
Reserved for future use
D2
DIS_TS
0
Disable temperature shutdown feature
0 = Temperature shutdown enabled
1 = Temperature shutdown disabled (not recommended)
D1
TJEW
0
TJ early warning bit
0 = TJ < 120°C (typ)
1 = TJ ≥ 120°C (typ)
D0
TJTS
0
TJ temperature shutdown bit
0 = die temperature within the valid range
1 = temperature shutdown was triggered
LSB
46
Bit needs to be reset after it has been latched.
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
Register 0x06h Description: RmpCtrl
Table 31. TPS6236x Register 0x06h Description
REGISTER ADDRESS: 0x06h Read/Write
BIT
NAME
DEFAULT
MSB
D7
D6
DESCRIPTION
Output voltage ramp timing
0
0
RMP[2:0]
D7-D5
Slope
000
32 mV / µs
001
16 mV / µs
010
8 mV / µs
...
...
110
0.5 mV / µs
111
0.25 mV / µs
ΔVOUT
mV
1
= 32
Δt
μs 2(RMP[2-0] )2
D5
0
D4
x
Reserved for future use
D3
x
Reserved for future use
0
Active output capacitor discharge at shutdown
0 = disabled
1 = enabled
0
Defines the ramp behavior if the device is in Power Save (PFM) mode
0 = output cap will be discharged by the load
1 = output voltage will be forced to follow the ramp down slope
x
Reserved for future use
EN_DISC
D2
D1
RAMP_PFM
D0
LSB
Register 0x07h Description: (Reserved)
Table 32. TPS6236x Register 0x07h Description
REGISTER ADDRESS: 0x07h
BIT
D7
NAME
DEFAULT
x
Reserved for future use
D6
x
Reserved for future use
D5
x
Reserved for future use
D4
x
Reserved for future use
D3
x
Reserved for future use
D2
x
Reserved for future use
D1
x
Reserved for future use
x
Reserved for future use
D0
MSB
DESCRIPTION
LSB
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Register 0x08h, 0x09h Description Chip_ID:
Table 33. TPS6236x Register 0x08h and 0x09h Description
REGISTER ADDRESS: 0x08h, 0x09 Read
BIT
D7
NAME
DEFAULT
MSB
D6
0
D5
0
D4
0
D3
x
D2
x
D1
x
D0
x
LSB
48
DESCRIPTION
1
Vendor ID
D3-D2
Part number ID
00
TPS62360
01
TPS62361B
10
TPS62362
11
TPS62363
D1-D0
Chip revision ID
00
Rev. 1
01
Rev. 2
10
Rev. 3
11
Rev. 4
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SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012
PACKAGE SUMMARY
CHIP SCALE PACKAGE
(TOP VIEW)
Code:
TIYMLLLLS
XXXXXXXXX
E
• TI — Texas Instruments
• YM — Year Month date code
• LLLL — Lot trace code
• S — Assembly site code
• XXXXXXXX — Part number
• TPS62360 = TPS62360
• TPB62361 = TPS62361B
• TPS62362 = TPS62362
• TPS62363 = TPS62363
A1
D
Figure 53. Package Marking and Dimensions
CHIP SCALE PACKAGE DIMENSIONS
The TPS6236x device is available in a 16-bump chip scale package (YZH, NanoFree™). The package
dimensions are given as:
• D = 2.076mm (+/- 0.03mm)
• E = 2.076mm (+/- 0.03mm)
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REVISION HISTORY
Changes from Revision B (March 2012) to Revision C
Page
•
Changed solution size of approximately 27.5 mm2 to 25 mm2 ............................................................................................. 1
•
Changed application schematic ............................................................................................................................................ 1
•
Changed layout diagram ....................................................................................................................................................... 1
•
Changed TPS62362 output voltage preset from 1.10V to 1.00V in ORDERING INFORMATION ....................................... 2
•
Changed continuous output current in RECOMMENDED OPERATING CONDITIONS ...................................................... 3
•
Added rising and falling signal transition time at EN, VSELx to RECOMMENDED OPERATING CONDITIONS,
removed from from ELECTRICAL CHARACTERISTICS ..................................................................................................... 3
•
Changed Figure 40 ............................................................................................................................................................. 26
•
Changed Figure 45 ............................................................................................................................................................. 29
•
Changed Figure 46 ............................................................................................................................................................. 29
•
Changed Figure 47 ............................................................................................................................................................. 29
•
Changed I2C REGISTER RESET information .................................................................................................................... 30
•
Added Figure 48 ................................................................................................................................................................. 30
•
Changed CIN = 4.7µF to 22µF to CIN = 10µF to 22µF in INPUT CAPACITOR SELECTION ............................................. 30
•
Changed optional low pass filter in DECOUPLING CAPACITORS AT AVIN, VDD ........................................................... 31
•
Changed Table 8 (updated list of recommended Inductors) .............................................................................................. 32
•
Changed OUTPUT CAPACITOR SELECTION description ................................................................................................ 32
•
Changed OUTPUT FILTER DESIGN description ............................................................................................................... 32
•
Changed PCB LAYOUT description ................................................................................................................................... 34
50
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62360YZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62360
TPS62360YZHT
ACTIVE
DSBGA
YZH
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62360
TPS62361BYZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPB62361
TPS62361BYZHT
ACTIVE
DSBGA
YZH
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPB62361
TPS62362YZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62362
TPS62362YZHT
ACTIVE
DSBGA
YZH
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62362
TPS62363YZHR
ACTIVE
DSBGA
YZH
16
3000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62363
TPS62363YZHT
ACTIVE
DSBGA
YZH
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
TPS62363
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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