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TPS62366AYZHR

TPS62366AYZHR

  • 厂商:

    BURR-BROWN(德州仪器)

  • 封装:

    DSBGA16

  • 描述:

    TPS62366A 4A PROCESSOR SUPPLY WI

  • 数据手册
  • 价格&库存
TPS62366AYZHR 数据手册
TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 4A Processor Supply with I2C Compatible Interface and Remote Sense Check for Samples: TPS62366A, TPS62366B FEATURES DESCRIPTION • • The TPS62366x is a high-frequency synchronous step down dc-dc converter optimized for batterypowered portable applications for a small solution size. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported. The device provides up to 4A peak load current, operating at 2.5MHz typical switching frequency. 1 2 • • • • • • 4A Peak Output Current Highest Efficiency: – Low RDS,on Switch and Active Rectifier – Power Save Mode for Light Loads I2C High Speed Compatible Interface Programmable Output Voltage for Digital Voltage Scaling – 0.5V to 1.77V, 10mV Steps Excellent DC/AC Output Voltage Regulation – Differential Load Sensing – Precise DC Output Voltage Accuracy – DCS-Control™ Architecture for Fast and Precise Transient Regulation Multiple Robust Operation/Protection Features: – Soft Start – Programmable Slew Rate at Voltage Transition – Over Temperature Protection – Input Under Voltage Detection / Lock Out Available in 16-Bump, 2mm x 2mm NanoFree™ Package Low External Device Count: < 25mm2 Solution Size • • • Application Processors and DSPs Power Supply Dynamic Voltage Scaling, SmartReflex™ Compliant Processor Supply Cell Phones, Smart Phones, Feature Phones Tablets, PDAs, MIDs, Netbooks TPS62366x 2.5V .. 5.5V VIN VIN AVIN EN 10µF 0.1µF 0.1µF SCL SDA VSEL The devices focus on a high output voltage accuracy. The differential sensing and the DCS-Control™ architecture achieve precise static and dynamic, transient output voltage regulation. The TPS62366x device offers high efficiency step down conversion. The area of highest efficiency is extended towards low output currents to increase the efficiency while the processor is operating in retention mode, as well as towards highest output currents increasing the battery on-time. The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of less than 25mm2. 1mm 0.47uH / 1µH SW SW COUT SENSE+ VDD The TPS62366x supports low-voltage DSPs and processor cores in smart-phones and handheld computers including latest submicron processes. A dedicated hardware input pin allows simple transitions to performance operating points and retention modes of processors. The robust architecture and multiple safety features allow perfect system integration. APPLICATIONS • The device converts to an output voltage range of 0.5V to 1.77V, programmable via I2C interface in 10mV steps. Dedicated inputs allow fast voltage transition to address processor performance operating points. LOAD SENSEPGND PGND AGND PGND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DCS-Control, NanoFree, SmartReflex are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION DEVICE SPECIFIC FEATURES (1) PART NUMBER PACKAGE MARKING PACKAGE Output Voltage Range Output Voltage Presets TPS62366A (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 1.20V, 1.16V TPS62366B (3) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.5V to 1.77V, 10mV Steps 0.96V, 1.40V (1) (2) (3) Contact the factory to check availability of other output voltage or feature versions. The YZH package is available in tape and reel. Add R suffix (TPS62366AYZHR) to order quantities of 3000 parts per reel, T suffix for 250 parts per reel (TPS62366AYZHT). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on ti.com. The YZH package is available in tape and reel. Add R suffix (TPS62366BYZHR) to order quantities of 3000 parts per reel, T suffix for 250 parts per reel (TPS62366BYZHT). For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage range (2) Continuous RMS VIN / SW current per Pin (3) Temperature range ESD rating (4) MAX VIN, AVIN, SW pin –0.3 7 V EN, VSEL, SENSE+ –0.3 (VAVIN+0.3V) V SENSE– –0.3 0.3 V SCL, SDA –0.3 (VDD+0.3V) V VDD –0.3 TA < 85°C (2) (3) (4) 2 3.6 V 1275 mA Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C Machine model 200 V Charge device model 500 V 2 kV Human body model (1) UNIT MIN Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. In order to be consistent with the TI reliability requirement for the silicon chips (100K Power-On-Hours at 105°C junction temperature), the current should not continuously exceed 2550mA in the VIN pins and 2550mA in the SW pins so as to prevent electromigration failure in the solder. See THERMAL AND DEVICE LIFETIME INFORMATION. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF capacitor discharged directly into each pin. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 THERMAL INFORMATION TPS62366x THERMAL METRIC (1) YZH UNITS 16 PINS Junction-to-ambient thermal resistance (2) θJA 94.8 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 60 ψJT Junction-to-top characterization parameter (5) 3.2 ψJB Junction-to-board characterization parameter (6) 57 θJCbot Junction-to-case (bottom) thermal resistance (7) n/a (1) (2) (3) (4) (5) (6) (7) 25 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX IOUT ≤ 2.5A 2.5 5.5 IOUT ≥ 2.5A 2.8 5.5 UNIT VIN Input voltage range, VIN IOUT,avg Continuous output current (1) trf Rising and falling signal transition time at EN, VSEL TA Operating ambient temperature (2) –40 85 °C TJ Operating junction temperature –40 150 °C (1) (2) 2.5 30 V A mV/µs Refer to the APPLICATION INFORMATION section for further information. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 3 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT VIN Input voltage range at VIN, AVIN VDD I2C and registers supply voltage range ISD(AVIN) Shutdown current into AVIN EN = LOW, VDD = 0V ISD(VIN) Shutdown current into VIN EN = LOW, VDD = 0V ISD(VDD) Shutdown current into VDD EN = LOW, I2C bus idle 2.5 5.5 1.15 3.6 V 0.65 5 µA 0.5 1 µA 1 3 µA TA = 25°C TA = 85°C V 0.01 µA 56 µA Forced PWM mode (Test Mode) 180 µA Input voltage falling, EN = High 2.3 EN = HIGH, IOUT = 0mA, not switching PFM mode IQ Operating quiescent current into (AVIN + VIN) VUVLO Under voltage lock out at AVIN Input voltage rising, EN = Low 1.3 V VUVLO,HYST(AVIN) Under voltage lock out hysteresis at AVIN Input voltage rising 110 mV VDD,UVLO Under voltage lock out at VDD Input voltage falling VUVLO,HYST(VDD) Under voltage lock out hysteresis at VDD Input voltage rising IVDD 0.7 1.1 50 I2C not active Input current at VDD 0.92 2.45 0.02 V mV 0 I2C active (r/w) V µA 1 mA LOGIC INTERFACE VIH High-level input voltage at EN, VSEL VIL Low-level input voltage at EN, VSEL VIH,I2C High-level input voltage at SCL, SDA VIL,I2C Low-level input voltage at SCL, SDA ILKG Logic input leakage current at EN, VSEL, SDA, SCL Internal pulldown resistors disabled 0.05 µA RPD Pull down resistance at EN, VSEL Internal pulldown resistors enabled 300 kΩ I2C clock frequency 1.2 V 0.4 0.7x VDD V V 0.3x VDD V Fast mode 400 kHz High speed mode 3.4 MHz 75 mΩ POWER SWITCH RDS(on) ILIMF High side MOSFET switch VIN = 3.6V Low side MOSFET switch VIN = 3.6V 25 32 50 mΩ High side MOSFET forward current limit VIN = 3.6V 4.3 4.9 5.5 A Low side MOSFET forward current limit VIN = 3.6V 3.9 4.4 4.9 A 2.2 2.5 2.9 Low side MOSFET negative current limit VIN = 3.6V, PWM mode fSW Nominal switching frequency PWM mode TJEW TJSD TJSD,HYST Thermal shutdown hysteresis tON,min Minimum on time 4 25 44 A 2.5 MHz Die temperature early warning 120 °C Thermal shutdown 150 °C 20 °C 120 ns Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.5 1.77 V -0.5% +0.5% OUTPUT VOUT Output voltage range 10mV increments VIN = 2.8V .. 5.5V VOUT = 0.5V .. 1.77V Output voltage accuracy No load, Forced PWM, VOUT = [0.77V, 1.3V] TJ = 85°C No load, Forced PWM, TJ = -40 .. 150°C Line regulation IOUT = 1A, forced PWM Load regulation VOUT = 1.2V, forced PWM tStart Start-up time Time from active EN to VOUT = 1.4V, COUT < 100µF, RMP[2:0] = 000, IOUT = 0mA RSense Input resistance between Sense+, Sense– Ramp timer -1% ±0.5% +1% < 0.1 %/V < 0.05 %/A 1 ms 2.2 RMP[2:0] = 000 32 RMP[2:0] = 001 16 RMP[2:0] = 010 8 RMP[2:0] = 011 4 RMP[2:0] = 100 2 RMP[2:0] = 101 1 RMP[2:0] = 110 0.5 RMP[2:0] = 111 0.25 MΩ mV/µs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 5 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com I2C INTERFACE TIMING REQUIREMENTS (1) PARAMETER f(SCL) SCL clock frequency Bus free time between a STOP and START condition tBUF MAX UNIT Standard mode TEST CONDITIONS 100 kHz Fast mode 400 kHz High-speed mode (write operation), CB – 100 pF max 3.4 MHz High-speed mode (read operation), CB – 100 pF max 3.4 MHz High-speed mode (write operation), CB – 400 pF max 1.7 MHz High-speed mode (read operation), CB – 400 pF max 1.7 MHz Standard mode 4.7 μs Fast mode 1.3 μs 4 μs Fast mode 600 ns High-speed mode 160 ns Standard mode 4.7 μs Fast mode 1.3 μs High-speed mode, CB – 100 pF max 160 ns High-speed mode, CB – 400 pF max 320 ns 4 μs Standard mode tHD, tSTA tLOW Hold time (repeated) START condition Low period of the SCL clock Standard mode tHIGH High period of the SCL clock tSU, tSTA tSU, tDAT Setup time for a repeated START condition Data setup time Fast mode 600 ns High-speed mode, CB – 100 pF max 60 ns High-speed mode, CB – 400 pF max 120 ns Standard mode 4.7 μs Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns High-speed mode tHD, tDAT tRCL Data hold time Rise time of SCL signal tRCL1 Rise time of SCL signal after a repeated START condition and after an acknowledge bit tRDA (1) 6 Fall time of SCL signal Rise time of SDA signal 10 ns Standard mode 0 3.45 μs Fast mode 0 0.9 μs High-speed mode, CB – 100 pF max 0 70 ns High-speed mode, CB – 400 pF max 0 150 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF max 10 40 ns High-speed mode, CB – 400 pF max 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns 10 80 ns High-speed mode, CB – 100 pF max High-speed mode, CB – 400 pF max tFCL MIN 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF max 10 40 ns High-speed mode, CB – 400 pF max 20 80 ns Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF max 10 80 ns High-speed mode, CB – 400 pF max 20 160 ns S/M = standard mode; F/M = fast mode Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 I2C INTERFACE TIMING REQUIREMENTS(1) (continued) PARAMETER tFDA TEST CONDITIONS Fall time of SDA signal MIN MAX UNIT Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.1 CB 300 ns High-speed mode, CB – 100 pF max 10 80 ns High-speed mode, CB – 400 pF max 20 160 tSU, tSTO Setup time for STOP condition CB Capacitive load for SDA and SCL ns 4 μs Fast mode 600 ns High-speed mode 160 Standard mode ns 400 pF I2C TIMING DIAGRAMS SDA tsu;DAT tf tr tLOW tf thd;STA thd;STA tBUF tr SCL thd;STA tsu;STO thd;DAT HIGH Sr S P S Figure 1. Serial Interface Timing for F/S Mode tfDA Sr P trDA SDAH thd;DAT tsu;STA tsu;DAT thd;STA tsu;STO SCLH Sr tfCL tfCL1 See Note A tHIGH tLOW tfCL tLOW trCL1 tHIGH See Note A = MCS Current Source Pull-Up = R(P) Resistor Pull-Up Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit. Figure 2. Serial Interface Timing for H/S Mode Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 7 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS YZH Package (Top View) YZH Package (Bottom View) AVIN AGND VIN VIN A1 A2 A3 A4 SENSE+ EN SW SW B1 B2 B3 B4 SENSE– VSEL PGND PGND C1 C2 C3 C4 VDD SDA SCL PGND D1 D2 D3 D4 A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. AVIN A1 I Analog Supply Voltage Input. AGND A2 – Analog Ground Connection. EN B2 I Device Enable Logic Input. Logic HIGH enables the device, logic LOW disables the device and turns it into shutdown. The pin must be terminated to either HIGH or LOW if the internal pull down resistor is deactivated. VDD D1 I I2C Logic and Registers supply voltage. For resetting the internal registers, this connection must be pulled below its UVLO level. SCL D3 I/O I2C clock signal. SDA D2 I/O I2C data signal. VSEL C2 I Output Settings Selection Logic Input. Predefined register settings can be chosen for setting output voltage and mode. The pin must be terminated to logic HIGH or LOW if the internal pull down resistor is deactivated. SW B3 – Inductor connection B4 SENSE+ B1 I Positive Output Voltage Remote Sense. Must be connected closest to the load supply node. SENSE– C1 I Negative Output Voltage Remote Sense. Must be connected closest to the load ground node. VIN A4 I Power Supply Voltage Input. – Power Ground Connection. A3 PGND C3 C4 D4 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 FUNCTIONAL BLOCK DIAGRAM ramp Softstart AVIN AGND direct control & compensation comparator error amplifier Analog Circuit Supply Differential Sense SENSE+ SENSE- Thermal Shutdown DCS-CONTROL TM REF EN VDD SCL RDISCHARGE I2C Interface High Side Current Limit 2 VIN SDA Bandgap Control Logic High Side P-MOS Gate Driver 2 SW Under Voltage Shutdown Low Side N-MOS PGND 3 VSEL Low Side Current Limit Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 9 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE η VOUT = 1.5V Figure 3 vs. Output Current (Power Save and VOUT = 1.2V Forced PWM Mode) VOUT = 0.9V Figure 4 VOUT = 0.6V Figure 6 IOUT = 4000mA Figure 7 IOUT = 1000mA Figure 8 Efficiency vs. Input Voltage (Power Save and Forced PWM Mode) VO DC Output Voltage IOUT = 100mA Figure 9 IOUT = 10mA Figure 10 VOUT = 1.5V, TA = 25°C Figure 11 vs. Output Current (Power Save and VOUT = 1.2V, TA = 25°C Forced PWM Mode) VOUT = 0.9V, TA = 25°C Figure 12 VOUT = 0.6V, TA = 25°C Figure 14 VOUT = 0.5V, IOUT = 0mA Figure 15 VOUT = 1.5V, IOUT = 0mA Figure 16 VOUT = 0.5V, IOUT = 1000mA Figure 17 VOUT = 1.5V, IOUT = 1000mA Figure 18 IOUT = 10mA Figure 19 IOUT = 200mA Figure 20 IOUT = 1000mA Figure 21 IOUT = 4000mA Figure 22 IOUT = 10mA Figure 23 IOUT = 200mA Figure 24 IOUT = 1000mA Figure 25 IOUT = 4000mA Figure 26 IOUT = 0mA Figure 27 IOUT = 1000mA Figure 28 IOUT = 50mA to 200mA Figure 29 IOUT = 200mA to 1000mA Figure 30 IOUT = 2500mA to 4000mA Figure 31 IOUT = 50mA to 200mA Figure 32 IOUT = 200mA to 1000mA Figure 33 IOUT = 2500mA to 4000mA Figure 34 VIN = 3.6 to 4.2V, IOUT = 3500mA Figure 35 Into No Load Startup Into Load L = 1μH Switching Wave forms L = 0.47μH Output Voltage Ramp Control Figure 5 Transition 0.5V .. 1.5V L = 1μH Load Transient Response L = 0.47μH Line Transient Response Figure 13 ISD(VIN), ISD(AVIN) Shutdown Current at AVIN and VIN vs. Input Voltage TA = [-40°C, 25°C, 125°C] Figure 36 IQ Operating Quiescent Current vs. Input Voltage TA = [-40°C, 25°C, 125°C], auto PFM/PWM Figure 37 fSW Switching Frequency vs. Output Current VOUT = 1.2V Figure 38 ILIM Current Limit vs. Input Voltage IOUT Maximum DC Output current vs. Input Voltage 10 Figure 39 VOUT = [0.6V, 0.9V, 1.2V, 1.5V] Submit Documentation Feedback Figure 40 Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.2V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.5V TPS62366x VOUT = 1.5V TA = 25°C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 TPS62366x VOUT = 1.2V TA = 25°C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 60 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 10 0 1m 4 10m 100m Output Current (A) 1 G002 Figure 3. Figure 4. EFFICIENCY vs OUTPUT CURRENT VOUT = 0.9V EFFICIENCY vs OUTPUT CURRENT VOUT = 0.6V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) G001 TPS62366x VOUT = 0.9V TA = 25°C 50 40 30 20 10 0 1m 10m 100m Output Current (A) 1 60 TPS62366x VOUT = 0.6V TA = 25°C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 20 10 4 4 0 1m 10m 100m Output Current (A) 1 G003 Figure 5. 4 G004 Figure 6. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 11 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs INPUT VOLTAGE IOUT = 1A 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) EFFICIENCY vs INPUT VOLTAGE IOUT = 4A 50 40 30 0 2.5 40 30 20 10 50 20 PWM, VOUT = 0.9V PWM, VOUT = 1.2V PWM, VOUT = 1.5V TPS62366x IOUT = 4A TA = 25°C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 10 0 2.5 5.5 PWM, VOUT = 0.9V PWM, VOUT = 1.2V PWM, VOUT = 1.5V TPS62366x IOUT = 1A TA = 25°C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 G006 Figure 8. EFFICIENCY vs INPUT VOLTAGE IOUT = 100mA EFFICIENCY vs INPUT VOLTAGE IOUT = 10mA 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) G005 Figure 7. 50 40 30 10 0 2.5 TPS62366x IOUT = 100mA TA = 25°C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 50 40 30 Forced PWM, VOUT = 0.9V Forced PWM, VOUT = 1.2V Forced PWM, VOUT = 1.5V Auto PFM/PWM, VOUT = 0.9V Auto PFM/PWM, VOUT = 1.2V Auto PFM/PWM, VOUT = 1.5V 20 Forced PWM, VOUT = 0.9V Forced PWM, VOUT = 1.2V Forced PWM, VOUT = 1.5V Auto PFM/PWM, VOUT = 0.9V Auto PFM/PWM, VOUT = 1.2V Auto PFM/PWM, VOUT = 1.5V 20 10 5.5 0 2.5 TPS62366x IOUT = 10mA TA = 25°C 3.0 3.5 4.0 4.5 Input Voltage (V) G007 Figure 9. 12 5.0 5.5 G008 Figure 10. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 TYPICAL CHARACTERISTICS (continued) DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 1.5V DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 1.2V 1.55 1.24 1.53 1.23 1.52 1.22 DC Output Voltage (V) DC Output Voltage (V) 1.54 1.25 TPS62366x VOUT = 1.5V TA = 25°C 1.51 1.50 1.49 1.48 1.46 1.45 1m 10m 100m Output Current (A) 1 1.21 1.20 1.19 1.18 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 1.47 TPS62366x VOUT = 1.2V TA = 25°C Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 1.17 1.16 1.15 1m 4 10m 100m Output Current (A) 1 G009 G010 Figure 11. Figure 12. DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 0.9V DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 0.6V 0.95 0.65 TPS62366x VOUT = 0.9V TA = 25°C 0.64 0.93 0.63 0.92 0.62 DC Output Voltage (V) DC Output Voltage (V) 0.94 0.91 0.90 0.89 0.88 0.86 10m 100m Output Current (A) 1 TPS62366B VOUT = 0.6V TA = 25°C 0.61 0.60 0.59 0.58 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 0.87 0.85 1m 4 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.8V Auto PFM/PWM, VIN = 3.6V Auto PFM/PWM, VIN = 4.2V 0.57 0.56 4 0.55 1m 10m 100m Output Current (A) 1 G011 Figure 13. 4 G012 Figure 14. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 13 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) STARTUP INTO NO LOAD VOUT = 0.5V STARTUP INTO NO LOAD VOUT = 1.5V VOUT 500mV/Div EN 2V/DIV EN 2V/DIV VOUT 200mV/Div TPS62366A RAMP[2:0] = 000 (32mV/μs) IOUT = 0A VIN = 3.6V TPS62366x RAMP[2:0] = 000 (32mV/μs) IOUT = 0A VIN = 3.6V Inductor Current 200mA/Div Inductor Current 500mA/Div Time Base - 20μs/Div Time Base - 20μs/Div G013 G014 Figure 15. Figure 16. STARTUP INTO LOAD VOUT = 0.5V STARTUP INTO LOAD VOUT = 1.5V EN 2V/DIV VOUT 500mV/Div EN 2V/DIV VOUT 200mV/Div TPS62366x RAMP[2:0] = 000 (32mV/μs) IOUT = 1A VIN = 3.6V TPS62366x RAMP[2:0] = 000 (32mV/μs) IOUT = 1A VIN = 3.6V Inductor Current 500mA/Div Inductor Current 500mA/Div Time Base - 20μs/Div Time Base - 20μs/Div G015 Figure 17. 14 G016 Figure 18. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 TYPICAL CHARACTERISTICS (continued) SWITCHING WAVE FORMS IOUT = 10mA TPS62366x IOUT = 10mA (PFM) VOUT 20mV/Div w/ 1.2V Offset SWITCHING WAVE FORMS IOUT = 200mA VIN = 3.6V VOUT = 1.2V L = 1μ H TPS62366x IOUT = 200mA VOUT 20mV/Div w/ 1.2V Offset VIN = 3.6V VOUT = 1.2V L = 1μ H SW Pin 2V/Div SW Pin 2V/Div Inductor Current 200mA/Div Inductor Current 200mA/Div Time Base - 20μs/Div Time Base - 1μs/Div G017 G018 Figure 19. Figure 20. SWITCHING WAVE FORMS IOUT = 1A SWITCHING WAVE FORMS IOUT = 4A VOUT 20mV/Div w/ 1.2V Offset VOUT 20mV/Div w/ 1.2V Offset SW Pin 2V/Div SW Pin 2V/Div Inductor Current 500mA/Div Inductor Current 2A/Div TPS62366x IOUT = 1A VIN = 3.6V VOUT = 1.2V L = 1μ H Time Base - 1μs/Div TPS62366x IOUT = 4A VIN = 3.6V VOUT = 1.2V L = 1μH Time Base - 1μs/Div G020 G019 Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 15 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING WAVE FORMS IOUT = 10mA TPS62366x IOUT = 10mA (PFM) COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF VOUT 20mV/Div w/ 1.2V Offset SWITCHING WAVE FORMS IOUT = 200mA VIN = 3.6V VOUT = 1.2V L = 0.47μH TPS62366x IOUT = 200mA (PFM) COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF VIN = 3.6V VOUT = 1.2V L = 0.47μH VOUT 20mV/Div w/ 1.2V Offset SW Pin 2V/Div SW Pin 2V/Div Inductor Current 200mA/Div Inductor Current 200mA/Div Time Base - 20μs/Div Time Base - 1μs/Div G037 G038 Figure 23. Figure 24. SWITCHING WAVE FORMS IOUT = 1A SWITCHING WAVE FORMS IOUT = 4A TPS62366x IOUT = 1A COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF VIN = 3.6V VOUT = 1.2V L = 0.47μH VOUT 20mV/Div w/ 1.2V Offset VOUT 20mV/Div w/ 1.2V Offset SW Pin 2V/Div SW Pin 2V/Div Inductor Current 2A/Div Inductor Current 1A/Div TPS62366x IOUT = 4A VIN = 3.6V VOUT = 1.2V L = 0.47μH COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF Time Base - 1μs/Div Time Base - 1μs/Div G039 Figure 25. 16 G040 Figure 26. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE RAMP CONTROL NO LOAD OUTPUT VOLTAGE RAMP CONTROL IOUT = 1A VSEL 2V/Div VSEL 2V/Div VOUT 500mV/Div VOUT 500mV/Div TPS62366x RAMP[2:0] = 000 (32mV/μs) IOUT = 0A VIN = 3.6V VOUT = 0.5V to 1.5V Inductor Current 500mA/Div Inductor Current 500mA/Div TPS62366x RAMP[2:0] = 000 (32mV/μs) IOUT = 1A VIN = 3.6V VOUT = 0.5V to 1.5V Time Base - 10μs/Div Time Base - 10μs/Div G021 G022 Figure 27. Figure 28. LOAD TRANSIENT RESPONSE IOUT RANGE: 50mA to 200mA LOAD TRANSIENT RESPONSE IOUT RANGE: 200mA to 1A TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs L = 1μ H VOUT 20mV/Div w/ 1.2V Offset TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs L = 1μ H VOUT 20mV/Div w/ 1.2V Offset ILOAD 200mA/Div ILOAD 1A/Div Inductor Current 1A/Div Inductor Current 500mA/Div Time Base - 100μs/Div Time Base - 100μs/Div G023 Figure 29. G024 Figure 30. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 17 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE IOUT RANGE: 2.5A to 4A LOAD TRANSIENT RESPONSE IOUT RANGE: 50mA to 200mA TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs L = 1μ H VOUT 50mV/Div w/ 1.2V Offset TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF L = 0.47μH VOUT 20mV/Div w/ 1.2V Offset ILOAD 1A/Div w/ 2.5A Offset ILOAD 200mA/Div Inductor Current 500mA/Div Inductor Current 2A/Div Time Base - 100μs/Div Time Base - 100μs/Div G025 G041 Figure 31. Figure 32. LOAD TRANSIENT RESPONSE IOUT RANGE: 200mA to 1A LOAD TRANSIENT RESPONSE IOUT RANGE: 2.5A to 4A TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF L = 0.47μH VOUT 20mV/Div w/ 1.2V Offset TPS62366x VIN = 3.6V VOUT = 1.2V trise = tfall = 5μs COUT = 2 ´ 10μF CLOAD = 3 ´ 22μF L = 0.47μH VOUT 50mV/Div w/ 1.2V Offset ILOAD 1A/Div w/ 2.5A Offset ILOAD 1A/Div Inductor Current 1A/Div Inductor Current 2A/Div Time Base - 100μs/Div Time Base - 100μs/Div G043 G042 Figure 33. 18 Figure 34. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 TYPICAL CHARACTERISTICS (continued) SHUTDOWN CURRENT vs INPUT VOLTAGE LINE TRANSIENT RESPONSE VIN RANGE: 4.2V to 3.6V TPS62366x 100 ILOAD = 3500mA VOUT = 1.2V AVIN, TA = −40°C AVIN, TA = 25°C AVIN, TA = 125°C VIN 500mV/Div w/ 3.6V Offset VIN, TA = −40°C VIN, TA = 25°C VIN, TA = 125°C Shutdown Current (µA) 10 VOUT 50mV/Div w/ 1.18V Offset ILOAD 500mA/Div w/ 3A Offset Inductor Current 2A/Div 1 0.1 0.01 tVINleading-edge = tVINfalling-edge = 5μs 0.001 2.5 Time Base - 200μs/Div 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 G026 G027 Figure 35. Figure 36. OPERATING QUIESCENT CURRENT INTO AVIN + VIN vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 100 10000 TPS62366x EN = HIGH 1000 Switching Frequency (kHz) Quiescent Current (mA) 10 Forced PFM/PWM, TA = −40°C Forced PFM/PWM, TA = 25°C Forced PFM/PWM, TA = 125°C Auto PFM/PWM, TA = −40°C Auto PFM/PWM, TA = 25°C Auto PFM/PWM, TA = 125°C 1 100 TPS62366x VOUT = 1.2V VIN = 3.6V 10 0.1 1 Forced PWM Auto PFM/PWM with 0.47µH Inductor Auto PFM/PWM with 1µH Inductor 0.01 2.5 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 5.5 0.1 0.0001 0.001 0.01 0.1 Output Current (mA) 1 G028 Figure 37. 4 G029 Figure 38. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 19 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) FET CURRENT LIMIT vs INPUT VOLTAGE MAXIMUM DC OUTPUT CURRENT vs INPUT VOLTAGE 6 5500 5000 5 4000 Output Current (A) FET Current Limit (mA) 4500 3500 3000 2500 4 3 TPS62366x IOUT,MAX = IOUT (VOUT − 2%) 2 2000 1500 1000 2.5 TPS62366x TA = 25°C 3.0 3.5 4.0 4.5 Input Voltage (V) 5.0 VOUT = 0.6V, TA = 25°C VOUT = 0.9V, TA = 25°C VOUT = 1.2V, TA = 25°C VOUT = 1.5V, TA = 25°C 1 High Side PMOS Current Limit Low Side NMOS Current Limit Negative NMOS Current Limit 5.5 0 2.5 3.0 3.5 4.0 4.5 Input Voltage (V) G030 Figure 39. 20 5.0 5.5 G031 Figure 40. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 PARAMETER MEASUREMENT INFORMATION TPS62366x VIN C2 L VOUT SW SW C4 LOAD VIN VIN AVIN EN SENSE+ C1 VDD CL SENSE– SCL SDA VDD VSEL PGND PGND AGND PGND C3 Table 2. List of Components REFERENCE DESCRIPTION MANUFACTURER SETUP TPS62366x 4A Processor Supply with I2C Compatible Interface and Remote Sense, 2.076 mm x 2.076 mm x 0.625mm Texas Instruments All Typical Characteristics Figures 3-40 C1, C3 0.1 μF, Ceramic, 10V, X5R Standard C2 10 μF, Ceramic, 6.3V, X5R Standard L 1 μH, 4 mm x 4 mm x 2.1 mm C4 10 μF, Ceramic, 6.3V, X5R CL Load Capacitors, 2x10 μF + 4.7μF, Ceramic, 6.3V, X5R Coilcraft (XFL4020-102ME1.0) 1 μH Setup: Typical Characteristics Standard Figures 3-22, 27- 31, 36-40 Standard C4 2 x 10 μF, Ceramic, 6.3V, X5R Standard CL Load Capacitors, 3x22 μF,Ceramic, 6.3V, X5R Standard L 0.47 μH, 4 mm x 4 mm x 1.5 mm Coilcraft (XFL4015-471MEC) 0.47 μH Setup: Typical Characteristics Figures 23-26, 32-34 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 21 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com DETAILED DESCRIPTION The TPS62366x are a family of high-frequency synchronous step down dc-dc converter optimized for batterypowered portable applications. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported. The device provides up to 4A peak load current, operating at 2.5MHz typical switching frequency. The devices convert to an output voltage range of 0.5V to 1.77V, programmable via I2C interface in 10mV steps. The TPS62366x supports low-voltage DSPs and processor cores in smart-phones and handheld computers, including latest submicron processes and their retention modes and addresses digital voltage scaling technologies such as SmartReflex™. Output Voltages and Modes can be fully programmed via I2C. To address different performance operating points and/or startup conditions, the device offers two output voltage / mode presets which can be chosen via a dedicated VSEL pin allowing simple and zero latency output voltage transition. The devices focus on a high output voltage accuracy. The fully differential sensing and the DCS-Control™ architecture achieve precise static and dynamic, transient output voltage regulation. This accounts for stable processor operation. Output voltage security margins can be kept small, resulting in an increased overall system efficiency. The TPS62366x devices offer high efficiency step down conversion. The area of highest efficiency is extended towards low output currents to increase the efficiency while the processor is operating in retention mode, as well as towards highest output currents reducing the power loss. This addresses the power profile of processors. High efficiency conversion is required for low output currents to support the retention modes of processors, resulting in an increased battery on-time. To address the processor maximum performance operating points with highest output currents, high efficiency conversion is enabled as well to save the battery on-time and reduce input power. The robust architecture and multiple safety features allow perfect system integration. The 2mm x 2mm package and the low number of required external components lead to a tiny solution size of approximately less than 25 mm2. OPERATION The TPS62366x synchronous switched mode power converters are based on DCS-Control™, an advanced regulation topology, that combines the advantages of hysteretic, voltage mode and current mode control architectures. While a comparator stage provides excellent load transient response, an additional voltage loop ensures high DC accuracy as well. The TPS62366x compensates ground shifts at the load by the differentially sensing the output voltage at the point of load. The internal ramp generator adds information about the load current and fast output voltage changes. The internally compensated regulation network achieves fast and stable operation with low ESR capacitors. The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and heavy load conditions and a Power Save Mode at light loads. During PWM mode it operates at its nominal switching frequency in continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation depending on the input voltage. As the load current decreases, the converter enters Power Save Mode to sustain high efficiency down to light loads. The transition from PWM to Power Save Mode is seamless and avoids output voltage transients. The TPS62366x family offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. ENABLING AND DISABLING THE DEVICE The device is enabled by setting the EN input to a logic high. Accordingly, a logic low disables the device. If the device is enabled, the internal power stage starts switching and regulates the output voltage to the programmed threshold. The EN input must be terminated, unless the internal pull down resistor is activated. The I2C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per default, this feature is disabled. Programming the EN_DISC bit to a logic high discharges the output capacitor via a typ. 300Ω path on the SENSE+ pin. SOFT START The device incorporates an internal soft start circuitry that controls the ramp up of the output voltage after enabling the device. This circuitry eliminates inrush current to avoid excessive voltage drops of primary cells and rechargeable batteries with high internal impedance. During soft start, the output voltage is monotonically ramped up to the minimum programmable output voltage. After reaching this threshold, the output voltage is further increased following the slope as programmed in the ramp rate settings (see RAMP RATE CONTROLLING) until reaching the programmed output voltage. Once the nominal voltage is reached, regular operation continues. The device is able to start into a pre biased output capacitor as well. PROGRAMMING THE OUTPUT The TPS62366x devices offer two similar registers to program the output. A dedicated hardware input pin (VSEL) is implemented for choosing the active register. The logic state of the VSEL pin selects the register whose settings are present at the output. The VSEL pin must be terminated, unless the internal pull-down resistor is activated. The registers have a certain initial default value (see Table 3) and can be readjusted via I2C during operation. This allows a simple transition between two output options by triggering the dedicated input pin. At the same time since the presets can be readjusted during operation, this offers highest flexibility. Table 3. Output Presets VSEL PIN PRESET I2C REGISTER DEFAULT OPERATION MODE 0 SET0 0x00h – see Table 11 and Table 12 1 SET1 0x01h – see Table 13 and Table 14 DEFAULT OUTPUT VOLTAGE [V] TPS62366A TPS62366B Power Save Mode 1.20 0.96 Power Save Mode 1.16 1.40 Via the I2C interface and/or the two preset options, the following output parameters can be changed: • Output voltage from 0.5V to 1.77V with 10 mV granularity • Mode of operation: Power Save Mode or forced PWM mode The slope for transition between different output voltages (Ramp Rate) can be changed via I2C as well. The slope applies for all presets globally. See RAMP RATE CONTROLLING for further details. Since the output parameters can be changed by a dedicated pin for selecting presets and by I2C, the following use scenarios are feasible: • Control the device via VSEL pin only, after programming the presets, to choose and change within the programmed settings. • Program via I2C only. The dedicated VSEL pin has a fixed connection. Changes are conducted by changing the preset values of the active register. • Dedicated VSEL pin and I2C mixed operation. The non active preset might be changed. The VSEL pin is used for the transition to the new output condition. Changes within an active preset via I2C are feasible as well. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 23 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com DYNAMIC VOLTAGE SCALING The output voltage can be adjusted dynamically. Each of the two output registers can be programmed individually by setting OV[6:0] in the SET0 and SET1 registers. Table 4. TPS62366x Output Voltage Settings for Registers SET0 and SET1 REGISTERS: SET0, SET1, SET2, SET3 OV[D6:D0] OUTPUT VOLTAGE 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV 000 0011 530 mV … … 111 1101 1750 mV 111 1110 1760 mV 111 1111 1770 mV If the output voltage is changed at the active register (selected by the VSEL status), these changes apply after the I2C command is sent. POWER SAVE MODE AND FORCED PWM MODE The TPS62366x devices feature a Power Save Mode to gain efficiency at light output current conditions. The device automatically transitions in both directions between pulse width modulation (PWM) operation at high load and pulse frequency modulation (PFM) operation at light load current. This maintains high efficiency at both light and heavy load currents. In PFM Mode, the device generates single switching pulses when required to maintain the programmed output voltage. The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in both directions. The output current, at which the device transitions from PWM to PFM operation can be estimated as follows: V - VOUT VOUT 1 IOUT,TRANS = IN 2 VIN (f L) (1) With: VIN = Input voltage VOUT = Output Voltage ƒ = Switching frequency, typ. 2.5 MHz L = Inductance (0.47uH - 1uH nominal) The TPS62366x is optimized for low output voltage ripple. Therefore, the peak inductor current in PFM mode is kept small and can be calculated as follows: IL,PFM,peak = t ON ´ (VIN - VOUT ) L (2) And: t ON = VOUT ´ 350ns + 20ns VIN (3) With: VIN = Input Voltage VOUT = Output Voltage tON = On-time of the High Side FET, from Equation 3 L = Inductance 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 The TPS62366x offers a forced PWM mode as well. In this mode, the converter is forced in PWM mode even at light load currents. This comes with the benefit that the converter is operating with lower output voltage ripple. Compared to the PFM mode, the efficiency is lower during light load currents. According to the output voltage, the Power Save Mode / forced PWM Mode can be programmed individually for each preset via I2C by setting the MODE0 and MODE1 bit D7. Table 3 shows the factory presets after enabling the I2C. For additional flexibility, the Power Save Mode can be changed at a preset that is currently active. RAMP RATE CONTROLLING If the output voltage is changed, the TPS62366x actively controls the voltage ramp rate during the transition. An internal oscillator is embedded for high timing precision. Figure 41 shows the operation principle. If the output voltage changes, the device changes the output voltage by adjusting through discrete steps with a programmable ramp rate resulting in a corresponding transition time. The connected output capacitor flattens the steps. Output Voltage Output Voltage VOUT,B ΔVOUT VOUT,A VOUT,A 20 mV/ Ramp Rate ΔVOUT 20 mV 20 mV/ Ramp Rate 20 mV VOUT,B time Δt Δt time Figure 41. Ramp Up and Down The ramp up/down slope can be programmed via I2C interface (see Table 5). Table 5. Ramp Rates RMP [2:0] RAMP RATE [mV/µs] [µs/10mV] 000 32 0.3125 001 16 0.625 010 8 1.25 011 4 2.5 100 2 5 101 1 10 110 0.5 20 111 0.25 40 For a transition of the output voltage from VOUT,A to VOUT,B and vice versa, the resulting ramp up/down slope can be calculated as ΔVOUT mV 1 = 32 RMP[2-0] ( )2 Δt μs 2 (4) If the device is operating in forced PWM Mode, the device actively controls both the ramp up and down slope. If Power Save Mode is activated, the ramp up phase follows the programmed slope. To force the output voltage to follow the ramp down slope in Power Save Mode, the RAMP_PFM bit needs to be set. This forces the converter to follow the ramp down slope during PFM operation as well. If the RAMP_PFM bit is not set in Power Save Mode, the slope can be less at low output currents since the device does not actively source energy back from the output capacitor to the input or it might be sharper at high output currents since the output capacitor is discharged quickly. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 25 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com The TPS62366x ramps taking 20mV steps with a final 10mV step, if required, for reaching the target output voltage. While the output voltage setpoint is changed in a digital stair step fashion, the output voltage change is linear due to the output capacitor whose voltage cannot change instantaneously. SAFE OPERATION AND PROTECTION FEATURES Inductor Current Limit The inductor current limiting prevents the device from drawing high inductor current and excessive current from the battery. Excessive current might occur with a shorted/saturated inductor or a heavy load/shorted output circuit condition. The incorporated inductor peak current limit measures the current while the high side power MOSFET is turned on. Once the current limit is tripped, the high side MOSFET is turned off and the low side MOSFET is turned on to ramp down the inductor current. This prevents high currents to be drawn from the battery. Once the low side MOSFET is on, the low side forward current limit keeps the low side MOSFET on until the current through it decreases below the low side forward current limit threshold. The negative current limit acts if current is flowing back to the battery from the output. It works differently in PWM and PFM operation. In PWM operation, the negative current limit prevents excessive current from flowing back through the inductor to the battery, preventing abnormal voltage conditions at the switching node. In PFM operation, a zero current limits any power flow back to the battery by preventing negative inductor current. Die Temperature Monitoring and Over Temperature Protection The TPS62366x offers two stages of die temperature monitoring and protection. The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that the die temperature is in the higher range. If the device's junction temperature, TJ, exceeds 120°C typical, the TJEW bit is set high. To avoid the thermal shutdown being triggered, the current drawn from the TPS62366x should be reduced at this early stage. The Over Temperature Protection feature disables the device if the temperature increases due to heavy load and/or high ambient temperature. It monitors the device die temperature and, if required, triggers the device into shutdown until the die temperature falls sufficiently. If the junction temperature, TJ, exceeds 150°C typical, the device goes into thermal shutdown. In this mode, the power stage is turned off. During thermal shutdown, the I2C interface remains operable. All register values are kept. For the thermal shutdown, a hysteresis of 20°C typical is implemented allowing the device to cool after the shutdown is triggered. Once the junction temperature TJ cools down to 130°C typical, the device resumes operation. If a thermal shutdown has occurred, the TJTS bit is latched and remains a logic high as long as VDD and AVIN are present and until the bit is reset by the host. Input Under Voltage Protection The input under voltage protection is implemented in order to prevent operation of the device for low input voltage conditions. If the device is enabled, it prevents the device from switching if AVIN falls below the under voltage lock out threshold. If the AVIN under voltage protection threshold is tripped, the device goes into under voltage shutdown instantaneously, turning the power stage off and resetting all internal registers. The input under voltage protection is also implemented on the VDD input. If the VDD under voltage protection threshold is tripped, the device resets all internal registers. A under voltage lock out hysteresis of VUVLO,HYST(AVIN) at AVIN and VUVLO,HYST(VDD) at VDD is implemented. The I2C compatible interface remains fully functional if AVIN and VDD are present. If the under voltage lock out of AVIN or VDD is triggered during operation, all internal registers are reset to their default values. Figure 42 shows the UVLO block diagram. 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 AVIN external low ohmic connection AVIN Under Voltage? Device Shutdown VIN VDD VDD Under Voltage? ≥1 Register Reset, 2 I C I/F Disabled Figure 42. UVLO State Chart By connecting VIN and AVIN to the same potential, VIN is included in the under voltage monitoring. If a low pass input filter is applied at AVIN (not mandatory for the TPS62366x), the delay and shift in the voltage level can be calculated by taking the typical quiescent current IQ at AVIN. As an example, for IQ and 10Ω series resistance, this results in a minimal static shift of approx. 560µV. VIN and AVIN must be connected to the same source for proper device operation. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 27 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com APPLICATION INFORMATION I2C INTERFACE Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The TPS62366x device works as a slave and supports the following data transfer modes, as defined in the I2CBus Specification: • Standard mode (100 kbps) • Fast mode (400 kbps) • Fast mode plus (1Mbps) • High-speed mode (3.4 Mbps) The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as VDD and AVIN are present in the specified range. Tripping the under voltage lock out of AVIN or VDD deletes the registers and establishes the default values once the supply is present again. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-mode. The TPS62366x device supports 7-bit addressing. 10-bit addressing and general call addressing are not supported. Table 6 shows the TPS62366x devices and their assigned I2C addresses. Table 6. I2C Address I2C ADDRESS DEVICE OPTION HEXADECIMAL CODED BINARY CODED TPS62366A (0x60)HEX (110 0000)2 TPS62366B (0x60)HEX (110 0000)2 F/S-Mode Protocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 43. All I2C-compatible devices should recognize a start condition. SDA SCL S P STOP condition START condition Figure 43. START and STOP Conditions 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 44). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 45) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. SDA SCL Data line stable; data valid Change of data allowed Figure 44. Bit Transfer on the Serial Interface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 43). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. Attempting to read data from register addresses not listed in this section results in 00h being read out. Data Output by Transmitter Data Output by Receiver Not Acknowledge Acknowledge SCL 1 2 8 9 S Clock Pulse for Acknowledgment START condition Figure 45. Acknowledge on the I2C Bus Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 29 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com Recognize repeated START or STOP Condition Recognize START or repeated START Condition Generate ACKNOWLEDGE Signal P SDA Sr Acknowledgment Signal From Slave SCL S 1 or 2 Sr 7 8 1 9 ACK 2-8 9 ACK Address Clock Line Held Low While Interrupts are Serviced START or repeated START Condition Sr or P repeated START or STOP Condition Figure 46. Bus Protocol HS-Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. Attempting to read data from register addresses not listed in this section results in 00h being read out. I2C UPDATE SEQUENCE The TPS62366x requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, the TPS62366x device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the TPS62366x. The TPS62366x performs an update on the falling edge of the acknowledge signal that follows the LSB byte. 1 7 S Slave Address 1 1 R/W A 8 1 8 1 1 Register Address A Data A P “0” Write From Master to TPS62366x From TPS62366x to Master A S Sr P = = = = Acknowledge START condition REPEATED START condition STOP condition Figure 47. Write Data Transfer Format in F/S-Mode 30 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 S 1 1 7 Slave Address R/W A 8 1 1 7 Register Address A Sr Slave Address R/W A A S Sr P From TPS62366x to Master 8 1 1 Data A P “1” Read “0” Write From Master to TPS62366x 1 1 = = = = Acknowledge START condition REPEATED START condition STOP condition Figure 48. Read Data Transfer Format in F/S-Mode F/S Mode 1 H/S Mode 8 S HS-Master Code 1 1 7 A Sr Slave Address 1 1 F/S Mode 8 R/W A Register Address 1 8 1 1 A Data A/A P Data Transferred (n x Bytes + Acknowledge) From Master to TPS62366x From TPS62366x to Master A A S Sr P = = = = = H/S Mode continues Acknowledge Acknowledge START condition REPEATED START condition STOP condition Sr Slave Address Figure 49. Data Transfer Format in H/S-Mode Slave Address Byte MSB X X X X X X A1 LSB A0 The slave address byte is the first byte received following the START condition from the master device. Register Address Byte MSB 0 0 0 0 0 D2 D1 LSB D0 Following the successful acknowledgment of the slave address, the bus master sends a byte to the TPS62366x, which contains the address of the register to be accessed. I2C REGISTER RESET The I2C registers can be reset by pulling VDD below the VDD Under Voltage Level, VDD,UVLO. VDD can be used as a hardware reset function to reset the registers to defaults, if VDD is supplied by a GPIO of the host. The host's GPIO must be capable of driving IVDD,max. Refer to the Input Under Voltage Protection section for details. PULL DOWN RESISTORS The EN and VSEL inputs feature internal pull down resistors to discharge the potential if one of the pins is not connected or is triggered by a high impedance source. See Figure 50. By default, the pull down resistors are enabled. EN / VSEL input buffer EN_internal / VSEL_internal RPD PD_x Figure 50. Pull Down Resistors at EN and VSEL pins Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 31 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com If a pin is read as a logic HIGH, its pull down resistor is disconnected dynamically to reduce power consumption. To achieve lowest possible quiescent current or if external pull up/down resistors are employed, the internal pull down resistors can be disabled individually at EN and VSEL by I2C programming the registers PD_EN and PD_VSEL. INPUT CAPACITOR SELECTION The input capacitor is required to buffer the pulsing current drawn by the device at VIN and reducing the input voltage ripple. The pulsing current is originated by the operation principles of a step down converter. Low ESR input capacitors are required for best input voltage filtering and minimal interference with other system components. For best performance, ceramic capacitors with a low ESR at the switching frequency are recommended. X7R or X5R type capacitors should be used. A ceramic input capacitor in the nominal range of CIN = 4.7µF to 22µF should be a good choice for most application scenarios. In general, there is no upper limit for increasing the input capacitor. For typical operation, a 10µF X5R type capacitor is recommended. Table 7 shows a list of recommended capacitors. Table 7. List of Recommended Capacitors CAPACITANCE [µF] TYPE DIMENSIONS L x W x H [mm3] MANUFACTURER 10 GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata 10 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung 22 GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata 22 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung DECOUPLING CAPACITORS AT AVIN, VDD Noise impacts can be reduced by buffering AVIN and VDD with a decoupling capacitor. It is recommended to buffer AVIN and VDD with a X5R or X7R ceramic capacitor of at least 0.1µF connected between AVIN, AGND and VDD, AGND respectively. The capacitor closest to the pin should be kept small (< 0.22µF) in order to keep a low impedance at high frequencies. In general, there is no upper limit for the total capacitance. INDUCTOR SELECTION The choice of the inductor type and value has an impact on the inductor ripple current, the transition point of PFM to PWM operation, the output voltage ripple and accuracy. The subsections below support for choosing the proper inductor. Inductance Value The TPS62366x is designed for best operation with a nominal inductance value of 1µH. Inductances down to 0.47µH nominal may be used to improve the load transient behavior or to decrease the total solution size. See OUTPUT FILTER DESIGN for details. Depending on the inductance, using inductances lower than 1µH results in a higher inductor current ripple. It can be calculated as: V 1 - OUT VIN ΔIL = VOUT ´ L ´ ¦ (5) With: VIN = Input Voltage VOUT = Output Voltage ƒ = Switching frequency, typ. 2.5MHz L = Inductance 32 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 Inductor Saturation Current The inductor needs to be selected for its current rating. To pick the proper saturation current rating, the maximum inductor current can be calculated as: ΔIL IL,MAX = IOUT,MAX + 2 (6) With: ΔIL = Inductor ripple current (see Equation 5) IOUT,MAX = Maximum output current Since the inductance can be decreased by saturation effects and temperature impact, the inductor needs to be chosen to have an effective inductance of at least 0.3µH under temperature and saturation effects. Table 8 shows a list of inductors that have been used with the TPS62366x. Special care needs to be taken for choosing the proper inductor, taking e.g. the load profile into account. Table 8. List of Recommended Inductors INDUCTANCE [µH] SATURATION CURRENT RATING (1) (ΔL/L =30%, typ) [A] TEMPERATURE CURRENT RATING (1) (ΔT =40°C, typ) [A] DIMENSIONS LxWxH [mm3] DC RESISTANCE [mΩ typ] TYPE MANUFACTURER 1.0 5.4 11.0 4.0 x 4.0 x 2.1 11 XFL4020-102ME1.0 Coilcraft 1.0 4.7 3.6 3.2 x 2.5 x 1.2 34 DFE322512C Toko 1.0 6.0 4.1 4.4 x 4.1 x 1.2 38 SPM4012 TDK 1.0 4.7 3.8 3.2 x 2.5 x 1.2 35 PILE32251B1R0MS-11 (2) Cyntec 1.0 4.5 7.0 4.15 x 4.0 x 1.8 24 PIMB042T-1R0MS11 Cyntec 1.0 4.2 3.7 2.5 x 2.0 x 1.2 38 DFE252012R -H1R0N (2) Toko 0.47 6.6 11.2 4.0 x 4.0 x 1.5 8 XFL4015-471M Coilcraft 0.47 5 4.5 2.5 x 2.0 x 1.2 23 PIFE25201BR47MS-11 (2) Cyntec 0.47 5.2 4.4 2.5 x 2.0 x 1.2 27 DFE252012R -HR47N (3) Toko (1) (2) (3) Excessive inductor temperature might result in a further effective inductance drop which might be below or close to the max. current limit threshold, ILIM,max, depending on the inductor, use case and thermal board design. Proper saturation current rating must be verified, taking into account the use scenario and thermal board layout. Product preview, release planned for Q3/4 2012. Contact manufacturer for details. Under development, typ. data might change. Contact manufacturer for schedule and details. OUTPUT CAPACITOR SELECTION The unique hysteretic control scheme allows the use of tiny ceramic capacitors. For best performance, ceramic capacitors with low ESR values are recommended to achieve high conversion efficiency and low output voltage ripple. For stable operation, X7R or X5R type capacitors are recommended. The TPS62366x is designed to operate with a minimum output capacitor of 10µF for a 1µH inductor and 2x10µF for a 0.47µH inductor, placed at the device's output. In addition, a 0.1µF capacitor can be added to the output to reduce the high frequency content created by a very sudden load change. For stability, an overall maximum output capacitance must not be exceeded. See OUTPUT FILTER DESIGN. Table 7 shows a list of tested capacitors. The TPS62366x is not designed for use with polymer, tantalum, or electrolytic output capacitors. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 33 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com OUTPUT FILTER DESIGN The inductor and the output capacitors create the output filter. The output capacitors consist of COUT and buffer capacitors at the load, CLOAD. See Figure 51. Buffering the load by ceramic capacitors, CLOAD, improves the voltage quality at the load input and the dynamic load step behavior. This is especially true if the trace between the TPS62366x and the load is longer than the smallest possible. TPS62366x L SW SW COUT LOAD SENSE+ CLOAD SENSE- PGND PGND PGND Figure 51. L, COUT and CLOAD Forming the Output Filter Depending on the chosen inductor value, a certain minimum output capacitor COUT must be present. Also depending on the chosen inductor value, a maximum output and buffer capacitor configuration (COUT + CLOAD) must not be exceeded. Figure 52 shows the range of L, COUT and CLOAD that create a stable output filter. L 1µH N( MI MAX (CO UT +C LOA D ) ) T C OU Output filter range 0.47µH 10µF 20µF COUT + CLOAD 100µF 200µF Figure 52. Recommended L, COUT and CLOAD Combinations Within the allowed output filter range, a certain filter can be chosen to improve further on application specific key parameters. The choice of the inductance, L, affects the inductor current ripple, output voltage ripple, the PFM to PWM transition point and the PFM operation switching frequency. The TPS62366x is designed for operation with a nominal inductance value of 1µH. Inductances down to 0.47µH nominal may be used to improve the load transient behavior (see Figure 31 and Figure 34) or to decrease the total solution size. This increases the inductor current ripple (see Equation 5). As a consequence, the output voltage ripple is increased if the output capacitance is kept constant. The increased inductor ripple current also causes higher peak inductor currents (see Equation 6), requiring a higher saturation current rating. Furthermore, the PFM switching frequency is decreased (see Figure 38) and the automatic PFM to PWM transition occurs at a higher output current (see Equation 1). The choice of the output and buffer capacitance (COUT and CLOAD) affects the load step behavior, output voltage ripple, PFM switching frequency and output voltage transition time. A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreasing the PFM switching frequency. For very large output filter combinations, the output voltage might be slower than the programmed ramp rate at voltage transitions (see RAMP RATE CONTROLLING) because of the higher energy stored on the output capacitance. At startup, the time required to charge the output capacitor to 0.5V might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor (see ENABLING AND DISABLING THE DEVICE), this requires more time to settle VOUT down as a consequence of the increased time constant τ = RDISCHARGE x (COUT + CLOAD). 34 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 For further performance or specific demands, these values might be tweaked. In any case, the loop stability should be checked since the control loop stability might be affected. At light loads, if the device is operating in PFM Mode, choosing a higher value minimizes the voltage ripple resulting in a better DC output accuracy. THERMAL AND DEVICE LIFETIME INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures. Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with vias to different layers. Proper This results in reduced junction-to-ambient (θJA) and junction-to-board (θJB) thermal resistances and thereby reduces the device junction temperature, TJ. The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at TJ = 105°C) is affected by the junction temperature and the continuously drawn output current. In order to be consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at TJ = 105°C), the average output current IOUT,avg should not continuously exceed 2550mA so as to prevent electromigration failure in the SW pins solder bumps. Exceeding IOUT,avg and/or TJ,max might affect the device reliability by electromigration. Electromigration is a physical effect of wafer chip scale packages in general, being a first order function of DC current and temperature. Refer to the application note TPS62366x Thermal and Device Lifetime Information (SLVA525) for detailed information. For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953). PCB LAYOUT The PCB layout is an important step to maintain the high performance of the TPS62366x. Both the high current and the fast switching nodes demand full attention to the PCB layout to save the robustness of the TPS62366x through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. Signal Routing Strategy The TPS62366x is a mixed signal IC. Depending on the function of a pin or trace, different board layout strategies must be addressed to achieve a good design. Due to the nature of a switching converter, some signals are sensitive to influence from other signals (aggressors). The sense lines, SENSE+ and SENSE-, are sensitive to the aggressors, which are high bandwidth I/O pins (SCL and SDA) and the switch node (SW) and their connected traces. Special care must be taken to avoid cross-talk between them. The following recommendations need to be followed: • • • • • PGND, VIN and SW should be routed on thick layers. They must not surround inner signal layers which are not able to withstand interference from noisy PGND, VIN and SW. They create a flux which is determined by the switching frequency. The flux generated affects neighboring layers due to capacitive coupling across layers. AGND, AVIN and VDD must be isolated from noisy signals. If crossing layers is required for PGND, VIN and SW, they must be dimensioned to support the high currents to not cause high IR drops. In general, changing the layers frequently must be avoided. Signal traces, and especially the sense lines (SENSE+ and SENSE-), must be kept away from noisy traces/ signals. Avoid capacitive coupling with neighboring noisy layers by cutting away the overlapping areas close to signal traces. Special care must be taken for the sense lines to avoid inductive / capacitive cross-talk from aggressors, both from noisy lines as well as the external inductor which generates a magnetic field. Care should be taken for a proper thermal layout. Wide traces, connecting with vias through the layers, provides a proper thermal path to sink the heat energy created from the device and inductor. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 35 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com External Components Placement The input capacitor at VIN must be placed closest to the IC for proper operation. The decoupling caps at AVIN and VDD reduce noise impacts and should be placed as close to the IC as possible. The output filter, consisting of COUT and L, converts the switching signal at SW to the noiseless output voltage. It should be placed as close as possible to the device keeping the switch node small, for best EMI behavior. Trace routing Route the VIN trace wide and thick to avoid IR drops. The trace between the input capacitor's higher node and VIN as well as the trace between the input capacitor's lower node and PGND must be kept as short as possible. Parasitic inductance on these traces must be kept as tiny as possible for proper device operation. AVIN and AGND should be isolated from noisy signals. Route AGND to the star ground point where no IR drop occurs. The input cap at AVIN isolates noise. Proceed with VDD and AGND in a similar manner. The switch node trace, SW, must connect directly to the inductor followed by the output capacitors, COUT. The switch node is an aggressor. Keeping this trace short reduces noise being radiated and improves EMI behavior. The lower node of the output capacitor, COUT, needs to connect to the star ground point. The TPS62366x supports the point of load concept (POL). Input caps at the POL do not need to be placed closest to the IC; they should be placed close to the POL. Route the traces between the TPS62366x's output capacitor and the load's input capacitors direct and wide to avoid losses due to the IR drop. Connect the sense lines to the POL. This puts into practice the remote sensing concept, allowing the device to regulate the voltage at the POL, compensating IR drops. If possible, make a Kelvin connection to the load device. The sense lines are susceptible to noise. They must be kept away from noisy signals such as PGND, VIN, and SW, as well as high bandwidth signals such as the I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short, direct and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a differential pair is recommended. The PGND nodes at CIN and COUT can be connected underneath the IC at the PGND pins (star point). Make sure that small signal traces returning to the AGND do not share the high current path at PGND to CIN and COUT. See Figure 53 for the recommended layout. VIN SW PGND star ground point VOUT Figure 53. Layout Suggestion (top view) with 3225 inductor. Overall Solution Size: 27.5mm2 36 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 REGISTER SETTINGS Overview Table 9. TPS62366A Register Settings Overview ADDRESS REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 0x00h SET0 0100 0110 R/W MODE0 OV0[6:0] 0x01h SET1 0100 0010 R/W MODE1 OV1[6:0] 0x02h (Reserved) xxxx xxxx - 0x03h (Reserved) xxxx xxxx - 0x04h Ctrl 11xx xxxx R/W 0x05h Temp xxxx x000 R/W 0x06h RmpCtrl 000x x00x R/W 0x07h (Reserved) xxxx xxxx - 0x08h Chip_ID 0x09h Chip_ID 1001 00xx R PD_EN D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM PD_VSEL RMP[2:0] Table 10. TPS62366B Register Settings Overview ADDRESS REGISTER REGISTER (default / reset values) RESET / DEFAULT STATE READ / WRITE MSB D7 LSB D6 D5 D4 D3 0x00h SET0 0010 1110 R/W MODE0 OV0[6:0] 0x01h SET1 0101 1010 R/W MODE1 OV1[6:0] 0x02h (Reserved) xxxx xxxx - 0x03h (Reserved) xxxx xxxx - 0x04h Ctrl 11xx xxxx R/W 0x05h Temp xxxx x000 R/W 0x06h RmpCtrl 000x x00x R/W 0x07h (Reserved) xxxx xxxx - 0x08h Chip_ID 0x09h Chip_ID 1001 01xx R PD_EN D2 D1 D0 DIS_TS TJEW TJTS EN_DISC RAMP_PFM PD_VSEL RMP[2:0] Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 37 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com Register 0x00h Description: SET0 The register settings apply by choosing SET0 (VSEL = LOW). Table 11. TPS62366A Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB 0 DESCRIPTION Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET0 Default: (100 0110)2 = 1.2V D4 0 D6-D0 Output voltage D3 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D2 OV0[6:0] 1 D1 1 D0 LSB 0 VOUT = (xxx xxxx)2 × 10mV + 500 mV Table 12. TPS62366B Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB 0 DESCRIPTION Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 0 D5 1 Output voltage for SET0 Default: (010 1110)2 = 0.96V D4 0 D6-D0 Output voltage D3 1 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D2 OV0[6:0] 1 D1 D0 38 1 LSB 0 VOUT = (xxx xxxx)2 × 10mV + 500 mV Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 Register 0x01h Description: SET1 The register settings apply by choosing SET1 (VSEL = HIGH). Table 13. TPS62366A Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB 0 DESCRIPTION Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET1 Default: (100 0010)2 = 1.16V D4 0 D6-D0 Output voltage D3 0 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D2 OV1[6:0] 0 D1 1 D0 LSB 0 VOUT = (xxx xxxx)2 × 10mV + 500 mV Table 14. TPS62366B Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB 0 DESCRIPTION Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 1 D5 0 Output voltage for SET1 Default: (101 1010)2 = 1.40V D4 1 D6-D0 Output voltage D3 1 000 0000 500 mV 000 0001 510 mV 000 0010 520 mV ... ... 111 1111 1770 mV D2 OV1[6:0] 0 D1 D0 1 LSB 0 VOUT = (xxx xxxx)2 × 10mV + 500 mV Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 39 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com Register 0x04h Description: Ctrl Table 15. TPS62366x Register 0x04h Description REGISTER ADDRESS: 0x04h Read / Write BIT NAME DEFAULT DESCRIPTION MSB D7 PD_EN 1 EN internal pull down resistor 0 = disabled 1 = enabled D6 PD_VSEL 1 VSEL internal pull down resistor 0 = disabled 1 = enabled D5 x Reserved for future use D4 x Reserved for future use D3 x Reserved for future use D2 x Reserved for future use D1 x Reserved for future use x Reserved for future use D0 LSB Register 0x05h Description: Temp Table 16. TPS62366x Register 0x05h Description REGISTER ADDRESS: 0x05h Read/Write BIT NAME D7 DEFAULT MSB Reserved for future use D6 x Reserved for future use D5 x Reserved for future use D4 x Reserved for future use D3 x Reserved for future use D2 DIS_TS 0 Disable temperature shutdown feature 0 = Temperature shutdown enabled 1 = Temperature shutdown disabled (not recommended) D1 TJEW 0 TJ early warning bit 0 = TJ < 120°C (typ) 1 = TJ ≥ 120°C (typ) D0 TJTS 0 TJ temperature shutdown bit 0 = die temperature within the valid range 1 = temperature shutdown was triggered LSB 40 DESCRIPTION x Bit needs to be reset after it has been latched. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 Register 0x06h Description: RmpCtrl Table 17. TPS62366x Register 0x06h Description REGISTER ADDRESS: 0x06h Read/Write BIT NAME DEFAULT DESCRIPTION MSB D7 Output voltage ramp timing 0 D6 0 RMP[2:0] D7-D5 Slope 000 32 mV / µs 001 16 mV / µs 010 8 mV / µs ... ... 110 0.5 mV / µs 111 0.25 mV / µs ΔVOUT mV 1 = 32 Δt μs 2(RMP[2-0] )2 D5 0 D4 x Reserved for future use D3 x Reserved for future use 0 Active output capacitor discharge at shutdown 0 = disabled 1 = enabled 0 Defines the ramp behavior if the device is in Power Save (PFM) mode 0 = output cap is discharged by the load only 1 = output voltage is forced to follow the ramp down slope x Reserved for future use EN_DISC D2 D1 RAMP_PFM D0 LSB Register 0x07h Description: (Reserved) Table 18. TPS62366x Register 0x07h Description REGISTER ADDRESS: 0x07h BIT D7 NAME DEFAULT x Reserved for future use D6 x Reserved for future use D5 x Reserved for future use D4 x Reserved for future use D3 x Reserved for future use D2 x Reserved for future use D1 x Reserved for future use x Reserved for future use D0 MSB DESCRIPTION LSB Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 41 TPS62366A, TPS62366B SLUSAX3 – JULY 2012 www.ti.com Register 0x08h, 0x09h Description Chip_ID: Table 19. TPS62366x Register 0x08h and 0x09h Description REGISTER ADDRESS: 0x08h, 0x09 Read BIT D7 NAME DEFAULT MSB D6 0 D5 0 D4 1 D3 x D2 x D1 x D0 x LSB 42 DESCRIPTION 1 Vendor ID D3-D2 Part number ID 00 TPS62366A 01 TPS62366B 10 - 11 - D1-D0 Chip revision ID 00 Rev. 1 01 Rev. 2 10 Rev. 3 11 Rev. 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B TPS62366A, TPS62366B www.ti.com SLUSAX3 – JULY 2012 PACKAGE SUMMARY CHIP SCALE PACKAGE (TOP VIEW) Code: TIYMLLLLS TPSxxxxxx E • TI — Texas Instruments • YM — Year Month date code • LLLL — Lot trace code • S — Assembly site code • TPSxxxxxx — Part number A1 D Figure 54. Package Marking and Dimensions CHIP SCALE PACKAGE DIMENSIONS The TPS62366x device is available in a 16-bump chip scale package (YZH, NanoFree™). The package dimensions are given as: • D = 2.076mm (+/- 0.03mm) • E = 2.076mm (+/- 0.03mm) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPS62366A TPS62366B 43 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS62366AYZHR ACTIVE DSBGA YZH 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS62366A TPS62366AYZHT ACTIVE DSBGA YZH 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS62366A TPS62366BYZHR ACTIVE DSBGA YZH 16 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS62366B TPS62366BYZHT ACTIVE DSBGA YZH 16 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 TPS62366B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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