Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
TPS62410 2.25-MHz 2 x 800-mA Dual Step-Down Converter in Small 3 × 3 mm VSON
Package
1 Features
3 Description
•
•
•
•
•
•
The TPS62410 device is a synchronous dual stepdown DC–DC converter. It provides two independent
output voltage rails powered by 1-cell Li-Ion or 3-cell
NiMH/NiCD batteries. The device is also suitable to
operate from a standard 3.3 V or 5 V voltage rail.
1
•
•
•
•
•
•
High Efficiency up to 95%
VIN Range from 2.5 V to 6 V
2.25-MHz Fixed Frequency Operation
Output Current 2 x 800 mA
Adjustable Output Voltage from 0.6 V to VIN
Optional EasyScale™ One-Pin Serial Interface for
Dynamic Output Voltage Adjustment
Power-Save Mode at Light Load Currents
180° Out of Phase Operation
Output Voltage Accuracy in PWM Mode ±1%
Typical 32-μA Quiescent Current for Both
Converters
100% Duty Cycle for Lowest Dropout
Available in a 10-Pin VSON (3 mm × 3 mm)
2 Applications
•
•
•
•
•
•
Cell Phones, Smartphones
PDAs, Pocket PCs
OMAP™ and Low-Power DSP Supply
Portable Media Players
Digital Radios
Digital Cameras
With an input voltage range of 2.5 V to 6 V, the
TPS62410 is ideal for battery powered portable
applications like smart phones, PDAs, and other
portable equipment.
With the EasyScale™ serial interface, the output
voltages can be modified during operation. It
therefore supports dynamic voltage scaling for lowpower DSP and processors.
The TPS62410 operates at 2.25-MHz fixed switching
frequency and enter the power-save mode operation
at light load currents to maintain high efficiency over
the entire load current range. For low-noise
applications the devices can be forced into fixed
frequency PWM mode by pulling the MODE/DATA
pin High. In the shutdown mode, the current
consumption is reduced to 1.2 μA. The device allows
the use of small inductors and capacitors to achieve a
small solution size.
The TPS62410 operates over a free-air temperature
range of –40°C to 85°C. It is available in a 10-pin
leadless package (3 × 3 mm VSON)
Device Information(1)
PART NUMBER
PACKAGE
TPS62410
BODY SIZE (NOM)
VSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Efficiency vs Output Current
TPS62410
VIN
100
FB 1
SW1
CIN
L1
2.2 μH
10 μF
R11
270kΩ
DEF_1
L2
EN_2
MODE/
DATA
SW2
2.2 μH
80
COUT1 = 22 µF
70
V OUT2 = 1.8V
Cff2
R21
360kΩ 33pF
ADJ2
GND
R22
180kΩ
Up to 800mA
COUT2 = 22 µF
VOUT = 3.3 V
VIN = 3.6 V
up to 800mA
R12
180kΩ
EN_1
90
VOUT1 = 1.5V
Efficiency - %
VIN 2.5V – 6V
VIN = 3.6 V
60
VIN = 5 V
VIN = 5 V
50
40
30
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
20
10
0
0.01
0.1
1
10
IOUT - mA
100
1000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 11
7.5 Programming........................................................... 13
7.6 Register Maps ......................................................... 16
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 20
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 Device and Documentation Support ................. 28
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
28
28
28
28
28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2007) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Ordering Information table ....................................................................................................................................... 1
2
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
ADJ2
1
10
SW2
MODE/DATA
2
9
EN2
VIN
3
8
GND
FB1
4
7
EN1
DEF_1
5
6
SW1
Thermal Pad
Pin Functions
PIN
NAME
NO.
ADJ2
1
I/O
DESCRIPTION
I
Input to adjust output voltage of converter 2. In adjustable version (TPS62410) connect an external
resistor divider between VOUT2, this pin and GND to set output voltage between 0.6 V and VIN. If
EasyScale™ interface is used for converter 2, this pin must be directly connected to the output.
MODE/DATA
2
I
This Pin has 2 functions:
1. Operation mode selection: With low level, power-save mode is enabled where the device operates
in PFM mode at light loads and enters automatically PWM mode at heavy loads. Pulling this PIN
to High forces the device to operate in PWM mode over the whole load range.
2. EasyScale™ interface function: One wire serial interface to change the output voltage of both
converters. The pin has an open-drain output to provide an acknowledge condition if requested.
The current into the open-drain output stage may not exceed 500 μA. The interface is active if
either EN1 or EN2 is High.
VIN
3
I
Supply voltage, connect to VBAT, 2.5 V to 6 V
FB1
4
I
Direct feedback voltage sense input of converter 1, connect directly to VOUT1. An internal feed forward
capacitor is connected between this pin and the error amplifier. In case of fixed output voltage versions
or when the Interface is used, this pin is connected to an internal resistor divider network.
DEF_1
5
I/O
This pin defines the output voltage of converter 1. The pin acts in TPS62410 as an analog input for
output voltage setting through external resistors. In fixed default output voltage versions this pin is a
digital input to select between two fixed default output voltages.
In TPS62410 an external resistor network needs to be connected to this pin to adjust the default output
voltage.
SW1
6
—
EN1
7
I
Switch pin of converter1. Connected to inductor 1
Enable input for converter1, active high
GND
8
I
GND for both converters, this pin should be connected with the PowerPAD
EN2
9
I/O
Enable input for converter 2, active high
SW2
10
—
Switch pin of converter 2. Connected to inductor 2
PowerPAD™
—
—
Connect to GND
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
3
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltage on VIN
(2)
Voltage on EN, MODE/DATA, DEF_1
MIN
MAX
UNIT
–0.3
7
V
–0.3
VIN +0.3, ≤7
V
500
μA
V
Maximum current into MODE/DATA
Voltage on SW1, SW2
–0.3
7
Voltage on ADJ2, FB1
–0.3
VIN +0.3, ≤7
V
150
°C
TJ(max) Maximum junction temperature
TA
Operating ambient temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
VIN
Supply voltage
MIN
MAX
2.5
6
UNIT
V
Output voltage range for adjustable voltage
0.6
VIN
V
TA
Operating ambient temperature
-40
85
°C
TJ
Operating junction temperature
-40
125
°C
6.4 Thermal Information
TPS62410
THERMAL METRIC
(1)
DRC (VSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
45.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
64.3
°C/W
RθJB
Junction-to-board thermal resistance
20.4
°C/W
ψJT
Junction-to-top characterization parameter
1.3
°C/W
ψJB
Junction-to-board characterization parameter
20.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.8
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
6.5 Electrical Characteristics
VIN = 3.6 V, VOUT = 1.8 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 20 μF, TA = –40°C to 85°C typical values are at TA =
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
6
V
One converter, IOUT = 0 mA. PFM mode
enabled (Mode = 0) device not switching,
EN1 = 1 or EN2 = 1
19
29
μA
Two converter, IOUT = 0mA. PFM mode
enabled (Mode = 0) device not switching,
EN1 = 1 and EN2 = 1
32
48
μA
IOUT = 0 mA, MODE/DATA = GND, for one
converter, VOUT 1.575 V (1)
23
μA
IOUT = 0 mA, MODE/DATA = VIN, for one
converter, VOUT 1.575 V (1)
3.6
mA
EN1, EN2 = GND, VIN = 3.6 V (2)
1.2
3
EN1, EN2 = GND, VIN ramped from 0 V to
3.6 V (3)
0.1
1
Falling
1.5
2.35
SUPPLY CURRENT
VIN
Input voltage
IQ
Operating quiescent current
ISD
Shutdown current
VUVLO
Undervoltage lockout threshold
2.5
Rising
2.4
μA
V
ENABLE EN1, EN2
VIH
High-level input voltage, EN1,
EN2
1.2
VIN
V
VIL
Low-level input voltage, EN1,
EN2
0
0.4
V
IIN
Input bias current, EN1, EN2
EN1, EN2 = GND or VIN
0.05
1
μA
DEF_1 = GND or VIN
0.01
1
μA
DEF_1 INPUT
IIN
Input biasd current DEF_1
MODE/DATA
VIH
High-level input voltage,
MODE/DATA
1.2
VIN
V
VIL
Low-level input voltage,
MODE/DATA
0
0.4
V
IIN
Input bias current, MODE/DATA
MODE/DATA = GND or VIN
VOH
Acknowledge output voltage high
Open-drain, through external pullup resistor
VOL
Acknowledge output voltage low
Open-drain, sink current 500 μA
0.01
0
1
μA
VIN
V
0.4
V
INTERFACE TIMING
tStart
Start time
tH_LB
High time low bit, logic 0
detection
Signal level on MODE/DATA pin is > 1.2 V
tL_LB
Low time low bit, logic 0
detection
tL_HB
μs
2
2
200
μs
Signal level on MODE/DATA pin < 0.4 V
2 x tH_LB
400
μs
Low time high bit, logic 1
detection
Signal level on MODE/DATA pin < 0.4 V
2
200
μs
tH_LB
High time high bit, logic 1
detection
Signal level on MODE/DATA pin is > 1.2 V
2 x tL_HS
400
μs
TEOS
End of Stream
TEOS
tACKN
Duration of acknowledge
condition (MODE/DATE line
pulled low by the device)
VIN 2.5 V to 6 V
(1)
(2)
(3)
μs
2
400
520
μs
Device is switching with no load on the output, L = 3.3 μH, value includes losses of the coil
These values are valid after the device has been already enabled one time (EN1 or EN2 = High) and supply voltage VIN has not
powered down.
After the first enable, these values are valid when the device is disabled (EN1 and EN2 = Low) and supply voltage VIN is powered up.
The values remain valid until the device has been enabled first time (EN1 or EN2 = High).
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
5
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Electrical Characteristics (continued)
VIN = 3.6 V, VOUT = 1.8 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 20 μF, TA = –40°C to 85°C typical values are at TA =
25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tvalACK
Acknowledge valid time
ttimeout
Time-out for entering power-save MODE/DATA Pin changes from high to low
mode
TYP
MAX
UNIT
2
μs
520
μs
280
620
mΩ
1
μA
200
450
mΩ
6
7.5
μA
1.2
1.38
A
POWER SWITCH
RDS(ON)
P-channel MOSFET onresistance, converter 1, 2
VIN = VGS = 3.6 V
ILK_PMOS
P-channel leakage current
VDS = 6.0 V
RDS(ON)
N-channel MOSFET onresistance converter 1, 2
VIN = VGS = 3.6 V
ILK_SW1/SW
Leakage current into SW1/SW2
pin
Includes N-Chanel leakage current,
VIN = open, VSW = 6.0 V, EN = GND (4)
ILIMF
Forward current
limit PMOS and
NMOS
2.5 V ≤ VIN ≤ 6.0 V
TSD
Thermal shutdown
Increasing junction temperature
150
°C
Thermal shutdown hysteresis
Decreasing junction temperature
20
°C
2
OUT 1/2 800
mA
1
OSCILLATOR
fSW
2.5 V ≤ VIN ≤ 6.0 V
Oscillator frequency
2
2.25
2.5
MHz
OUTPUT
VOUT
Adjustable output voltage range
Vref
Reference voltage
0.6
Voltage positioning active, MODE/DATA =
GND, device operating in PFM mode, VIN =
2.5 V to 5.0 V (6) (7)
VOUT (PFM)
DC output voltage accuracy PFM
MODE/DATA = GND; device operating in
mode, adjustable and fixed
PWM mode VIN = 2.5 V to 6.0 V (7)
(5)
output voltage
VIN = 2.5 V to 6.0 V, MODE/DATA = VIN ,
Fixed PWM operation, 0 mA < IOUT <
IOUTMAX (8)
VOUT
VIN
600
–1.5%
1.01 x VOUT
2.5%
–1%
0%
1%
–1%
0%
1%
DC output voltage load regulation PWM operation mode
V
mV
0.5
%/A
tStart up
Start-up time
Activation time to start switching (9)
170
μs
tRamp
VOUT Ramp-up time
Time to ramp from 5% to 95% of VOUT
750
μs
(4)
(5)
(6)
(7)
(8)
(9)
At pins SW1 and SW2 an internal resistor of 1 MΩ is connected to GND
Output voltage specification does not include tolerance of external voltage programming resistors
Configuration L typical 2.2 μH, COUT typical 20 μF, see parameter measurement information, the output voltage ripple depends on the
effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance
In power-save mode, PWM operation is typically entered at IPSM = VIN/32 Ω.
For VOUT >2. 2V, VIN min = VOUT +0.3 V
This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) and the other converter is already
enabled (that is, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = Low) to active mode (EN1 and/or
EN2 = 1) a value of typical 80 μs for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps
VOUT.
6.6 Dissipation Ratings
6
PACKAGE
POWER RATING FOR TA ≤25°C
DERATING FACTOR ABOVE TA = 25°C
DRC
2050 mW
21 mW/°C
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
6.7 Typical Characteristics
24
2.5
2.45
23
2.4
85°C
22
Iddq - mA
Fosc - MHz
2.35
2.3
-40°C
2.25
2.2
20
25°C
2.15
25°C
21
-40°C
19
85°C
2.1
18
2.05
2
2.5
3
3.5
4
4.5
VIN - V
17
2.5
6
5.5
5
3
3.5
4
4.5
5
5.5
6
VIN - V
Figure 1. FOSC vs VIN
Figure 2. Iq for One Converter, Not Switching
0.55
42
0.5
40
0.45
38
RDSon - W
Iddq - mA
85°C
36
25°C
34
0.4
85°C
0.35
25°C
0.3
32
-40°C
0.25
-40°C
30
0.2
0.15
2.5
28
2.5
3
3.5
4
4.5
5
5.5
6
3
3.5
VIN - V
4
4.5
5
5.5
6
VIN - V
Figure 3. Iq for Both Converters, Not Switching
Figure 4. RDSON PMOS vs VIN
0.3
0.25
RDSon - W
85°C
0.2
25°C
-40°C
0.15
0.1
0.05
2.5
3
3.5
4
4.5
5
5.5
6
VIN - V
Figure 5. RDSON NMOS vs VIN
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
7
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
7 Detailed Description
7.1 Overview
7.1.1 Operation
The TPS62410 includes two synchronous step-down converters. The converters operate with typically 2.25-MHz
fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. If power-save mode is
enabled, the converters automatically enter power-save mode at light load currents and operate in pulse
frequency modulation (PFM). During PWM operation the converters use a unique fast response voltage mode
controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of
small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the
P-channel MOSFET switch is turned on and the inductor current ramps up until the comparator trips and the
control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel
MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is
turned off and the N-channel MOSFET is turned on. If the current in the N-channel MOSFET is above the NMOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC/DC converters operate synchronized to each other. A 180° phase shift between converter 1 and
converter 2 decreases the input RMS current.
7.1.1.1 Converter 1
In the adjustable output voltage version TPS62410 the converter 1 output voltage can be set through an external
resistor network on pin DEF_1, which operates as an analog input. In this case, the output voltage can be set in
the range of 0.6 V to VIN. The FB1 pin must be directly connected to the converter 1 output voltage VOUT1. It
feeds back the output voltage directly to the regulation loop.
The output voltage of converter 1 can also be changed by the EasyScale™ serial interface. This makes the
device very flexible for output voltage adjustment. In this case, the device uses an internal resistor network.
7.1.1.2 Converter 2
In the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistor
divider connected to ADJ2 pin and uses an external feed forward capacitor of 33 pF.
It is also possible to change the output voltage of converter 2 through the EasyScale™ interface. In this case, the
ADJ2 pin must be directly connected to converter 2 output voltage VOUT2. At TPS62410 no external resistor
network may be connected.
8
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
7.2 Functional Block Diagram
VIN
PMOS Current
Limit Comparator
Converter 1
VIN
FB_VOUT
Thermal
Shutdown
Softstart
VREF +1%
Skip Comp.
EN1
FB_VOUT
VREF- 1%
Ext. res. network
DEF1
Skip Comp. Low
VREF
Control
Stage
Error Amp.
Internal
FB
VOUT1 compensated
Int. Resistor
Network
PWM
Comp.
Cff 25pF
SW1
MODE
Register
RI 1
RI..N
Sawtooth
Generator
DEF1_High
RI3
FB1
Gate Driver
GND
DEF1_Low
Average
Current Detector
Skip Mode Entry
Note A
NMOS Current
Limit Comparator
CLK 0°
Reference
Mode/
DATA
Easy Scale
Interface
ACK
MOSFET
Open drain
Load Comparator
2.25MHz
Oscillator
Undervoltage
Lockout
PMOS Current
Limit Comparator
CLK 180°
VIN
FB_VOUT
Converter 2
Int. Resistor
Network
VREF +1%
Skip Comp.
Register
FB_VOUT
DEF2
Note B
Cff 25pF
VREF- 1%
Skip Comp. Low
VREF
Error Amp.
RI 1
Internal
compensated
RI..N
Control
Stage
Gate Driver
PWM
Comp.
SW2
MODE
FB_VOUT2
ADJ2
Thermal
Shutdown
Softstart
Sawtooth
Generator
CLK 180°
GND
Average
Current Detector
Skip Mode Entry
NMOS Current
Limit Comparator
EN2
Load Comparator
GND
A.
In fixed output voltage version, the pin DEF_1 is connected to an internal digital input and disconnected from the error
amplifier
B.
To set the output voltage of converter 2 through EasyScale™ interface, ADJ2 pin must be directly connected to VOUT2
7.3 Feature Description
7.3.1 Dynamic Voltage Positioning
This feature reduces the voltage undershoots and overshoots at load steps from light to heavy load and vice
versa. It is activated in power-save mode operation. It provides more headroom for both the voltage drop at a
load step, and the voltage increase at a load throw-off. This improves load transient behavior.
At light loads, in which the converter operate in PFM mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to –2% below the nominal value and enters PWM mode. During a
load throw-off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
9
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Feature Description (continued)
Smooth
increased load
+1%
PFM Mode
light load
Fast load transient
PFM Mode
light load
VOUT_NOM
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
PWM Mode
medium/heavy load
COMP_LOW threshold –1%
Figure 6. Dynamic Voltage Positioning
7.3.2 Undervoltage Lockout
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery and disables the converters. The undervoltage lockout threshold is typically
1.5 V, maximum is 2.35 V. In case the default register values are overwritten by the Interface, the new values in
the registers REG_DEF_1_Low and REG_DEF_2 remain valid as long the supply voltage does not fall under the
undervoltage lockout threshold, independent of whether the converters are disabled.
7.3.3 Mode Selection
The MODE/DATA pin allows mode selection between forced PWM mode and power-save mode for both
converters. Furthermore, this pin is a multi-purpose pin and provides (besides mode selection) a one-pin
interface to receive serial data from a host to set the output voltage. This is described in the section EasyScale™
interface.
Connecting this pin to GND enables the automatic PWM and power-save mode operation. The converters
operate in fixed-frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads,
maintaining high efficiency over a wide load current range.
Pulling the MODE/DATA pin high forces both converters to operate constantly in the PWM mode even at light
load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the
switching frequency for noise-sensitive applications. In this mode, the efficiency is lower compared to the powersave mode during light loads. For additional flexibility it is possible to switch from power-save mode to forced
PWM mode during operation. This allows efficient power management by adjusting the operation of the converter
to the specific system requirements.
In case the operation mode will be changed from forced PWM mode (MODE/DATA = High) to power-save mode
enable (MODE/DATA = 0) the power-save mode will be enabled after a delay time of typically ttimeout, which is a
maximum of 520 μs.
The forced PWM mode operation is enabled immediately with pin MODE/DATA set to 1.
7.3.4 Enable
The device has for each converter a separate EN pin to start up each converter independently. If EN1 and EN2
are set to high, the corresponding converter starts up with soft-start.
Pulling EN1 and EN2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2
μA. In this mode, the P- and N-channel MOSFETs are turned off and the entire internal control circuitry is
switched off. For proper operation, the EN1 and EN2 pins must be terminated and must not be left floating.
10
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
Feature Description (continued)
7.3.5 DEF_1 Pin Function
The DEF_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting.
Connecting an external resistor network to this pin adjusts the default output voltage to any value starting from
0.6 V to VIN.
7.3.6 180° Out of Phase Operation
In PWM mode the converters operate with a 180° turnon phase shift of the PMOS (high-side) transistors. It
prevents the high-side switches of both converters to be turned on simultaneously, and therefore smooths the
input current. This feature reduces the surge current drawn from the supply.
7.3.7 Thermal Shutdown
As soon as the junction temperature, TJ, exceeds typically 150°C the device goes into thermal shutdown. In this
mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction
temperature falls below the thermal shutdown hysteresis again.
7.4 Device Functional Modes
7.4.1 Soft Start
The two converters have an internal soft-start circuit that limits the inrush current during start-up. During softstart, the output voltage ramp up is controlled as shown in Figure 7.
EN
95%
5%
VOUT
tStartup
tRAMP
Figure 7. Soft-Start
7.4.2 100% Duty Cycle Low Dropout Operation
The converters offer a low input to output voltage difference while still maintaining operation with the use of the
100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly useful in
battery-powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range; that is, the minimum input voltage to maintain regulation depends on the load current and output
voltage, and can be calculated as:
Vin min + Vout max ) Iout max
ǒRDSonmax ) R LǓ
where
•
•
•
•
Ioutmax = maximum output current plus inductor ripple current
RDSonmax = maximum P-channel switch RDSon
RL = DC resistance of the inductor
Voutmax = nominal output voltage plus maximum output voltage tolerance
(1)
With decreasing load current, the device automatically switches into pulse-skipping operation in which the power
stage operates intermittently based on load demand. By running cycles periodically the switching losses are
minimized and the device runs with a minimum quiescent current maintaining high efficiency.
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
11
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Device Functional Modes (continued)
7.4.3 Power-Save Mode
The power-save mode is enabled with MODE/DATA pin set to 0 for both converters. If the load current of a
converter decreases, this converter will enter power-save mode operation automatically. The transition to powersave mode of a converter is independent from the operating condition of the other converter. During power-save
mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent
current to maintain high efficiency. The converter will position the output voltage in PFM mode to typically 1.01 ×
VOUT. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average inductor current is monitored. The device
changes from PWM mode to power-save mode, if in PWM mode the inductor current falls below a certain
threshold. The typical output current threshold depends on VIN and can be calculated according to Equation 2 for
each converter.
Equation 2: Average output current threshold to enter PFM mode
VINDCDC
I OUT_PFM_enter +
32 W
(2)
Equation 3: Average output current threshold to leave PFM mode
VINDCDC
I OUT_PFM_leave +
24 W
(3)
In order to keep the output voltage ripple in power-save mode low, the output voltage is monitored with a single
threshold comparator (skip comparator). As the output voltage falls below the skip comparator threshold (skip
comp) of 1.01 × VOUTnominal, the corresponding converter starts switching for a minimum time period of typically 1
μs and provides current to the load and the output capacitor. Therefore the output voltage increases and the
device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. At this
moment all switching activity is stopped and the quiescent current is reduced to minimum. The load is supplied
by the output capacitor until the output voltage has dropped below the threshold again. Hereupon the device
starts switching again. The power-save mode is exited and PWM mode entered in case the output current
exceeds the current IOUT_PFM_leave, or if the output voltage falls below a second comparator threshold, called
skip comparator low (skip comp Low) threshold. This skip comparator low threshold is set to –2% below nominal
Vout, and enables a fast transition from power-save mode to PWM mode during a load step. In power-save mode
the quiescent current is reduced typically to 19 μA for one converter and 32 μA for both converters active. This
single skip comparator threshold method in power-save mode results in a very low output voltage ripple. The
ripple depends on the comparator delay and the size of the output capacitor. Increasing output capacitor values
minimizes the output ripple. The power-save mode can be disabled through the MODE/DATA pin set to high.
Both converters then operate in fixed PWM mode. Power-save mode enable/disable applies to both converters.
7.4.4 Short Circuit Protection
Both outputs are short circuit protected with maximum output current = ILIMF (P-MOS and N-MOS). Once the
PMOS switch reaches its current limit, it will be turned off and the NMOS turned on. The PMOS only turns on
again, once the current in the NMOS decreases below the NMOS current limit.
12
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
7.5 Programming
7.5.1 EasyScale™ Interface: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
7.5.1.1 General
The EasyScale™ interface is a simple but very flexible one-pin interface to configure the output voltage of both
DC–DC converters. The interface is based on a master-slave structure, where the master is typically a microcontroller or application processor. Figure 8 and Table 1 give an overview of the protocol. The protocol consists
of a device specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data
byte consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the
Request For Acknowledge condition. The acknowledge condition is only applied if the protocol was received
correctly.
The advantage of EasyScale™ interfaces compared to other one-pin interfaces is that its bit detection is, to a
large extent, independent from the bit transmission rate. It can automatically detect bit rates between 1.7 kbps
and up to 160 kbps. Furthermore, the interface is shared with the MODE/DATA pin and requires therefore no
additional pin.
7.5.1.2 Protocol
All bits are transmitted MSB first and LSB last. Figure 9 shows the protocol without acknowledge request (bit
RFA = 0), Figure 10 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
MODE/DATA pin needs to be pulled high for at least tStart before the bit transmission starts with the falling edge.
In case the MODE/DATA line was already at high level (forced PWM mode selection) no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an end-of-stream condition for at least TEOS.
7.5.1.3 Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between tLOW and tHIGH. It can
be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2x tLow, see Figure 11
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 11
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between tLow and tHigh a 0 or 1 is detected.
7.5.1.4 Acknowledge
The acknowledge condition is only applied if:
• acknowledge is requested by a set RFA bit
• the transmitted device address matches with the device address of the device
• 16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is max. 520 μs. The acknowledge condition is valid after an internal delay time tvalACK. This means
the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected.
The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with it’s input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied,
thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after
tvalACK. The MODE/DATA pin can be used again after the acknowledge condition ends.
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
13
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Programming (continued)
NOTE
The acknowledge condition may only be requested in case the master device has an
open-drain output.
In case of a push-pull output stage, TI recommends to use a series resistor in the MODE/DATA line to limit the
current to 500 μA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.
7.5.1.5 MODE Selection
Because of the MODE/DATA pin is used for two functions, interface and a mode selection, the device needs to
determine when it has to decode the bit stream or to change the operation mode.
The device enters forced PWM mode operation immediately whenever the MODE/DATA pin turns to high level.
The device stays also in forced PWM mode during the whole time of a protocol reception.
With a falling edge on the MODE/DATA pin the device starts bit decoding. If the MODE/DATA pin stays low for at
least ttimeout, the device get’s an internal time-out and power-save mode operation is enabled.
A protocol which is sent within this time will be ignored, because the falling edge for the mode change will be first
interpreted as start of the first bit. In this case, TI recommends to send first the protocol and change at the end of
the protocol to power-save mode.
DATA IN
Start
Start
Device Address
DA7 DA6 DA5 DA4
0
1
0
0
DATABYTE
DA3 DA2 DA1
1
1
1
DA0 EOS Start RFA
0
A1
A0
D4
D3
D2
D1
D0
EOS
DATA OUT
ACK
Figure 8. EasyScale™ Interface Protocol Overview
Table 1. EasyScale™ Interface Bit Description
BYTE
Device
Address
Byte
4Ehex
Data
Byte
BIT
NUMBER
NAME
TRANSMISSION
DIRECTION
DESCRIPTION
7
DA7
IN
0 MSB device address
6
DA6
IN
1
5
DA5
IN
0
4
DA4
IN
0
3
DA3
IN
1
2
DA2
IN
1
1
DA1
IN
1
IN
0 LSB device address
0
DA0
7 (MSB)
RFA
6
A1
Address bit 1
5
A0
Address bit 0
4
D4
3
D3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
ACK
Request for acknowledge, if High, acknowledge condition will applied by the device
IN
OUT
Data bit 4
Data bit 3
Acknowledge condition active 0, this condition will only be applied in case RFA bit is
set. Open-drain output, Line needs to be pulled high by the host with a pullup
resistor.
This feature can only be used if the master has an open-drain output stage. In case
of a push-pull output stage acknowledge condition may not be requested.
14
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
tStart
DATA IN
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
RFA
0
TEOS
D0
1
TEOS
Figure 9. EasyScale™ Interface Protocol Without Acknowledge
tStart
DATA IN
tStart
Address Byte
DATA Byte
Mode, Static
High or Low
Mode, Static
High or Low
DA7
0
DA0
0
D0
1
RFA
1
T EOS
tvalACK
ACKN
tACKN
Controller needs to
Pullup Data Line via a
resistor to detect ACKN
DATA OUT
Acknowledge
true, Data Line
pulled down by
device
Acknowledge
false, no pull
down
Figure 10. EasyScale™ Interface Protocol Including Acknowledge
tLow
tHigh
Low Bit
(Logic 0)
tLOW
tHigh
High Bit
(Logic 1)
Figure 11. EasyScale™ Interface – Bit Coding
MODE/DATA
ttimeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 12. MODE/DATA Pin: Mode Selection
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
15
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
tStart Address Byte
tStart
DATA Byte
MODE/DATA
TEOS
TEOS
ttimeout
Power Save Mode
Forced PWM MODE
Power Save Mode
Figure 13. MODE/DATA Pin: Power-Save Mode and Interface Communication
7.6 Register Maps
In TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of both
converters. With 5 bit data content, 32 different values for each register are available. Table 2 shows the
addressable registers if DEF_1 pin acts as analog input with external resistors connected.
The available output voltages for converter 1 are shown in Table 3 and for converter 2 in Table 4. To generate
these output voltages, a precise internal resistor divider network is used, which makes external resistors
unnecessary and results therefore in an higher output voltage accuracy and less board space.
The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is High). After the start-up time
tStart (170 μs) the interface is ready for data reception.
Table 2. Addressable Registers for Adjustable Output Voltage Devices
A1
A0
REG_DEF_1_High
REGISTER
Not available in TPS62410 adjustable version
0
1
REG_DEF_1_Low
Converter 1 output voltage setting
0
0
TPS62410 see Table 3
REG_DEF_2
Converter 2 output voltage
1
0
TPS62410 see Table 4, connect ADJ2
pin directly to VOUT2
Do not use
1
1
16
DESCRIPTION
Submit Documentation Feedback
D4
D3
D2
D1
D0
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
Table 3. Selectable Output Voltages for Converter 1,
With DEF1 Pin as Analog Input
0
TPS62410 OUTPUT VOLTAGE [V]
REGISTER REG_DEF_1_LOW
D4
D3
D2
D1
D0
VOUT1 Adjustable Output with Resistor Network on DEF_1 Pin
0
0
0
0
0
0.6 V with DEF_1 Pin connected to VOUT1
1
0.825
0
0
0
0
1
2
0.85
0
0
0
1
0
3
0.875
0
0
0
1
1
4
0.9
0
0
1
0
0
5
0.925
0
0
1
0
1
6
0.95
0
0
1
1
0
7
0.975
0
0
1
1
1
8
1.0
0
1
0
0
0
9
1.025
0
1
0
0
1
10
1.050
0
1
0
1
0
11
1.075
0
1
0
1
1
12
1.1
0
1
1
0
0
13
1.125
0
1
1
0
1
14
1.150
0
1
1
1
0
15
1.175
0
1
1
1
1
16
1.2
1
0
0
0
0
17
1.225
1
0
0
0
1
18
1.25
1
0
0
1
0
19
1.275
1
0
0
1
1
20
1.3
1
0
1
0
0
21
1.325
1
0
1
0
1
22
1.350
1
0
1
1
0
23
1.375
1
0
1
1
1
24
1.4
1
1
0
0
0
25
1.425
1
1
0
0
1
26
1.450
1
1
0
1
0
27
1.475
1
1
0
1
1
28
1.5
1
1
1
0
0
29
1.525
1
1
1
0
1
30
1.55
1
1
1
1
0
31
1.575
1
1
1
1
1
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
17
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
Table 4. Selectable Output Voltages for Converter 2,
(ADJ2 Connected to VOUT)
0
OUTPUT VOLTAGE [V]
FOR REGISTER REG_DEF_2
D4
D3
D2
D1
D0
VOUT2 Adjustable Output with Resistor Network on ADJ2
0
0
0
0
0
0.6 V with ADJ2 pin connected to VOUT2
18
1
0.85
0
0
0
0
1
2
0.9
0
0
0
1
0
3
0.95
0
0
0
1
1
4
1.0
0
0
1
0
0
5
1.05
0
0
1
0
1
6
1.1
0
0
1
1
0
7
1.15
0
0
1
1
1
8
1.2
0
1
0
0
0
9
1.25
0
1
0
0
1
10
1.3
0
1
0
1
0
11
1.35
0
1
0
1
1
12
1.4
0
1
1
0
0
13
1.45
0
1
1
0
1
14
1.5
0
1
1
1
0
15
1.55
0
1
1
1
1
16
1.6
1
0
0
0
0
17
1.7
1
0
0
0
1
18
1.8
1
0
0
1
0
19
1.85
1
0
0
1
1
20
2.0
1
0
1
0
0
21
2.1
1
0
1
0
1
22
2.2
1
0
1
1
0
23
2.3
1
0
1
1
1
24
2.4
1
1
0
0
0
25
2.5
1
1
0
0
1
26
2.6
1
1
0
1
0
27
2.7
1
1
0
1
1
28
2.8
1
1
1
0
0
29
2.85
1
1
1
0
1
30
3.0
1
1
1
1
0
31
3.3
1
1
1
1
1
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Output Voltage Setting
8.1.1.1 Converter 1 Adjustable Default Output Voltage Setting
The output voltage can be calculated to:
V OUT + VREF
ǒ
R
1 ) 11
R 12
Ǔ
with an internal reference voltage VREF typical 0.6V
(4)
To keep the operating current to a minimum, TI recommends selecting R12 within a range of 180 kΩ to 360 kΩ.
The sum of R12 and R11 should not exceed approimately1 MΩ. For higher output voltages than 3.3 V, TI
recommends choosing lower values than 180 kΩ for R12. Route the DEF_1 line away from noise sources, such
as the inductor or the SW1 line. The FB1 line needs to be directly connected to the output capacitor. An internal
feed-forward capacitor is connected to this pin, therefore there is no need for an external feed-forward capacitor
for converter 1.
8.1.1.2 Converter 2
The default output voltage of converter 2 can be set by an external resistor network. For converter 2 the same
recommendations apply as for converter 1. In addition to that, a 33-pF external feed-forward capacitor Cff2 for
good load transient response must be used.
The output voltage can be calculated to:
V OUT + VREF
ǒ
R
1 ) 21
R 22
Ǔ
with an internal reference voltage VREF typical 0.6V
(5)
Route the ADJ2 line away from noise sources, such as the inductor or the SW2 line. In case the interface is used
for converter 2, connect ADJ2 pin directly to VOUT2
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
19
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
8.2 Typical Application
TPS62410
VIN 3.3 V – 6 V
FB 1
VIN
L1
SW1
CIN
10 mF
2.2 mH
DEF_1
COUT1 = 22 mF
R12
180 kW
EN_1
EN_2
R11
270 kW
VOUT1 = 1.5 V
up to 800 mA
L2
SW2
3.3 mH
MODE/
DATA
ADJ2
GND
R21
Cff2
825 kW 33 pF
VOUT2 = 2.85 V
up to 800 mA
COUT2 = 22 mF
R22
220 kW
Figure 14. Typical Application Circuit 1.5-V and 2.85-V Adjustable Outputs, Low PFM Voltage Ripple
Optimized
8.2.1 Design Requirements
The step-down converter design can be adapted to different output voltage and load current needs by choosing
appropriate external components. The following design procedure is adequate for whole VIN, VOUT and load
current range of TPS62410.
8.2.2 Detailed Design Procedure
8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
The device is optimized to operate with inductors of 2.2 μH to 4.7 μH and output capacitors of 10 μF to 22 μF.
For operation with a 2.2 μH inductor, a 22 μF capacitor is suggested.
8.2.2.1.1 Inductor Selection
The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the
inductance will influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance
should be selected for highest efficiency.
Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with Equation 7. This is
recommended because during heavy load transient the inductor current will rise above the calculated value.
DI L + Vout
1 * Vout
Vin
L
I Lmax + I outmax )
ƒ
(6)
DI L
2
where
•
•
•
•
20
f = Switching frequency (2.25 MHz typical)
L = Inductor value
ΔIL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
Submit Documentation Feedback
(7)
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
Typical Application (continued)
The highest inductor current will occur at maximum VIN.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents
versus a comparable shielded inductor.
A more conservative approach is to select the inductor current rating just for the maximum switch current of the
corresponding converter. It must be considered, that the core material from inductor to inductor differs and will
have an impact on the efficiency especially at high switching frequencies.
Refer to Table 5 and the typical applications for possible inductors.
Table 5. List of Inductors
DIMENSIONS [mm3]
INDUCTOR TYPE
SUPPLIER
2.8 x 2.6 × 1.4
VLF3014
TDK
3 × 3 × 1.4
LPS3015
Coilcraft
3.9 × 3.9 × 1.7
LPS4018
Coilcraft
8.2.2.1.2 Output Capacitor Selection
The advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic
capacitors with a typical value of 10 μF, without having large output voltage undershoots and overshoots during
heavy load transients. Ceramic X7R/X5R capacitors having low ESR values result in lowest output voltage ripple
and are therefore recommended.
If ceramic output capacitors are used, the capacitor RMS ripple current rating will always meet the application
requirements. The RMS ripple current is calculated as:
1 * Vout
1
Vin
I RMSCout + Vout
ƒ
L
2
Ǹ3
(8)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
DVout + Vout
1 * Vout
Vin
L
ƒ
ǒ8
1
Cout
ƒ
Ǔ
) ESR
(9)
Where the highest output voltage ripple occurs at the highest input voltage VIN.
At light load currents the converters operate in power-save mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Higher output capacitors like 22 μF values minimize the voltage ripple in PFM mode and tighten DC
output accuracy in PFM mode.
8.2.2.1.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10 μF. The input capacitor can be increased
without any limit for better input voltage filtering.
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
21
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
8.2.3 Application Curves
100
90
100
VOUT = 1.2 V
90
80
80
70
70
MODE/DATA = Low
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
60
50
40
30
Efficiency - %
Efficiency - %
VOUT = 1.5 V
MODE/DATA = High
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
50
40
30
20
20
10
10
0
0.01
0.1
1
10
IOUT - mA
100
MODE/DATA = Low
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
60
0
0.01
1000
Figure 15. Efficiency VOUT = 1.2 V
1
10
IOUT - mA
100
1000
Figure 16. Efficiency VOUT = 1.5 V
100
90
0.1
MODE/DATA = High
VIN = 5 V
VIN = 3.7 V
VIN = 3.3 V
VIN = 2.7 V
100
VOUT = 1.8 V
90
VOUT = 3.3 V
80
70
70
VIN = 2.7 V
60
VIN = 2.7 V
VIN = 3.6 V
50
VIN = 3.6 V
VIN = 5 V
40
Efficiency - %
Efficiency - %
VIN = 3.6 V
80
VIN = 5 V
30
20
60
40
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
Forced PWM Mode
MODE/DATA = 1
Power Save Mode
MODE/DATA = 0
10
0.1
1
10
IOUT - mA
100
0
0.01
1000
0.1
1
100
MODE/DATA = 0
VOUT = 1.575 V
10
IOUT - mA
100
IOUT = 100 mA
MODE/DATA = 0
VOUT = 3.3 V
IOUT = 10 mA
IOUT = 200 mA
90
1000
Figure 18. Efficiency VOUT2 = 3.3 V
100
95
VIN = 5 V
20
Figure 17. Efficiency VOUT2 = 1.8 V
90
IOUT = 10 mA
85
80
Efficiency
Efficiency
VIN = 5 V
50
30
10
0
0.01
VIN = 3.6 V
IOUT = 1 mA
75
70
IOUT = 1 mA
80
70
65
60
60
55
50
50
2
22
3
4
5
6
3
4
5
VIN - V
VIN - V
Figure 19. Efficiency vs VIN , VOUT = 1.575 V
Figure 20. Efficiency vs VIN, VOUT = 3.3 V
Submit Documentation Feedback
6
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
3.400
1.575
VOUT = 1.5 V
VOUT = 3.3 V
MODE/DATA = low, PFM Mode, Voltage Positioning Active
1.550
VIN = 5 V
MODE/DATA = low, PFM Mode, Voltage Positioning Active
VOUT DC - V
VIN = 3.3 V
VIN = 2.7 V
1.500
1.475
VIN = 2.7 V
VIN = 3.3 V
VIN = 3.7 V
VIN = 5 V
VIN = 3.7 V
VOUT DC - V
VIN = 5 V
1.525
PWM Mode
Operation
3.350
VIN = 3.7 V
3.300
VIN = 3.7 V
VIN = 4.2 V
VIN = 4.2 V
VIN = 5 V
MODE/DATA = high, forced PWM Mode
3.250
1.450
MODE/DATA = high, forced PWM Mode
1.425
0.01
0.1
1
10
IOUT - mA
100
1000
Figure 21. DC Output Accuracy VOUT1 = 1.5 V
Power Save Mode
Mode/Data = low
IOUT = 10mA
3.200
0.01
0.1
1
10
IOUT - mA
100
1000
Figure 22. DC Output Accuracy VOUT2 = 3.3 V
Mode/Data = high,
forced PWM MODE operation
IOUT = 10mA
VOUT = 1.8V 20mV/Div
VOUT = 1.8V 20mV/Div
Inductor current 100mA/Div
Inductor current 100mA/Div
Time base - 10 ms/Div
Time base - 400 ns/Div
Figure 23. Light-Load Output Voltage Ripple in
Power-Save Mode
Figure 24. Output Voltage Ripple in Forced PWM Mode
PWM MODE OPERATION
VOUT ripple 20mV/Div
VOUT = 1.8V
IOUT = 400mA
Forced PWM
Mode
MODE/DATA 1V/Div
Enable Power Save Mode
Entering PFM Mode
Voltage positioning active
VOUT 20mV/Div
Inductor current 200mA/Div
VOUT = 1.8V
IOUT = 20mA
Time base - 20 ms/Div
Time base - 200 ns/Div
Figure 25. Output Voltage Ripple in PWM Mode
Figure 26. Forced PWM/PFM Mode Transition
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
23
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
VOUT = 1.575V
50mV/Div
www.ti.com
MODE/DATA = low
Voltage positioning in PFM
Mode reduces voltage drop
during load step
MODE/DATA = high
PWM Mode operation
VOUT = 1.575V
50mV/Div
PWM Mode operation
IOUT1 = 540mA
IOUT1 = 540mA
IOUT 200mA/Div
IOUT 200mA/Div
IOUT= 60mA
IOUT= 60mA
Time base - 100 ms/Div
Time base - 100 ms/Div
Figure 27. Load Transient Response PFM/PWM
VIN 3.6V to 4.6V
VIN 1V/Div
MODE/DATA = high
Figure 28. Load Transient Response PWM Operation
EN1 / EN2 5V/Div
VIN = 3.8V
IOUT1 max = 400mA
VOUT1
500mV/Div
VOUT 1.575
IOUT 200mA
SW1 1V/Div
VOUT 50mV/Div
Icoil 500mA/Div
Time base - 200 ms/Div
Time base - 400 ms/Div
Figure 29. Line Transient Response
Figure 30. Start-Up Timing One Converter
SW1 5V/Div
SW1 5V/Div
I coil1 200mA/Div
I coil1 200mA/Div
SW2 5V/Div
SW2 5V/Div
Icoil2 200mA/Div
Icoil2 200mA/Div
VIN 3.6V,
VOUT1 : 1.8V
VOUT2 : 3.0V
I OUT1 = I OUT2 = 200mA
VIN 3.6V,
VOUT1: 1.575V
VOUT2: 1.8V
I OUT1 = IOUT2 = 200mA
Time base - 100 ns/Div
Time base - 100 ns/Div
Figure 31. Typical Operation VIN = 3.6 V, VOUT1 = 1.575 V,
VOUT2 = 1.8 V
24
Figure 32. Typical Operation VIN = 3.6 V, VOUT1 = 1.8 V,
VOUT2 = 3 V
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
SW1 5V/Div
I coil1 200mA/Div
SW2 5V/Div
I coil2 200mA/Div
VIN 3.6V,
VOUT1 : 1.2V
VOUT2 : 1.2V
I OUT1 = I OUT2 = 200mA
Time base - 100 ns/Div
Figure 33. Typical Operation VIN = 3.6 V, VOUT1 = 1.2 V, VOUT2 = 1.2 V
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
25
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
9 Power Supply Recommendations
The TPS62410 device has no special requirements for its input power supply. The input power supply's output
current needs to be rated according to the supply voltage, output voltage and output current of the TPS62410.
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Take care in the board layout to get the specified performance. If the
layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as
EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short
traces for the main current paths as indicated in bold in Figure 34.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor.
Connect the GND pin of the device to the PowerPAD of the PCB and use this pad as a star point. For each
converter use a common power GND node and a different node for the signal GND to minimize the effects of
ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the
common path to the GND pin, which returns the small signal components and the high current of the output
capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB1, ADJ2, DEF_1)
should be connected right to the output capacitor and routed away from noisy components and traces (that is,
SW line). If the EasyScale™ interface is operated with high transmission rates, the MODE/DATA trace must be
routed away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the
MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
10.2 Layout Example
TPS62410
VIN = 2.5 to 6 V
VIN
EN1
CIN
10 µF
EN2
MODE/DATA
FB1
L2
SW2
C(OUT2
Cff2
33 pF R21
3.3 µH
L1
3.3 µH
R11
ADJ2
R22
SW1
COUT2
DEF_1
R12
Thermal Pad
GND
Figure 34. Layout Diagram
26
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
TPS62410
www.ti.com
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
Layout Example (continued)
COUT1
CIN
GND Pin
connected
with thermal
pad
COUT2
Figure 35. PCB Layout
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
27
TPS62410
SLVS737A – FEBRUARY 2007 – REVISED JULY 2015
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
EasyScale, OMAP, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
Submit Documentation Feedback
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: TPS62410
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62410DRCR
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCRG4
ACTIVE
VSON
DRC
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCT
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
TPS62410DRCTG4
ACTIVE
VSON
DRC
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CAT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
