TPS62698YFDR

TPS62692, TPS62693 TPS62694, TPS62698 CSP-6 www.ti.com SLVSAZ1 – DECEMBER 2012 800-mA , 3-MHz HIGH-EFFICIENCY STEP-DOWN CONVERTER Check for Samples: TPS62692, TPS62693, TPS62694, TPS62698 FEATURES 1 • • • • • • • • • • • • 23 • • • • • 95% Efficiency at 3MHz Operation 21 μA Quiescent Current 3 MHz Regulated Frequency Operation Spread Spectrum, PWM Frequency Dithering High Duty-Cycle Operation ±2% Total DC Voltage Accuracy Best in Class Load and Line Transient Excellent AC Load Regulation Low Ripple Light-Load PFM Mode ≥40 dB VIN PSRR (1 kHz to 10 kHz) Internal Soft Start, 350-μs Start-Up Time Integrated Active Power-Down Sequencing (Optional) Current Overload and Thermal Shutdown Protection Three Surface-Mount External Components Required (One 2012 MLCC Inductor, Two 0402 Ceramic Capacitors) Complete Sub 1-mm Component Profile Solution Total Solution Size RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the measurements match with the theoretical calculations. LOW DROPOUT, 100% DUTY CYCLE OPERATION The device starts to enter 100% duty cycle mode once input and output voltage come close together. In order to maintain the output voltage, the P-channel MOSFET is turned on 100% for one or more cycles. With further decreasing VIN the high-side switch is constantly turned on, thereby providing a low input-to-output voltage difference. This is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: ( VINmin = VOUT max + IOUT max ´ RDS(on)max + RL (1) ) (4) Spectrum illustrations and formulae (Figure 39 and Figure 40 ) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005. See REFERENCES Section for full citation. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 19 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com With: IOUTmax = Maximum output current, plus inductor ripple current. RDS(on)max = Maximum P-channel MOSFET RDS(on). RL = Inductor DC resistance. VOUTmax = Nominal output voltage, plus maximum output voltage tolerance. ENABLE The TPS62692 device starts operation when EN is set high and starts up with the soft start as previously described. For proper operation, the EN pin must be terminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdown quiescent current of typically 0.2 μA. In this mode, the P and N-channel MOSFETs are turned off, the internal resistor feedback divider is disconnected, and the entire internal-control circuitry is switched off. The TPS62692 device can actively discharge the output capacitor when it turns off. The integrated discharge resistor has a typical resistance of 100 Ω. The required time to discharge the output capacitor at the output node depends on load current and the output capacitance value. SOFT START The TPS62692 has an internal soft-start circuit that limits the inrush current during start-up. This limits input voltage drops when a battery or a high-impedance power source is connected to the input of the converter. In the TPS62692, the soft start is implemented as a digital circuit increasing the switch current in steps of typically 300 mA, 700 mA, 1000 mA, and the typical switch current limit of 1250 mA. During the first phase the soft-start system progressively increases the on-time from a minimum pulse-width of 35 ns as a function of the output voltage, resulting in an current limit of approximately 300mA in this phase. The current limit transitions to the next step every 256 clocks (≈ 88us). To be able to switch from 700 mA to 1000 mA current limit step, the output voltage needs to be higher than 0.6 V (otherwise the parts keeps operating at 700 mA current limit). After the soft-start time has exceeded and the output voltage settled at its nominal value, the converter supports the full load curent. UNDERVOLTAGE LOCKOUT The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the converter from turning on the switch or rectifier MOSFET under undefined conditions. The TPS62692 device has an UVLO threshold set to 2.05V (typical). Fully functional operation is permitted down to 2.1 V input voltage. SHORT-CIRCUIT PROTECTION The TPS62692 integrates a P-channel MOSFET current limit to protect the device against heavy load or short circuits. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on. The regulator continues to limit the current on a cycle-by-cycle basis. As soon as the output voltage falls below ca. 0.4 V, the converter current limit is reduced to half of the nominal value. Because the short-circuit protection is enabled during start-up, the device does not deliver more than half of its nominal current limit until the output voltage exceeds approximately 0.5 V. This needs to be considered when a load acting as a current sink is connected to the output of the converter. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds typically 140°C, the device goes into thermal shutdown. In this mode, the P- and N-channel MOSFETs are turned off. The device continues its operation when the junction temperature again falls below typically 130°C. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 APPLICATION INFORMATION INDUCTOR SELECTION The TPS62692 series of step-down converters have been optimized to operate with an effective inductance value in the range of 0.5μH to 1.8μH and with output capacitors in the range of 4.7 μF to 10 μF. The internal compensation is optimized to operate with an output filter of L = 1 μH and CO = 4.7 μF. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. For more details, see the CHECKING LOOP STABILITY section. The inductor value affects its peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage ripple and the efficiency. The selected inductor has to be rated for its dc resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VI or VO. V V *V DI I O DI + O DI +I ) L L L(MAX) O(MAX) 2 V L ƒ sw I with: fSW = switching frequency (4 MHz typical) L = inductor value ΔIL = peak-to-peak inductor ripple current IL(MAX) = maximum inductor current (5) In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (i.e. quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor size, increased inductance usually results in an inductor with lower saturation current. The total losses of the coil consist of both the losses in the DC resistance (DC)) and the following frequencydependent components: • The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) • Additional losses in the conductor from the skin effect (current displacement at high frequencies) • Magnetic field losses of the neighboring windings (proximity effect) • Radiation losses The following inductor series from different suppliers have been used with the TPS6269x converters. Table 1. List of Inductors MANUFACTURER MURATA SERIES DIMENSIONS (in mm) LQM21PN1R0NGC 2.0 x 1.2 x 1.0 max. height LQM21PN1R5MC0 2.0 x 1.2 x 0.55 max. height FDK MIPS2012D1R0-X2 2.0 x 1.2 x 1.0 max. height TAIYO YUDEN NM2012N1R0M 2.0 x 1.2 x 1.0 max. height MDT2012-CH1R0A 2.0 x 1.2 x 1.0 max. height MDT2012-CR1R0 2.0 x 1.2 x 1.0 max. height TOKO Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 21 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com OUTPUT CAPACITOR SELECTION The advanced fast-response voltage mode control scheme of the TPS62692 allows the use of tiny ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are recommended. For best performance, the device should be operated with a minimum effective output capacitance of 2μF. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. At nominal load current, the device operates in PWM mode and the overall output voltage ripple is the sum of the voltage step caused by the output capacitor ESL and the ripple current flowing through the output capacitor impedance. At light loads, the output capacitor limits the output ripple voltage and provides holdup during large load transitions. A 4.7 μF or 10 μF ceramic capacitor typically provides sufficient bulk capacitance to stabilize the output during large load transitions. The typical output voltage ripple is ca. 0.5% to 1.5% of the nominal output voltage VO. The output voltage ripple during PFM mode operation can be kept small. The PFM pulse is time controlled, which allows to modify the charge transferred to the output capacitor by the value of the inductor. The resulting PFM output voltage ripple and PFM frequency depend in first order on the size of the output capacitor and the inductor value. The PFM frequency decreases with smaller inductor values and increases with larger once. Increasing the output capacitor value and the effective inductance will minimize the output ripple voltage. INPUT CAPACITOR SELECTION Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required to prevent large voltage transients that can cause misbehavior of the device or interferences with other circuits in the system. For most applications, a 2.2 or 4.7-μF capacitor is sufficient. If the application exhibits a noisy or erratic switching frequency, the remedy should be found by experimenting with the value of the input capacitor. Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed between CI and the power source lead to reduce ringing than can occur between the inductance of the power source leads and CI. CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switching node, SW • Inductor current, IL • Output ripple voltage, VO(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply all of the current required by the load. VO immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of CO. ΔI(LOAD) begins to charge or discharge CO generating a feedback error signal used by the regulator to return VO to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VO can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 LAYOUT CONSIDERATIONS As for all switching power supplies, the layout is an important step in the design. High-speed operation of the TPS6269x devices demand careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor line and/or load regulation, stability and switching frequency issues as well as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the main current paths. The ground pins of the dc/dc converter must be strongly connected to the PCB ground (i.e. reference potential across the system). These ground pins serve as the return path for both the control circuitry and the synchronous rectifier. Furthermore, due to its high frequency switching circuitry, it is imperative for the input capacitor to be as close to the SMPS device as possible, and that there is an unbroken ground plane under the TPS6269x and its external passives. Additionally, minimizing the area between the SW pin trace and inductor will limit high frequency radiated energy. The feed-back line should be routed away from noisy components and traces (e.g. SW line). The output capacitor carries the inductor ripple current. While not as critical as the input capacitor, an unbroken ground connection from this capacitor’s ground return to the inductor, input capacitor and SMPS device will reduce the output voltage ripple and it’s associated ESL step. This is a critical aspect to achieve best loop and frequency stability. High frequency currents tend to find their way on the ground plane along a mirror path directly beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias in the surrounding of the dc/dc converter leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the PCB (i.e. onto which the components are located). MODE CI L VIN ENABLE CO GND VOUT Figure 41. Suggested Layout (Top) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 23 TPS62692, TPS62693 TPS62694, TPS62698 SLVSAZ1 – DECEMBER 2012 www.ti.com THERMAL INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the powerdissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design • Improving the thermal coupling of the component to the PCB • Introducing airflow into the system The maximum recommended junction temperature (TJ) of the TPS62692 devices is 105°C. The thermal resistance of the 6-pin CSP package (YFD-6) is RθJA = 125°C/W. Regulator operation is specified to a maximum steady-state ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 160 mW. PD(MAX) = TJ(MAX) - TA 105°C - 85°C = = 160mW RqJA 125°C/W (6) REFERENCES "EMI Reduction in Switched Power Converters Using Frequency Modulation Techniques", in IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 4, NO. 3, AUGUST 2005, pp 569-576 by Josep Balcells, Alfonso Santolaria, Antonio Orlandi, David González, Javier Gago. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 TPS62692, TPS62693 TPS62694, TPS62698 www.ti.com SLVSAZ1 – DECEMBER 2012 PACKAGE SUMMARY CHIP SCALE PACKAGE (BOTTOM VIEW) D A2 A1 B2 B1 CHIP SCALE PACKAGE (TOP VIEW) YMDS CC A1 C1 C2 Code: E • YM — Year Month date Code • D — Day of laser mark • S — Assembly site code • CC— Chip code CHIP SCALE PACKAGE DIMENSIONS The TPS62692 device is available in an 6-bump chip scale package (YFD, NanoFree™). The package dimensions are given as: D E Max = 1.33 mm Max = 0.956 mm Min = 1.27 mm Min = 0.896 mm Spacer Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPS62692 TPS62693 TPS62694 TPS62698 25 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TPS62693YFDR ACTIVE DSBGA YFD 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UD TPS62693YFDT ACTIVE DSBGA YFD 6 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 UD TPS62698YFDR ACTIVE DSBGA YFD 6 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 B7 TPS62698YFDT ACTIVE DSBGA YFD 6 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 B7 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of