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TPS62736, TPS62737
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
TPS6273x Programmable Output Voltage Ultra-Low Power Buck Converter
With Up to 50 mA / 200 mA Output Current
1 Features
3
•
The TPS6273x family provides a highly integrated
ultra low power buck converter solution that is well
suited for meeting the special needs of ultra-low
power applications such as energy harvesting. The
TPS6273x provides the system with an externally
programmable regulated supply to preserve the
overall efficiency of the power-management stage
compared to a linear step-down converter. This
regulator is intended to step-down the voltage from
an energy storage element such as a battery or super
capacitor to supply the rail to low-voltage electronics.
The regulated output has been optimized to provide
high efficiency across low-output currents ( 4.6 V -> 4.6 V from bench power supply
R(OUT) = 9 Ω
Figure 57. Line Transient Response
V(IN) = 4.0 V bench supply + additional C(IN) = 100 uF
VOUT resistors modified to provide 2.5 V
I(OUT) = 200 mA every 1 us
Figure 58. IR Pulse Transient Response
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Product Folder Links: TPS62736 TPS62737
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EN1
2 V/div
2 V/div
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
VOUT
VIN-OK
1 V/div
VIN-OK
2 V/div
1 V/div 1 V/div
1 V/div
VIN
VOUT
VSW
10 s/div
20 ms/div
V(IN) = power amplifier ramped from 0 V to 5 V to 0 V
EN1 = low; EN2 = high
V(IN) = 3.6 V bench power supply
EN2 = high; EN1 transitioned from high to low
R(OUT) = 1 kΩ
Figure 60. Ship-Mode Startup Behavior
EN2
VIN-OK
VOUT
VSW
2 V/div
1 V/div
2 V/div
2 V/div
Figure 59. Startup Behavior with Slow Ramping
VIN
200 μs/div
V(IN) = 3.6 V bench power supply
EN1 = low; EN2 transitioned from low to high
R(OUT) = 1 kΩ
Figure 61. Standby-Mode Startup Behavior
24
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Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS62736 TPS62737
TPS62736, TPS62737
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SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
10.2.2 TPS62736 4-Resistor Typical Application Circuit
TPS62736
IN
VIN
CIN1
CIN2
4.7PF
0.1PF
SW
L
10 PH
System Load
OUT
22PF
Buck
Controller
GPIO1
VIN_OK
GPIO2
EN1
GPIO2
EN2
COUT
VSS
Host
VRDIV
R3
VOUT_SET
R2
R4
VIN_OK_SET
Nano-Power
Management
R1
Figure 62. TPS62736 4-Resistor Typical Application Circuit
10.2.2.1 Design Requirements
A 2.5-V, up to 50-mA regulated power rail is needed. The VIN_OK comparator should indicate when the input
voltage drops below 2.9 V. No large load transients are expected.
10.2.2.2 Detailed Design Procedure
The recommended 10-µH inductor (TOKO DFE252012C) and 4.7-µF input capacitor are used. Since no large
load transients are expected, the minimum 22-µF output capacitor is used. Had a large load transient been
expected, we would have sized the capacitor using ITRAN = COUT x ΔVOUT / ΔTIME where ΔVOUT is amount
of VOUT droop allowed for the time of the transient.
First set RSUM = R1 + R2 = R3 + R4 = 13 MΩ then solve Equation 4 for R1 = VBIAS x RSUM / VIN_OK = 1.21
V x 13 MΩ / 2.9 V = 5.42 MΩ → 5.36 MΩ as the closest 1 % resistor.
Then R2 = RSUM - R1 = 13 MΩ - 5.42 MΩ = 7.58 MΩ → 7.5 MΩ as the closest 1% resistor.
Solve Equation 3 for R4 = VBIAS x RSUM / VOUT = 1.21 V x 13 MΩ / 2.5 V = 6.29 MΩ → 6.34 MΩ as the
closest 1% resistor.
Finally R3 = RSUM - R3 = 13 MΩ - 6.29 MΩ = 6.71 MΩ → 6.81 MΩ as the closest 1% resistor.
These values yield VOUT = 2.51 V and VIN_OK threshold = 2.90 V.
If using 3 resistors, see Resistor Selection for guidance on sizing the resistors.
10.2.2.3 Application Curves
See efficiency, load regulation and line regulation graphs at Figure 1, Figure 7 and Figure 8 respectively.
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TPS62736, TPS62737
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
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2 V/div 10 mV/div 100 mA/div
VOUT-AC
SW
10 Ps/div
Figure 64. Steady State Operation
1 V/div
IL
1 V/div
1 V/div
VOUT-AC
SW
4 Ps/div
V(IN) = 3.0 V bench power supply
VOUT resistors changed to provide 1.8 V; L = 4.7 uH
R(OUT) = 100 kΩ
50 mA/div
VOUT-AC
40 ms/div
V(IN) = 3.0 V -> 5.0 V from bench power supply
R(OUT) = 50 Ω
Figure 67. Line Transient Response
VOUT
VRDIV
Figure 66. Sampling Waveform
20 mV/div
2 V/div
VIN
VIN
2 ms/div
V(IN) = 3.0 V bench power supply
Figure 65. Steady State Operation
10 mV/div
SW
IL
IOUT
50 mA/div
2 V/div 10 mV/div 100 mA/div
Figure 63. Steady State Operation
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VOUT-AC
2 Ps/div
V(IN) = 3.0 V bench power supply
R(OUT) = 100 kΩ
V(IN) = 3.0 V bench power supply
R(OUT) = 50 Ω
26
IL
VOUT-AC
SW
5 V/div
2 V/div 10 mV/div 50 mA/div
IL
10 Ps/div
V(IN) = 4.0 V from bench power supply + additional CIN = 100
uF
R(OUT) = open - > 50 Ω
Figure 68. Load Transient Response
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS62736 TPS62737
TPS62736, TPS62737
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
2 V/div 2 V/div 2 V/div 5 V/div
2 V/div 100 mA/div
www.ti.com
IOUT
VOUT
2 V/div
SW
4 Ps/div
V(IN) = 4.0 V from bench power supply + additional CIN = 100
uF
I(OUT) = 200 mA every 1us
VIN_OK
VOUT
SW
20 ms/div
V(IN) = 4.0 V from bench power supply
VOUT resistors modified to provide 1.8 V
EN2 = high, EN1 transitioned high to low
Figure 69. IR Pulse Transient Response
2 V/div 2 V/div 2 V/div 5 V/div
EN1
Figure 70. Ship-Mode Startup Behavior
EN2
VIN_OK
VOUT
SW
400 Ps/div
V(IN) = 4.0 V from bench power supply
VOUT resistors modified to provide 1.8 V
EN1 = low, EN2 transitioned low to high
Figure 71. Standby-Mode Startup Behavior
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Product Folder Links: TPS62736 TPS62737
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TPS62736, TPS62737
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
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11 Power Supply Recommendations
The TPS62736 / 7 ICs require a low impedance power source (e.g. battery, wall adapter) capable of providng
between 2.0 V and 5.5 V and up to 100 mA / 370 mA respectively. When the voltage at IN is less than or equal
to VOUT, the IC stops switching, turns on the high side FET and provides VOUT = VIN - ILOAD x RDS(on)HighSideFET.
12 Layout
12.1 Layout Guidelines
To minimize switching noise generation, the step-down converter (buck) power stage external components must
be carefully placed. The most critical external component for a buck power stage is its input capacitor. The bulk
input capacitor (CIN1) and high frequency decoupling capacitor (CIN2) must be placed as close as possible
between the power stage input (IN pin 1) and ground (VSS pin 12). Next, the inductor (L1) must be placed as
close as possible beween the switching node (SW pin 13) and the output voltage (OUT pin 11). Finally, the
output capacitor (COUT) should be placed as close as possible between the output voltage (OUT pin 11) and
GND (VSS pin 12). In the diagram below, the input and output capacitor grounds are connected to VSS pin 12
through vias to the bottom-layer ground plane of the PCB.
To minimize noise pickup by the high impedance voltage setting nodes (VIN_OK_SET pin 8 and VOUT_SET pin
9), the external resistors (R1, R2 and R3) should be placed so that the traces connecting the midpoints of the
string are as short as possible. In the diagram below, the connection to VOUT_SET is by a bottom layer trace.
The remaining pins are either NC pins, that should be connected to the PowerPAD™ as shown below, or digital
signals with minimal layout restrictions.
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended.
However, during board assembly, contaminants such as solder flux and even some board cleaning agents can
leave residue that may form parasitic resistors across the physical resistors and/or from one end of a resistor to
ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold
levels changing significantly from those expected per the installed resistor values. Therefore, it is highly
recommended that no ground planes be poured near the voltage setting resistors. In addition, the boards must
be carefully cleaned, possibly rotated at least once during cleaning, and then rinsed with de-ionized water until
the ionic contamination of that water is well above 50 MΩ. If this is not feasible, then it is recommended that the
sum of the voltage setting resistors be reduced to at least 5 times below the measured ionic contamination.
12.2 Layout Example
VIAS to
GND PLANE
CIN1
VIAS to
GND PLANE
CIN1
VIAS to
GND PLANE
CIN2
CIN2
VIN
VIN
1
1
COUT
L1
VOUT
R3
R2
R1
VIA to
GND PLANE
Figure 72. Recommended Layout, TPS62736
28
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COUT
L1
VOUT
R3
R2
R1
VIA to
GND PLANE
Figure 73. Recommended Layout, TPS62737
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS62736 TPS62737
TPS62736, TPS62737
www.ti.com
SLVSBO4C – OCTOBER 2012 – REVISED DECEMBER 2014
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62736
Click here
Click here
Click here
Click here
Click here
TPS62737
Click here
Click here
Click here
Click here
Click here
13.3 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2012–2014, Texas Instruments Incorporated
Product Folder Links: TPS62736 TPS62737
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS62736RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
62736
TPS62736RGYT
ACTIVE
VQFN
RGY
14
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
62736
TPS62737RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
62737
TPS62737RGYT
ACTIVE
VQFN
RGY
14
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
62737
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of