TPS628501, TPS628502, TPS628503
SLUSEC8A – MARCH 2021 – REVISED JUNE 2022
TPS62850x 2.7-V to 6-V, 1-A / 2-A / 3-A Step-Down Converter in SOT583 Package
1 Features
3 Description
•
The TPS62850x is a family of pin-to-pin 1-A, 2-A
(continuous), and 3-A (peak) high efficiency, easyto-use synchronous step-down DC/DC converters.
They are based on a peak current mode control
topology. Low resistive switches allow up to 2-A
continuous output current and 3-A peak current. The
switching frequency is externally adjustable from 1.8
MHz to 4 MHz and can also be synchronized to
an external clock in the same frequency range. In
PWM and PFM mode, the TPS62850x automatically
enters power save mode at light loads to maintain
high efficiency across the whole load range. The
TPS62850x provides a 1% output voltage accuracy
in PWM mode, which helps design a power supply
with high output voltage accuracy, fulfilling tight supply
voltage requirements of digital processors and FPGA.
•
•
•
•
•
•
•
•
•
•
•
•
•
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Input voltage range: 2.7 V to 6 V
Output voltage from 0.6 V to 5.5 V
1% feedback voltage accuracy
(full temperature range)
TJ = –40°C to +150°C
Family of 1-A, 2-A (continuous), and 3-A (peak)
devices
Adjustable switching frequency and sync of
1.8 MHz to 4 MHz
Forced PWM or PWM and PFM operation
Quiescent current 17 µA (typical)
Precise ENABLE input allows:
– User-defined undervoltage lockout
– Exact sequencing
100% duty cycle mode
Active output discharge
Power-good output with window comparator
For device options with adjustable soft start, see
the TPS628511
The TPS62850x is available in an 8-pin 1.60-mm ×
2.10-mm SOT583 package.
Device Information
PART NUMBER
TPS628502
TPS62850x
R1
MODE/SYNC
R2
COMP/FSET
R CF
VOUT
PG
GND
Simplified Schematic
For all available packages, see the orderable addendum at
the end of the data sheet.
95
90
CFF
FB
EN
1.60 mm × 2.10 mm
(including pins)
100
L
0.47PH
R3
COUT
2*10 PF
0603
85
Efficiency (%)
CIN
2*10 PF
0603
(1)
SW
VIN
SOT583
TPS628503
Motor drives
Factory automation and control
Building automation
Test and measurement
General purpose POL
VIN
2.7 V - 6 V
BODY SIZE (NOM)
TPS628501
2 Applications
•
•
•
•
•
PACKAGE(1)
80
75
70
65
60
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
55
50
100P
1m
10m
100m
Output Current (A)
1
Efficiency versus IOUT, VOUT = 3.3 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................ 8
8 Parameter Measurement Information............................ 9
8.1 Schematic................................................................... 9
9 Detailed Description......................................................10
9.1 Overview................................................................... 10
9.2 Functional Block Diagram......................................... 10
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................13
10 Application and Implementation................................ 15
10.1 Application Information........................................... 15
10.2 Typical Application.................................................. 17
10.3 System Examples................................................... 27
11 Power Supply Recommendations..............................29
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 30
13 Device and Documentation Support..........................31
13.1 Device Support....................................................... 31
13.2 Receiving Notification of Documentation Updates..31
13.3 Support Resources................................................. 31
13.4 Trademarks............................................................. 31
13.5 Electrostatic Discharge Caution..............................31
13.6 Glossary..................................................................31
14 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2021) to Revision A (June 2022)
Page
• Added TPS628503............................................................................................................................................. 3
2
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5 Device Comparison Table
DEVICE NUMBER
OUTPUT
CURRENT
VOUT
DISCHARGE
FOLDBACK
CURRENT LIMIT
SPREAD SPECTRUM
CLOCKING (SSC)
SOFT START
OUTPUT
VOLTAGE
TPS628501DRLR
1A
ON
OFF
by COMP/FSET pin
internal 1 ms
adjustable
TPS628502DRLR
2A
ON
OFF
by COMP/FSET pin
internal 1 ms
adjustable
TPS628503DRLR
3A
ON
OFF
by COMP/FSET pin
internal 1 ms
adjustable
GND
SW
PG
EN
MODE/SYNC
6 Pin Configuration and Functions
FB
VIN
COMP/FSET
1
Figure 6-1. 8-Pin SOT583 DRL Package (Top View)
Table 6-1. Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
EN
2
I
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
FB
5
I
Voltage feedback input. Connect the resistive output voltage divider to this pin.
GND
8
MODE/SYNC
3
I
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected. The mode pin can
also be used to synchronize the device to an external frequency. See Section 7.5 for the
detailed specification for the digital signal applied to this pin for external synchronization.
COMP/FSET
4
I
Device compensation and frequency set input. A resistor from this pin to GND defines
the compensation of the control loop as well as the switching frequency if not externally
synchronized.
PG
6
O
Open-drain power-good output
SW
7
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
VIN
1
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
Ground pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
Pin voltage(2)
Tstg
(1)
(2)
(3)
MAX
VIN
–0.3
6.5
SW (DC)
–0.3
VIN + 0.3
SW (AC, less than 10 ns)(3)
–3
10
COMP/FSET, PG
–0.3
VIN + 0.3
EN, MODE/SYNC, FB
–0.3
6.5
Storage temperature
–65
150
UNIT
V
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltage values are with respect to the network ground terminal
While switching
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN
MAX
UNIT
VIN
Input voltage range
2.7
6
V
VOUT
Output voltage range
0.6
5.5
V
L
Effective inductance
0.32
0.47
1.2
μH
COUT
Effective output capacitance(1)
8
10
200
μF
5
10
4.5
100
kΩ
CIN
Effective input
capacitance(1)
RCF
μF
ISINK_PG
Sink current at PG pin
0
2
mA
IOUT
Output current, TPS628503(2)
0
3
A
TJ
Junction temperature
–40
150
°C
(1)
(2)
4
NOM
The values given for all the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC bias
effect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check the
manufacturer's DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see the
feature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.
This part is designed for a 2-A continuous output current at a junction temperature of 105°C or 3-A continuous output current at a
junction temperature of 85°C; exceeding the output current or the junction temperature can significantly reduce lifetime.
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7.4 Thermal Information
THERMAL METRIC(1)
DRL (JEDEC)(2)
DRL (EVM)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
110
60
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.3
n/a
°C/W
RθJB
Junction-to-board thermal resistance
20
n/a
°C/W
ΨJT
Junction-to-top characterization parameter
0.8
n/a
°C/W
YJB
Junction-to-board characterization parameter
20
n/a
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
JEDEC standard PCB with four layers, no thermal vias
7.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Quiescent current
EN = VIN, no load, device not switching,
MODE = GND, VOUT = 0.6 V
17
36
μA
ISD
Shutdown current
EN = GND, nominal value at TJ = 25°C,
maximum value at TJ = 150°C
1.5
48
μA
ISD
Shutdown current
EN = GND, TJ = –40°C to 85°C, including
HSFET leakage
5.5
μA
VUVLO
Undervoltage lockout threshold
TJSD
VIN rising
2.45
2.6
2.7
V
VIN falling
2.1
2.5
2.6
V
Thermal shutdown threshold
TJ rising
170
°C
Thermal shutdown hysteresis
TJ falling
15
°C
CONTROL and INTERFACE
VEN,IH
Input threshold voltage at EN, rising edge
1.05
1.1
1.15
V
VEN,IL
Input threshold voltage at EN, falling edge
0.96
1.0
1.05
V
VIH
High-level input-threshold voltage at
MODE/SYNC
IEN,LKG
Input leakage current into EN
125
nA
VIL
Low-level input-threshold voltage at
MODE/SYNC
0.3
V
ILKG
Input leakage current into MODE/SYNC
100
nA
tDelay
Enable delay time
Time from EN high to device starts
switching; VIN applied already
520
µs
tDelay
Enable delay time
Time from EN high to device starts
switching; VIN applied already,
VIN ≥ 3.3 V
480
µs
tRamp
Output voltage ramp time
Time from device starts switching to
power good; device not in current limit
1.8
ms
fSYNC
Frequency range on MODE/SYNC pin for
synchronization
1.1
V
VIH = VIN or VIL = GND
Duty cycle of synchronization signal at
MODE/SYNC
135
0.8
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1.3
1.8
4
20%
80%
Time to lock to external frequency
Resistance from COMP/FSET to GND for Internal frequency setting with
logic low
f = 2.25 MHz
200
50
0
MHz
µs
2.5
kΩ
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Voltage on COMP/FSET for logic high
Internal frequency setting with
f = 2.25 MHz
VTH_PG
UVP power-good threshold voltage;
DC level
Rising (%VFB)
92%
95%
98%
VTH_PG
UVP power-good threshold voltage;
DC level
Falling (%VFB)
87%
90%
93%
OVP power-good threshold voltage;
DC level
Rising (%VFB)
107%
110%
113%
OVP power-good threshold voltage;
DC level
Falling (%VFB)
104%
107%
111%
VPG,OL
Low-level output voltage at PG
ISINK_PG = 2 mA
0.07
0.3
V
IPG,LKG
Input leakage current into PG
VPG = 5 V
100
nA
PG deglitch time
For a high level to low level transition on
the power-good output
VTH_PG
tPG
VIN
V
40
µs
0.6
V
OUTPUT
VFB
Feedback voltage, adjustable version
IFB,LKG
Input leakage current into FB, adjustable
version
VFB = 0.6 V
VFB
Feedback voltage accuracy
PWM, VIN ≥ VOUT + 1 V
–1%
1%
VFB
Feedback voltage accuracy
PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V,
Co,eff ≥ 10 µF, L = 0.47 µH
–1%
2%
VFB
Feedback voltage accuracy
PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V,
Co,eff ≥ 15 µF, L = 0.47 µH
–1%
3%
Load regulation
PWM
0.05
Line regulation
PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V
0.02
1
RDIS
Output discharge resistance
fSW
PWM switching frequency range
MODE = high, see the FSET pin
functionality about setting the switching
frequency.
1.8
fSW
PWM switching frequency range
MODE = low, see the FSET pin
functionality about setting the switching
frequency.
1.8
fSW
PWM switching frequency
With COMP/FSET tied to GND or VIN
2.025
fSW
PWM switching frequency tolerance
Using a resistor from COMP/FSET to
GND
–12%
ton,min
Minimum on time of high-side FET
VIN = 3.3 V, TJ = –40°C to 125°C
ton,min
Minimum on time of low-side FET
RDS(ON)
2.25
2.25
nA
%/A
%/V
100
Ω
4
MHz
3.5
MHz
2.475
MHz
12%
35
50
10
ns
ns
High-side FET on-resistance
VIN ≥ 5 V
65
120
mΩ
Low-side FET on-resistance
VIN ≥ 5 V
33
70
mΩ
High-side MOSFET leakage current
TJ = –40°C to 85°C
High-side MOSFET leakage current
Low-side MOSFET leakage current
3.5
µA
0.01
44
µA
5
µA
0.01
70
µA
11
µA
TJ = –40°C to 85°C
Low-side MOSFET leakage current
6
70
SW leakage
V(SW) = 0.6 V, current into SW pin
ILIMH
High-side FET switch current limit
DC value, for TPS628503;
VIN = 3 V to 6 V
3.45
4.5
5.1
A
ILIMH
High-side FET switch current limit
DC value, for TPS628502;
VIN = 3 V to 6 V
2.85
3.4
3.9
A
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7.5 Electrical Characteristics (continued)
Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ
= 25°C. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ILIMH
High-side FET switch current limit
DC value, for TPS628501;
VIN = 3 V to 6 V
ILIMNEG
Low-side FET negative current limit
DC value
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MIN
TYP
MAX
2.1
2.6
3.0
–1.8
UNIT
A
A
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7.6 Typical Characteristics
140
130
120
VIN
VIN
VIN
VIN
=
=
=
=
2.7V
3.3V
5.0V
6.0V
RDS(on) (m:)
RDS(on) (m:)
110
100
90
80
70
60
50
40
-40
0
25
85
Junction Temperature (°C)
125
150
Figure 7-1. RDS (ON) of High-Side Switch
8
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D002
80
76
72
68
64
60
56
52
48
44
40
36
32
28
24
20
-40
VIN
VIN
VIN
VIN
=
=
=
=
2.7V
3.3V
5.0V
6.0V
0
25
85
Junction Temperature (°C)
125
150
D002
Figure 7-2. RDS (ON) of Low-Side Switch
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8 Parameter Measurement Information
8.1 Schematic
VIN
2.7 V - 6 V
TPS62850x
VOUT
SW
VIN
CIN
2*10 PF
0603
L
0.47PH
R1
CFF
FB
EN
MODE/SYNC
R2
R3
COUT
2*10 PF
0603
R CF
COMP/FSET
PG
GND
Figure 8-1. Measurement Setup
Table 8-1. List of Components
DESCRIPTION
MANUFACTURER (1)
IC
TPS628502
Texas Instruments
L
0.47-µH inductor DFE252012PD
Murata
REFERENCE
(1)
CIN
2 × 10 µF / 6.3 V GRM188D70J106MA73
Murata
COUT
2 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT ≥ 1 V
Murata
COUT
3 × 10 µF / 6.3 V GRM188D70J106MA73 for VOUT < 1 V
Murata
RCF
8.06 kΩ
Any
CFF
10 pF
Any
R1
Depending on VOUT
Any
R2
Depending on VOUT
Any
R3
100 kΩ
Any
See the Third-party Products Disclaimer.
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9 Detailed Description
9.1 Overview
The TPS62850x synchronous switch mode power converters are based on a peak current mode control
topology. The control loop is internally compensated.
To optimize the bandwidth of the control loop to the wide range of output capacitance that can be used with
TPS62850x, the internal compensation has two settings. See Section 9.3.2. One out of the two compensation
settings is chosen either by a resistor from COMP/FSET to GND, or by the logic state of this pin. The
regulation network achieves fast and stable operation with small external components and low-ESR ceramic
output capacitors. The devices can be operated without a feedforward capacitor on the output voltage divider,
however, using a typically 10-pF feedforward capacitor improves transient response.
The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. The
frequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in a
range of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices can be
synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pin with no
need for additional passive components. An internal PLL allows the internal clock to be changed to an external
clock during operation. The synchronization to the external clock is done on a falling edge of the clock applied
at MODE to the rising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to
generate the synchronization signal for a second converter. When the MODE pin is set to a logic low level, the
device operates in power save mode (PFM) at low output current and automatically transfers to fixed frequency
PWM mode at higher output current. In PFM mode, the switching frequency decreases linearly based on the
load to sustain high efficiency down to very low output current.
9.2 Functional Block Diagram
VIN
SW
Bias
Regulator
Gate Drive and Control
Oscillator
Ipeak
EN
Izero
MODE/SYNC
gm
GND
Device
PG
Control
Bandgap
+
-
FB
COMP/FSET
Thermal
Shutdown
9.3 Feature Description
9.3.1 Precise Enable (EN)
The voltage applied at the enable pin of the TPS62850x is compared to a fixed threshold of 1.1 V for a rising
voltage. This allows the user to drive the pin by a slowly changing voltage and enables the use of an external RC
network to achieve a power-up delay.
The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to the
input of the Enable pin.
10
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The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. The
TPS62850x starts operation when the rising threshold is exceeded. For proper operation, the enable (EN) pin
must be terminated and must not be left floating. Pulling the enable pin low forces the device into shutdown, with
a shutdown current of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off
and the entire internal control circuitry is switched off.
9.3.2 COMP/FSET
This pin allows to set three different parameters:
•
•
•
Internal compensation settings for the control loop (two settings available)
The switching frequency in PWM mode from 1.8 MHz to 4 MHz
Enable/disable spread spectrum clocking (SSC)
A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The change
in compensation allows the user to adopt the device to different values of output capacitance. The resistor must
be placed close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation setting
is sampled at start-up of the converter, so a change in the resistor during operation only has an effect on the
switching frequency but not on the compensation.
To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined setting. Do not
leave the pin floating.
The switching frequency has to be selected based on the input voltage and the output voltage to meet the
specifications for the minimum on-time and minimum off-time.
Example: VIN = 5 V, VOUT = 0.6 V --> duty cycle = 0.6 V / 5 V = 0.12
•
•
--> ton,min = 1 / fs × 0.12
--> fsw,max = 1 / ton,min × 0.12 = 1 / 0.05 µs × 0.12 = 2.4 MHz
The compensation range has to be chosen based on the minimum capacitance used. The capacitance can be
increased from the minimum value as given in Table 9-1, up to the maximum of 200 µF in both compensation
ranges. If the capacitance of an output changes during operation, for example, when load switches are used to
connect or disconnect parts of the circuitry, the compensation has to be chosen for the minimum capacitance on
the output. With large output capacitance, the compensation must be done based on that large capacitance to
get the best load transient response. Compensating for large output capacitance but placing less capacitance on
the output can lead to instability.
The switching frequency for the different compensation setting is determined by the following equations.
For compensation (comp) setting 1 with spread spectrum clocking (SSC) disabled:
Space
RCF (k W) =
18MHz × k W
fS ( MHz )
(1)
For compensation (comp) setting 1 with spread spectrum clocking (SSC) enabled:
Space
RCF (k W) =
60 MHz × k W
fS ( MHz )
(2)
Space
For compensation (comp) setting 2 with spread spectrum clocking (SSC) disabled:
Space
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RCF (k W) =
180 MHz × k W
fS ( MHz )
(3)
Table 9-1. Switching Frequency, Compensation and Spread Spectrum Clocking
RCF
COMPENSATION
SWITCHING FREQUENCY
MINIMUM
OUTPUT
CAPACITANCE
FOR VOUT < 1 V
MINIMUM OUTPUT
CAPACITANCE
FOR 1 V ≤ VOUT < 3.3 V
MINIMUM OUTPUT
CAPACITANCE
FOR VOUT ≥ 3.3 V
10 kΩ .. 4.5 kΩ
for smallest output capacitance
1.8 MHz (10 kΩ) .. 4 MHz (4.5 kΩ)
(comp setting 1)
according to Equation 1
SSC disabled
15 µF
10 µF
8 µF
33 kΩ .. 15 kΩ
for smallest output capacitance
(comp setting 1)
SSC enabled
1.8 MHz (33 kΩ) .. 4 MHz (15 kΩ)
according to Equation 2
15 µF
10 µF
8 µF
100 kΩ .. 45 kΩ
for best transient response
(larger output capacitance)
(comp setting 2)
SSC disabled
1.8 MHz (100 kΩ) ..4 MHz (45 kΩ)
according to Equation 3
30 µF
18 µF
15 µF
tied to GND
for smallest output capacitance
(comp setting 1)
SSC disabled
internally fixed 2.25 MHz
15 µF
10 µF
8 µF
tied to VIN
for best transient response
(larger output capacitance)
(comp setting 2)
SSC enabled
internally fixed 2.25 MHz
30 µF
18 µF
15 µF
Refer to Section 10.1.3.2 for further details on the output capacitance required depending on the output voltage.
A resistor value that is too high for RCF is decoded as "tied to VIN". A value below the lowest range is decoded as
"tied to GND". The minimum output capacitance in Table 9-1 is for capacitors close to the output of the device. If
the capacitance is distributed, a lower compensation setting can be required.
9.3.3 MODE / SYNC
When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current.
The MODE/SYNC pin allows you to force PWM mode when set high. The pin also allows you to apply an
external clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. The specifications for
the minimum on-time and minimum off-time must be observed when setting the external frequency. For use
with external synchronization on the MODE/SYNC pin, the internal switching frequency must be set by RCF to a
similar value to the externally applied clock. This ensures that if the external clock fails, the switching frequency
stays in the same range and the compensation settings are still valid.
9.3.4 Spread Spectrum Clocking (SSC)
The device offers spread spectrum clocking as an option. When SSC is enabled, the switching frequency is
randomly changed in PWM mode when the internal clock is used. The frequency variation is typically between
the nominal switching frequency and up to 288 kHz above the nominal switching frequency. When the device is
externally synchronized by applying a clock signal to the MODE/SYNC pin, the TPS62850x follows the external
clock and the internal spread spectrum block is turned off. SSC is also disabled during soft start.
9.3.5 Undervoltage Lockout (UVLO)
If the input voltage drops, the undervoltage lockout prevents misoperation of the device by switching off both the
power FETs. When enabled, the device is fully operational for input voltages above the rising UVLO threshold
and turns off if the input voltage trips below the threshold for a falling supply voltage.
9.3.6 Power Good Output (PG)
Power good is an open-drain output that requires a pullup resistor to any voltage up to the recommended input
voltage level. It is driven by a window comparator. PG is held low when the device is disabled, in undervoltage
lockout in thermal shutdown, and not in soft start. When the output voltage is in regulation hence, within the
window defined in the electrical characteristics, the output is high impedance.
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VIN must remain present for the PG pin to stay low. If the power good output is not used, it is recommended to
tie it to GND or leave open. The PG indicator features a de-glitch, as specified in the electrical characteristics, for
the transition from "high impedance" to "low" of its output.
Table 9-2. PG Status
EN
DEVICE STATUS
PG STATE
X
VIN < 2 V
undefined
low
VIN ≥ 2 V
low
high
2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT not in regulation
OR device in soft start
low
high
VOUT in regulation
high impedance
9.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C
(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
PG goes low. When TJ decreases below the hysteresis amount of typically 15°C, the converter resumes normal
operation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,
the device needs up to 9 µs to detect a junction temperature that is too high. If the PFM burst is shorter than this
delay, the device does not detect a junction temperature that is too high.
9.4 Device Functional Modes
9.4.1 Pulse Width Modulation (PWM) Operation
The TPS62850x has two operating modes: forced PWM mode is discussed in this section and PWM/PFM as
discussed in Section 9.4.2.
With the MODE/SYNC pin set to high, the TPS62850x operates with pulse width modulation in continuous
conduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND or
by an external clock signal applied to the MODE/SYNC pin. With an external clock applied to MODE/SYNC, the
TPS62850x follows the frequency applied to the pin. In general, the frequency range in forced PWM mode is
1.8 MHz to 4 MHz. However, the frequency needs to be in a range the TPS62850x can operate at, taking the
minimum on-time into account.
9.4.2 Power Save Mode Operation (PWM/PFM)
When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as long as
the peak inductor current is above the PFM threshold of approximately 0.8 A. When the peak inductor current
drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switching
frequency decreases with the load current maintaining high efficiency. In addition, the frequency set with the
resistor on COMP/FSET must be in a range of 1.8 MHz to 3.5 MHz.
9.4.3 100% Duty-Cycle Operation
The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycle increases
as the input voltage comes close to the output voltage and the off-time gets smaller. When the minimum off-time
of typically 10 ns is reached, the TPS62850x skips switching cycles while it approaches 100% mode. In 100%
mode, it keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output
voltage is below the target. In 100% mode, the low-side switch is turned off. The maximum dropout voltage in
100% mode is the product of the on-resistance of the high-side switch plus the series resistance of the inductor
and the load current.
9.4.4 Current Limit and Short Circuit Protection
The TPS62850x is protected against overload and short circuit events. If the inductor current exceeds the
current limit ILIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down the
inductor current. The high-side switch turns on again only if the current in the low side-switch has decreased
below the low side current limit. Due to internal propagation delay, the actual current can exceed the static
current limit. The dynamic current limit is given as:
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Ipeak (typ ) = ILIMH +
VL
× tPD
L
(4)
where
•
•
•
•
ILIMH is the static current limit as specified in the Electrical Characteristics
L is the effective inductance at the peak current
VL is the voltage across the inductor (VIN - VOUT)
tPD is the internal propagation delay of typically 50 ns
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high-side switch peak current can be calculated as follows:
Ipeak (typ ) = ILIMH +
VIN - VOUT
× 50ns
L
(5)
9.4.5 Foldback Current Limit and Short Circuit Protection
This is valid for devices where foldback current limit is enabled. Contact Texas Instruments for more information
on this option.
When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the current
limit from its nominal value to typically 1.3 A. Foldback current limit is left when the current limit indication goes
away. If device operation continues in current limit, after 3072 switching cycles, it tries for full current limit for
1024 switching cycles.
9.4.6 Output Discharge
The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the device
is being disabled and to keep the output voltage close to 0 V when the device is off. The output discharge
feature is only active once the TPS62850x has been enabled at least once since the supply voltage was applied.
The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltage
lockout. The minimum supply voltage required for the discharge function to remain active is typically 2 V. Output
discharge is not activated during a current limit or foldback current limit event.
9.4.7 Soft Start
The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from high
impedance power sources or batteries. When EN is set high to start operation, the device starts switching after
a delay of about 200 μs then the internal reference and hence VOUT rises with a slope defined by an internally
defined slope of 150 µs or 1 ms (OTP option).
9.4.8 Input Overvoltage Protection
When the input voltage exceeds the absolute maximum rating, the device is set to PFM mode so it cannot
transfer energy from the output to the input.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
10.1.1 Programming the Output Voltage
The output voltage of the TPS62850x is adjustable. It can be programmed for output voltages from 0.6 V to 5.5
V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The value of
the output voltage is set by the selection of the resistor divider from Equation 6. It is recommended to choose
resistor values that allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lower
resistor values are recommended for highest accuracy and the most robust design.
æ VOUT ö
R1 = R 2 × ç
- 1÷
è VFB
ø
(6)
10.1.2 Inductor Selection
The TPS62850x family is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25
MHz. Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact
on efficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple, which
causes larger negative inductor current in forced PWM mode at low or no output current. For a higher or lower
nominal switching frequency, the inductance must be changed accordingly. See Section 7.3 for details.
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 calculates the maximum inductor current.
I L(max) = I OUT (max) +
DI L(max)
2
(7)
æ VOUT ö
VOUT × ç1 ÷
VIN ø 1
è
DIL (max) =
×
L min
fSW
(8)
where
•
•
•
IL(max) is the maximum inductor current
ΔIL(max) is the peak-to-peak inductor ripple current
Lmin is the minimum inductance at the operating point
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Table 10-1. Typical Inductors
TYPE
INDUCTANCE
[µH]
CURRENT [A]
(1)
FOR DEVICE
NOMINAL
SWITCHING
FREQUENCY
DIMENSIONS
[LxBxH] mm
MANUFACTURER(2)
XFL4015-471ME
0.47 µH, ±20%
3.5
TPS628501 / 502
2.25 MHz
4 × 4 × 1.6
Coilcraft
XFL4015-701ME
0.70 µH, ±20%
3.3
TPS628501 / 502
2.25 MHz
4 × 4 × 1.6
Coilcraft
XEL3520-801ME
0.80 µH, ±20%
2.0
TPS628501 / 502
2.25 MHz
3.5 × 3.2 × 2.0
Coilcraft
XEL3515-561ME
0.56 µH, ±20%
4.5
TPS628501 / 502
2.25 MHz
3.5 × 3.2 × 1.5
Coilcraft
XFL3012-681ME
0.68 µH, ±20%
2.1
TPS628501 / 502
2.25 MHz
3.0 × 3.0 × 1.2
Coilcraft
XPL2010-681ML
0.68 µH, ±20%
1.5
TPS628501
2.25 MHz
2 × 1.9 × 1
Coilcraft
DFE252012PD-R68M
0.68 µH, ±20%
see data sheet
TPS628501 / 502
2.25 MHz
2.5 × 2 × 1.2
Murata
DFE252012PD-R47M
0.47 µH, ±20%
see data sheet
TPS628501 / 502
2.25 MHz
2.5 × 2 × 1.2
Murata
DFE201612PD-R68M
0.68 µH, ±20%
see data sheet
TPS628501 / 502
2.25 MHz
2 × 1.6 × 1.2
Murata
DFE201612PD-R47M
0.47 µH, ±20%
see data sheet
TPS628501 / 502
2.25 MHz
2 × 1.6 × 1.2
Murata
(1)
(2)
Lower of IRMS at 20°C rise or ISAT at 20% drop.
See the Third-party Products Disclaimer.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well.
10.1.3 Capacitor Selection
10.1.3.1 Input Capacitor
For most applications, 10-µF nominal is sufficient and is recommended. The input capacitor buffers the input
voltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramic
capacitor (MLCC) is recommended for the best filtering and must be placed between VIN and GND as close as
possible to those pins.
10.1.3.2 Output Capacitor
The architecture of the TPS62850x allows the use of tiny ceramic output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its low
resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended
to use X7R or X5R dielectric. Using a higher value has advantages, like smaller voltage ripple and a tighter DC
output accuracy in power save mode.
The COMP/FSET pin allows the user to select two different compensation settings based on the minimum
capacitance used on the output. The maximum capacitance is 200 µF in any of the compensation settings. The
minimum capacitance required on the output depends on the compensation setting and output voltage.
For output voltages below 1 V, the minimum increases linearly from 10 µF at 1 V to 15 µF at 0.6 V with the
compensation setting for smallest output capacitance. Other compensation ranges are equivalent. See Table 9-1
for details.
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10.2 Typical Application
VIN
2.7 V - 6 V
L
0.47PH
TPS62850x
CIN
2*10 PF
0603
VOUT
SW
VIN
R1
CFF
FB
EN
MODE/SYNC
R2
R3
COUT
2*10 PF
0603
R CF
COMP/FSET
PG
GND
Figure 10-1. Typical Application
10.2.1 Design Requirements
The design guidelines provide a component selection to operate the device within the recommended operating
conditions.
10.2.2 Detailed Design Procedure
æ VOUT ö
R1 = R 2 × ç
- 1÷
è VFB
ø
(9)
With VFB = 0.6 V:
Table 10-2. Setting the Output Voltage
NOMINAL OUTPUT VOLTAGE
VOUT
R1
R2
CFF
EXACT OUTPUT VOLTAGE
0.8 V
16.9 kΩ
51 kΩ
10 pF
0.7988 V
1.0 V
20 kΩ
30 kΩ
10 pF
1.0 V
1.1 V
39.2 kΩ
47 kΩ
10 pF
1.101 V
1.2 V
68 kΩ
68 kΩ
10 pF
1.2 V
1.5 V
76.8 kΩ
51 kΩ
10 pF
1.5 V
1.8 V
80.6 kΩ
40.2 kΩ
10 pF
1.803 V
2.5 V
47.5 kΩ
15 kΩ
10 pF
2.5 V
3.3 V
88.7 kΩ
19.6 kΩ
10 pF
3.315 V
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10.2.3 Application Curves
All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unless
otherwise noted. The BOM is according to Table 8-1.
100
100
95
95
90
Efficiency (%)
Efficiency (%)
85
80
75
70
90
85
65
60
50
100P
80
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
55
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
75
1m
10m
100m
Output Current (A)
VOUT = 3.3 V
PFM
1
0
3
TA = 25°C
0.5
1
VOUT = 3.3 V
Figure 10-2. Efficiency Versus Output Current
1.5
2
Output Current (A)
PWM
2.5
3
TA = 25°C
Figure 10-3. Efficiency Versus Output Current
95
100
95
90
90
Efficiency (%)
Efficiency (%)
85
80
75
70
65
VIN
VIN
VIN
VIN
VIN
60
55
50
100P
1m
10m
100m
Output Current (A)
VOUT = 1.8 V
PFM
=
=
=
=
=
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
1
85
80
75
VIN
VIN
VIN
VIN
VIN
70
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
65
3
0
TA = 25°C
0.5
1
VOUT = 1.8 V
Figure 10-4. Efficiency Versus Output Current
=
=
=
=
=
1.5
2
Output Current (A)
PWM
3
TA = 25°C
Figure 10-5. Efficiency Versus Output Current
95
100
95
90
90
85
Efficiency (%)
Efficiency (%)
85
80
75
70
65
VIN
VIN
VIN
VIN
VIN
60
55
50
100P
1m
10m
100m
Output Current (A)
VOUT = 1.1 V
PFM
=
=
=
=
=
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
1
TA = 25°C
Figure 10-6. Efficiency Versus Output Current
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80
75
70
VIN
VIN
VIN
VIN
VIN
65
60
3
=
=
=
=
=
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
55
0
0.5
1
VOUT = 1.1 V
1.5
2
Output Current (A)
PWM
2.5
3
TA = 25°C
Figure 10-7. Efficiency Versus Output Current
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90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
75
70
65
60
55
VIN
VIN
VIN
VIN
50
45
40
100P
=
=
=
=
2.7
3.3
4.0
5.0
V
V
V
V
65
60
VIN
VIN
VIN
VIN
55
50
10m
100m
Output Current (A)
PFM
1
0
3
TA = 25°C
3.33
3.324
3.318
3.318
3.312
3.312
Output Voltage (V)
3.33
3.306
3.3
3.294
3.288
3.27
100P
1m
10m
100m
Output Current (A)
VOUT = 3.3 V
PFM
1
V
V
V
V
TA = 25°C
Output Voltage (V)
1.808
1.804
1.8
1.796
VOUT = 1.8 V
V
V
V
V
V
TA = 25°C
Figure 10-12. Output Voltage Versus Output
Current
3
TA = 25°C
1.8
1.796
1.792
1.784
PFM
PWM
1
1.804
1.788
1
10m
100m
Output Current (A)
Figure 10-11. Output Voltage Versus Output
Current
1.812
10m
100m
Output Current (A)
1m
VOUT = 3.3 V
1.808
1m
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.27
100P
3
1.812
1.78
100P
TA = 25°C
3.288
1.82
2.7
3.3
4.0
5.0
6.0
3
3.3
1.816
=
=
=
=
=
PWM
2.5
3.294
1.82
1.784
2.7
3.3
4.0
5.0
3.306
1.816
VIN
VIN
VIN
VIN
VIN
1.5
2
Output Current (A)
3.276
Figure 10-10. Output Voltage Versus Output
Current
1.788
1
3.282
VIN = 4.0 V
VIN = 5.0 V
VIN = 6.0 V
3.276
1.792
=
=
=
=
Figure 10-9. Efficiency Versus Output Current
3.324
3.282
0.5
VOUT = 0.6 V
Figure 10-8. Efficiency Versus Output Current
Output Voltage (V)
70
45
1m
VOUT = 0.6 V
Output Voltage (V)
75
3
VIN
VIN
VIN
VIN
VIN
=
=
=
=
=
1.78
100P
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
1m
VOUT = 1.8 V
10m
100m
Output Current (A)
PWM
1
3
TA = 25°C
Figure 10-13. Output Voltage Versus Output
Current
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1.11
1.11
1.108
1.108
1.106
1.106
1.104
1.104
Output Voltage (V)
Output Voltage (V)
SLUSEC8A – MARCH 2021 – REVISED JUNE 2022
1.102
1.1
1.098
1.096
1.094
1.092
VIN
VIN
VIN
VIN
VIN
=
=
=
=
=
1.09
100P
2.7
3.3
4.0
5.0
6.0
V
V
V
V
V
1m
10m
100m
Output Current (A)
PFM
1
TA = 25°C
0.606
0.6045
0.608
0.603
0.606
0.604
0.602
0.6
0.596
=
=
=
=
0.594
100P
2.7
3.3
4.0
5.0
1m
PFM
1
55
VOUT = 0.6 V
PWM
105
115
125
θJA = 60°C/W
Figure 10-18. Output Current Versus Ambient
Temperature
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TA = 25°C
VIN
VIN
VIN
VIN
=
=
=
=
2.7
3.3
4.0
5.0
V
V
V
V
1m
10m
100m
Output Current (A)
PWM
1
3
TA = 25°C
Figure 10-17. Output Voltage Versus Output
Current
Output Current (A)
65
75
85
95
Ambient temperature (qC)
3
0.6
VOUT = 0.6 V
TA = 25°C
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
45
PWM
1
0.5985
0.594
100P
3
Figure 10-16. Output Voltage Versus Output
Current
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
35
10m
100m
Output Current (A)
0.6015
0.5955
VOUT = 0.6 V
V
V
V
V
V
1m
0.597
V
V
V
V
10m
100m
Output Current (A)
2.7
3.3
4.0
5.0
6.0
Figure 10-15. Output Voltage Versus Output
Current
0.61
VIN
VIN
VIN
VIN
=
=
=
=
=
VOUT = 1.1 V
0.612
0.598
VIN
VIN
VIN
VIN
VIN
1.09
100P
3
Output Voltage (V)
Output Voltage (V)
1.096
1.092
Figure 10-14. Output Voltage Versus Output
Current
Output Current (A)
1.1
1.098
1.094
VOUT = 1.1 V
20
1.102
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
35
VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
45
55
65
75
85
95
Ambient temperature (qC)
VOUT = 1.1 V
PWM
105
115
125
θJA = 60°C/W
Figure 10-19. Output Current Versus Ambient
Temperature
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3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
35
SLUSEC8A – MARCH 2021 – REVISED JUNE 2022
Output Current (A)
Output Current (A)
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VIN=2.7V
VIN=3.3V
VIN=4.2V
VIN=5.0V
VIN=6.0V
45
55
VOUT = 1.8 V
65
75
85
95
Ambient temperature (qC)
PWM
105
115
125
θJA = 60°C/W
Figure 10-20. Output Current Versus Ambient
Temperature
VOUT = 3.3 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-22. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-24. Load Transient Response
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
35
VIN=4.2V
VIN=5.0V
VIN=6.0V
45
55
65
75
85
95
Ambient temperature (qC)
VOUT = 3.3 V
PWM
105
115
125
θJA = 60°C/W
Figure 10-21. Output Current Versus Ambient
Temperature
VOUT = 3.3 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-23. Load Transient Response
VOUT = 1.8 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-25. Load Transient Response
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VOUT = 1.2 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-26. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-28. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-30. Load Transient Response
22
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VOUT = 1.2 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-27. Load Transient Response
VOUT = 1.0 V
VIN = 5.0 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-29. Load Transient Response
VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 0.2 A to 1.8 A to 0.2 A
Figure 10-31. Load Transient Response
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VOUT = 3.3 V
IOUT = 0.2 A
SLUSEC8A – MARCH 2021 – REVISED JUNE 2022
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
VOUT = 3.3 V
IOUT = 2 A
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-32. Line Transient Response
Figure 10-33. Line Transient Response
VOUT = 1.8 V
IOUT = 0.2 A
VOUT = 1.8 V
IOUT = 2 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-34. Line Transient Response
Figure 10-35. Line Transient Response
VOUT = 1.2 V
IOUT = 0.2 A
VOUT = 1.2 V
IOUT = 2 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-36. Line Transient Response
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-37. Line Transient Response
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VOUT = 1.0 V
IOUT = 0.2 A
PFM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
PWM
TA = 25°C
VIN = 4.5 V to 5.5 V to 4.5 V
Figure 10-38. Line Transient Response
Figure 10-39. Line Transient Response
VOUT = 0.6 V
IOUT = 0.2 A
VOUT = 0.6 V
IOUT = 2 A
PFM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
PWM
TA = 25°C
VIN = 3.0 V to 3.6 V to 3.0 V
Figure 10-40. Line Transient Response
Figure 10-41. Line Transient Response
VOUT = 3.3 V
VIN = 5 V
VOUT = 3.3 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
Figure 10-42. Output Voltage Ripple
24
VOUT = 1.0 V
IOUT = 2 A
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PWM
TA = 25°C
IOUT = 2 A
Figure 10-43. Output Voltage Ripple
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VOUT = 1.8 V
VIN = 5 V
SLUSEC8A – MARCH 2021 – REVISED JUNE 2022
PFM
TA = 25°C
IOUT = 0.2 A
Figure 10-44. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
Figure 10-46. Output Voltage Ripple
VOUT = 1.0 V
VIN = 5 V
PFM
TA = 25°C
IOUT = 0.2 A
Figure 10-48. Output Voltage Ripple
VOUT = 1.8 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
Figure 10-45. Output Voltage Ripple
VOUT = 1.2 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
Figure 10-47. Output Voltage Ripple
VOUT = 1.0 V
VIN = 5 V
PWM
TA = 25°C
IOUT = 2 A
Figure 10-49. Output Voltage Ripple
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VOUT = 0.6 V
VIN = 3.3 V
PFM
TA = 25°C
IOUT = 0.2 A
Figure 10-50. Output Voltage Ripple
VOUT = 3.3 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
Figure 10-52. Start-Up Timing
VOUT = 1.2 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
Figure 10-54. Start-Up Timing
26
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VOUT = 0.6 V
VIN = 3.3 V
PWM
TA = 25°C
IOUT = 2 A
Figure 10-51. Output Voltage Ripple
VOUT = 1.8 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
Figure 10-53. Start-Up Timing
VOUT = 1.0 V
VIN = 5 V
PWM or PFM
TA = 25°C
IOUT = 2 A
Figure 10-55. Start-Up Timing
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VOUT = 0.6 V
VIN = 3.3 V
PWM or PFM
TA = 25°C
IOUT = 2 A
Figure 10-56. Start-Up Timing
10.3 System Examples
10.3.1 Synchronizing to an External Clock
The TPS62850x can be externally synchronized by applying an external clock on the MODE/SYNC pin. There is
no need for any additional circuitry as long as the input signal meets the requirements given in the electrical
specifications. The clock can be applied / removed during operation, allowing an externally defined fixed
frequency to be switched to a power-save mode or to internal fixed frequency operation.
The value of the RCF resistor must be chosen such that the internally defined frequency and the externally
applied frequency are close to each other. This ensures a smooth transition from internal to external frequency
and vice versa.
VIN
2.7 V - 6 V
L
0.47 PH
TPS62850x
VIN
CIN
2*10 PF
0603
VOUT
SW
R1
EN
CFF
FB
MODE/SYNC
R2
COUT
2*10 PF
0603
R3
fEXT
R CF
COMP/FSET
PG
GND
Figure 10-57. Schematic using External Synchronization
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VIN = 5 V
VOUT = 1.8 V
RCF = 8.06 kΩ
fEXT = 2.5 MHz
IOUT = 0.1 A
Figure 10-58. Switching from External
Syncronization to Power-Save Mode (PFM)
28
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VIN = 5 V
VOUT = 1.8 V
RCF = 8.06 kΩ
fEXT = 2.5 MHz
IOUT = 0.1 A
Figure 10-59. Switching from External
Synchronizaion to Internal Fixed Frequency
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11 Power Supply Recommendations
The TPS62850x device family does not have special requirements for its input power supply. The output current
of the input power supply needs to be rated according to the supply voltage, output voltage, and output current
of the TPS62850x.
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore, the PCB layout of the TPS62850x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like the following:
• Poor regulation (both in Section 12.2 and load)
• Stability and accuracy weaknesses
• Increased EMI radiation
• Noise sensitivity
See Figure 12-1 for the recommended layout of the TPS62850x, which is designed for common external ground
connections. The input capacitor must be placed as close as possible between the VIN and GND pin.
Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load
current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes)
for wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to
the IC pins and parallel wiring over long distances and narrow traces must be avoided. Loops which conduct
an alternating current must outline an area as small as possible since this area is proportional to the energy
radiated.
Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for example,
SW). As they carry information about the output voltage, they must be connected as close as possible to the
actual output voltage (at the output capacitor). The FB resistors, R1 and R2, must be kept close to the IC and be
connected directly to the pin and the system ground plane.
The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help to spread the heat
into the PCB.
The recommended layout is implemented on the EVM and shown in the TPS628502EVM-092 Evaluation
Module User's Guide.
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12.2 Layout Example
COUT
V
GND
IN
PG
GND
SW
MODE
U1
COMP
EN
R2
VIN
V
FB
L
Solution size = 30mm2
CIN
Cff
R1
OUT
R CF
GND
Figure 12-1. Example Layout
30
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
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25-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
TPS628501DRLR
ACTIVE
SOT-5X3
DRL
8
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
100
Samples
TPS628502DRLR
ACTIVE
SOT-5X3
DRL
8
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 125
200
Samples
TPS628503DRLR
ACTIVE
SOT-5X3
DRL
8
4000
RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
-40 to 150
300
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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