TPS62860, TPS62861
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1.8-V to 5.5-V Input, 0.6-/1-A Synchronous Step-Down Converter with I2C/VSEL
Interface
1 Features
3 Description
•
•
•
•
The
TPS6286x
devices
are
high-frequency
synchronous step-down converters with I2C- and
VSEL-Interface. They provide an efficient, flexible,
and high-power density point-of-load DC/DC solution.
At medium to heavy loads, the converter operates
in PWM mode and automatically enters Power
Save Mode operation at light load to maintain high
efficiency over the entire load current range. The
device can also be forced in PWM mode operation
for the smallest output voltage ripple. Together, with
its DCS-control architecture, excellent load transient
performance and tight output voltage accuracy are
achieved. With the I2C interface and a dedicated
VSEL pin, the output voltage is quickly adjusted to
adapt the power consumption of the load to the everchanging performance needs of the application. The
TPS6286x family is available with two VSEL pins and
four factory preset voltages to allow usage without I2C
interface.
•
•
•
•
•
•
•
2.3-μA operating quiescent current
Up to 4-MHz switching frequency
1% output voltage accuracy
DVS output from 0.4 V to 1.9875 V (12.5-mV
steps)
I2C user interface to adjust
– Output voltage presets
– Ramp speed
VSEL-pin to toggle VOUT during operation
Power good indication
Supports VTH_UVLO-.
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8.4 Programming
8.4.1 Serial Interface Description
I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus
Specification, Version .6, 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect
to the I2C bus through open-drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a
digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device
addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A
slave device receives, transmits data, or both on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The interface
adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending
on the instantaneous application requirements. Register contents remain intact as long as the input voltage
remains above 1.8 V.
The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different and must not be used.
It is recommended that the I2C master initiates a STOP condition on the I2C bus after the initial power up of SDA
and SCL pullup voltages to ensure reset of the I2C engine.
8.4.2 Standard- and Fast-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 8-4. All I2C-compatible devices
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 8-4. START and STOP Conditions
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 8-5). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 8-6) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with
a slave has been established.
DATA
CLK
Data line
stable;
data valid
Change
of data
allowed
Figure 8-5. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
14
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acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 8-4). This releases the bus and stops the communication link with
the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 8-6. Acknowledge on the I2C Bus
Figure 8-7. Bus Protocol
8.4.3 I2C Update Sequence
The requires the following:
•
•
•
•
A start condition
A valid I2C address
A register address byte
A data byte for a single update
After the receipt of each byte, the device acknowledges by pulling the SDA line low during the high period of a
single clock pulse. A valid I2C address selects the device. The device performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
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1
7
1
1
8
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Data
A/A
P
³0´ :ULWH
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
From Master to Slave
From Slave to Master
Figure 8-8. “Write” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address
R/W
A
Register Address
A
Sr
Slave Address
R/W
A
Data
A
P
³0´ :ULWH
From Master to Slave
From Slave to Master
³1´ 5HDG
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
Sr = REPEATED START condition
P = STOP condition
Figure 8-9. “Read” Data Transfer Format in Standard-, Fast, and Fast-Plus Modes
8.4.4 I2C Register Reset
The I2C registers can be reset by the following:
•
•
•
16
Pull the input voltage below 1.8 V (typ).
A high to low transition on EN. The previous value of the "Enable Output Discharge" bit is latched until the
next EN rising edge or pulling the input voltage below 1.0 V (typ).
Set the Reset bit in the CONTROL register. When Reset is set to 1, all registers are reset to the default
values and a new start-up begins immediately. After tDelay, the I2C registers can be programmed again.
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8.5 Register Map
Table 8-3. Register Map
REGISTER ADDRESS
(HEX)
REGISTER NAME
FACTORY DEFAULT
(HEX)
0x01
VOUT Register 1
0x10
Sets the target output voltage
0x02
VOUT Register 2
0x38
Sets the target output voltage
0x03
CONTROL Register
0x05
STATUS Register
DESCRIPTION
Sets miscellaneous configuration bits
0x00
Returns status flags, cleared on read-out
8.5.1 Slave Address Byte
7
6
1
5
0
4
0
3
0
2
0
1
0
0
0
R/W
The slave address byte is the first byte received following the START condition from the master device. The 7-bit
slave address is 0x40 and internally set.
8.5.2 Register Address Byte
7
0
6
5
0
4
0
3
0
2
0
1
D2
0
D1
D0
Following the successful acknowledgment of the slave address, the bus master sends a byte to the device,
which contains the address of the register to be accessed.
8.5.3 VOUT Register 1
Table 8-4. VOUT Register 1 Description
REGISTER ADDRESS 0X01 READ/WRITE
BIT
FIELD
6:0
VO1_SET
VALUE (HEX)
OUTPUT VOLTAGE (TYP)Section 8.5.3
0x00
0.400 V
0x01
0.4125 V
...
0x10
0.600 V (default value)
...
0x7E
1.975 V
0x7F
1.9875 V
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8.5.4 VOUT Register 2
Table 8-5. VOUT Register 2 Description
REGISTER ADDRESS 0X02 READ/WRITE
BIT
7
6:0
FIELD
VALUE (HEX)
OUTPUT VOLTAGE (TYP)Section 8.5.4
Operation Mode
0x00
0 - Keep PFM/PWM selection as in
CONTROL-Register
1 - sets the device in PWM operation for this
Voltage selection
VO2_SET
0x00
0.400 V
0x01
0.4125 V
...
0x38
1.10 V (default value)
...
0x7E
1.975 V
0x7F
1.9875 V
8.5.5 CONTROL Register
Table 8-6. CONTROL Register Description
REGISTER ADDRESS 0X03 READ/WRITE
BIT
FIELD
TYPE
7
Reset
W
0
1 - Reset all registers to default.
This bit triggers a shutdown followed by a re-reading of the
internal OTP settings and a new soft start.
6
Enable FPWM Mode during Output
Voltage Change
R/W
1
0 - Keep the current mode status during output voltage change.
1 - Force the device in FPWM during output voltage change.
5
Software Enable Device
R/W
1
0 - Disable the device. All registers values are still kept.
1 - Re-enable the device with a new start-up without the tDelay
period.
4
Enable FPWM Mode
R/W
0
0 - Set the device in power save mode at light loads.
1 - Set the device in forced PWM mode at light loads.
3
Enable Output Discharge
R/W
1
0 - Disable output discharge.
1 - Enable output discharge.
This setting is used for the next disable cycle (Software or
Hardware).
2
Reserved
R/W
11
00 - 10mV/µs
01 - 5 mV/µs
10 - 1 mV/µs
11 - 0.1 mV/µs
0:1
Voltage Ramp Speed
DEFAULT DESCRIPTION
8.5.6 STATUS Register
Table 8-7. STATUS Register Description
REGISTER ADDRESS 0X05 READ ONLY(1)
18
BIT
FIELD
7:5
Reserved
4
Thermal Shutdown Tripped
3
Reserved
2
Power Bad
TYPE
DEFAULT DESCRIPTION
R
0
1: Thermal Shutdown has tripped since the last reading.
0: No Thermal Shutdown event occurred during the last reading.
R
0
1: Output voltage is or was below 0.95xVO
0: No Power Bad event occurred since last reading
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Table 8-7. STATUS Register Description (continued)
REGISTER ADDRESS 0X05 READ ONLY(1)
(1)
BIT
FIELD
1:0
Reserved
TYPE
DEFAULT DESCRIPTION
All bit values are latched until the device is reset, or the STATUS register is read. Then, the STATUS register is reset to its default
values.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The following section discusses the design of the external components to complete the power supply design for
several input and output voltage options by using typical applications as a reference.
9.2 Typical Application, TPS628610
TPS628610
VIN
1.8V t 5.5V
0.47µH
VIN
SW
GND
VOS
EN
SDA
VSEL
SCL
VOUT
0.4V t 1.9V
10 …F
4.7 …F
Figure 9-1. TPS628610, Typical Application
9.2.1 Design Requirements
Table 9-1 shows the list of components for the application circuit and the characteristic application curves.
Table 9-1. Components for Application Characteristic Curves
DESCRIPTION
TPS628610
Step down converter, 1 A
CIN
Ceramic capacitor,
GRM155R60J475ME47D
4.7 µF
0402 (1 mm x 0.5 mm x 0.6 mm max.)
Murata
COUT
Ceramic capacitor,
GRM155R60J106ME15D
10 µF
0402 (1 mm x 0.5 mm x 0.65 mm max.)
Murata
L
Inductor DFE18SANR47MG0L
0.47 µH
0603 (1.6 mm x 0.8 mm x 1.0 mm max.)
Murata
(1)
20
VALUE
SIZE [L x W X T]
MANUFACTURER(1)
REFERENCE
1.4 mm x 0.70 mm x 0.4 mm max.
Texas Instruments
See Third-party Products Disclaimer.
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9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple, and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or V OUT and can be
estimated according to Equation 1.
Equation 2 calculates the maximum inductor current under static load conditions. The saturation current of
the inductor must be rated higher than the maximum inductor current, as calculated with Equation 2. This is
recommended because during a heavy load transient the inductor current rises above the calculated value. A
more conservative way is to select the inductor saturation current according to the high side MOSFET switch
current limit, ILIMF.
Vout
Vin
L ´ ¦
1D IL = Vout ´
ILmax = Ioutmax +
(1)
DIL
2
(2)
where
•
•
•
•
f = Switching frequency
L = Inductor value
ΔIL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
Table 9-2 shows a list of possible inductors.
Table 9-2. List of Possible Inductors
INDUCTANCE [µH]
INDUCTOR SERIES
SIZE IMPERIAL
(METRIC)
0.47
DFE18SAN_G0
0603 (1608)
1.6mm x 0.8mm x 1.0mm max
Murata
0.47
HTEB16080F
0603 (1608)
1.6mm x 0.8mm x 0.6mm max.
Cyntec
0.47
HTET1005FE
0402 (1005)
1.0mm x 0.5mm x 0.65mm max.
Cyntec
0.47
TFM160808ALC
0603 (1608)
1.6mm x 0.8mm x 0.8mm max.
TDK
(1)
DIMENSIONS L x W X T
SUPPLIER(1)
See Third-party Products Disclaimer
9.2.2.2 Output Capacitor Selection
The DCS-Control™ scheme of the TPS6286x allows the use of tiny ceramic capacitors. Ceramic capacitors with
low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires
either an X7R or X5R dielectric. At light load currents, the converter operates in Power Save Mode and the
output voltage ripple is dependent on the output capacitor value. A larger output capacitors can be used
reducing the output voltage ripple.
The inductor and output capacitor together provide a low-pass filter. To simplify this process, Table 9-3 outlines
possible inductor and capacitor value combinations.
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Table 9-3. Recommended LC Output Filter Combinations
(1)
(2)
(3)
DEVICE
NOMINAL INDUCTOR VALUE
[µH]
NOMINAL OUTPUT CAPACITOR VALUE [µF]
4.7 µF
10 µF
2 x 10 µF
22 µF
TPS628610
0.47(1)
√
√(3)
√
√
TPS62860x
1.0(2)
√
√(3)
√
√
An effective inductance range of 0.33 µH to 0.82 µH is recommended. An effective capacitance range of 2 µF to 26 µF is
recommended.
An effective inductance range of 0.7 µH to 1.2 µH is recommended. An effective capacitance range of 3 µF to 26 µF is recommended.
Typical application configuration. Other check marks indicate alternative filter combinations.
9.2.2.3 Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR ceramic input capacitor is required for
best input voltage filtering to minimize input voltage spikes. For most applications, a 4.7-µF input capacitor is
sufficient. When operating from a high impedance source, like a coin cell, a larger input buffer capacitor ≥10 µF
is recommended to avoid voltage drops during start-up and load transients. The input capacitor can be increased
without any limit for better input voltage filtering. The leakage current of the input capacitor adds to the overall
current consumption.
Table 9-4 shows a selection of input and output capacitors.
Table 9-4. List of Possible CapacitorsSection 9.2.2.3
CAPACITOR PART NUMBER
SIZE IMPERIAL
(METRIC)
4.7
GRM155R60J475ME47D
0402 (1005)
1.0mm x 0.5mm x 0.6mm max.
Murata
4.7
GRM035R60J475ME15
0201 (0603)
0.6mm x 0.3mm x 0.55mm max
Murata
10
GRM155R60J106ME15D
0402 (1005)
1.0mm x 0.5mm x 0.65mm max.
Murata
(1)
22
SUPPLIER(1)
CAPACITANCE [μF]
DIMENSIONS L x W X T
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9.2.3 Application Curves
95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
VIN = 3.8 V, VOUT = 1.1 V, TA = 25°C, BOM = Table 9-1, unless otherwise noted
75
70
65
60
55
75
70
65
60
55
VIN
VIN
VIN
VIN
VIN
50
45
40
10P
100P
1m
10m
=
=
=
=
=
1.8V
2.5V
3.3V
3.8V
5.0V
100m
VIN
VIN
VIN
VIN
VIN
50
45
40
10P
1
100P
Load Current [A]
VOUT = 1.1 V
Auto Power Save Mode
VOUT = 0.6 V
Figure 9-2. Efficiency
100m
1
Auto Power Save Mode
Figure 9-3. Efficiency
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
10m
1.8V
2.5V
3.3V
3.8V
5.0V
Load Current [A]
95
75
70
65
60
55
75
70
65
60
55
50
VIN
VIN
VIN
VIN
45
40
10P
100P
1m
10m
=
=
=
=
100m
VIN
VIN
VIN
VIN
VIN
50
2.5V
3.3V
3.8V
5.0V
45
1
40
10P
100P
Load Current [A]
VOUT = 1.9875 V
Auto Power Save Mode
VOUT = 0.4 V
VIN
VIN
VIN
VIN
VIN
10m
100m
=
=
=
=
=
1.8V
2.5V
3.3V
3.8V
5.0V
1
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
1m
100m
1
Auto Power Save Mode
VIN
VIN
VIN
VIN
VIN
10m
Load Current [A]
VOUT = 1.1 V
10m
1.8V
2.5V
3.3V
3.8V
5.0V
Figure 9-5. Efficiency
Efficiency [%]
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
1m
1m
=
=
=
=
=
Load Current [A]
Figure 9-4. Efficiency
Efficiency [%]
1m
=
=
=
=
=
100m
=
=
=
=
=
1.8V
2.5V
3.3V
3.8V
5.0V
1
Load Current [A]
Forced PWM Operation
Figure 9-6. Efficiency, Inductor Comparison
VOUT = 0.6 V
Forced PWM operation
Figure 9-7. Efficiency
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4
Switching Frequency [Hz]
Switching Frequency [MHz]
1M
3
100k
10k
2
1k
1
VIN
VIN
VIN
VIN
VIN
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
=
=
=
=
=
1.8V
2.5V
3.3V
3.8V
5.0V
0.9
VIN
VIN
VIN
VIN
VIN
100
1
1P
10P
10m
100m
1
VOUT = 1.1 V
Auto Power Save Mode
Figure 9-8. Switching Frequency
Figure 9-9. Switching Frequency
IOUT = 500 mA
VSEL = HIGH
Figure 9-10. PFM Mode Operation
10mV/µs
1m
1.8V
2.5V
3.3V
3.8V
5.0V
Load Current [A]
Load Current [A]
VOUT = 1.1 V
100P
=
=
=
=
=
VSEL = HIGH
Figure 9-11. PWM-Mode Operation
5mV/µs
5mV/µs
10mV/µs
1mV/µs
1mV/µs
0.1mV/µs
Default voltage setting
Default voltage setting
Figure 9-12. DVS by VSEL, Different Ramp Speed
Settings
24
Figure 9-13. DVS by VSEL, Different Ramp Speed
Settings
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IL
IL
Power Save Mode is active
Power Save Mode is active
Figure 9-14. Standard Operation: VOUT Change
Figure 9-15. FPWM-Mode During VOUT Change
Enabled
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9.2.4 Typical Application, TPS628600, TPS62860x
TPS628600
VIN
1.8V t 5.5V
VOUT
0.4V t 1.9V
1µH
VIN
SW
GND
VOS
EN
SDA
VSEL
SCL
10 …F
4.7 …F
Figure 9-16. TPS628600, Typical Application
TPS628601
VIN
1.8V t 5.5V
1.0µH
VIN
SW
GND
VOS
VOUT
10 …F
4.7 …F
EN
VSEL-1
PG
VSEL-2
Figure 9-17. TPS62860x, Typical Application
9.2.4.1 Design Requirements
Table 9-5 shows the list of components for the application circuit and the characteristic application curves.
Table 9-5. Components for Application Characteristic Curves
VALUE
SIZE [L x W X T]
MANUFACTURER(1)
REFERENCE
DESCRIPTION
TPS628610
Step down converter, 1 A
CIN
Ceramic capacitor,
GRM155R60J475ME47D
4.7 µF
0402 (1 mm x 0.5 mm x 0.6 mm max.)
Murata
COUT
Ceramic capacitor,
GRM155R60J106ME15D
10 µF
0402 (1 mm x 0.5 mm x 0.65 mm max.)
Murata
L
Inductor DFE201610E
1 µH
0805 (2.0 mm x 1.6 mm x 1.0 mm max.)
Murata
1.4 mm x 0.70 mm x 0.4 mm max.
Texas Instruments
9.2.4.2 Detailed Design Procedure
See Section 9.2.2.
26
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95
95
90
90
85
85
80
80
Efficiency [%]
Efficiency [%]
9.2.4.3 Application Curves
75
70
65
60
55
75
70
65
60
55
VIN
VIN
VIN
VIN
VIN
50
45
40
10P
100P
1m
10m
=
=
=
=
=
100m
1.8V
2.5V
3.3V
3.8V
5.0V
VIN
VIN
VIN
VIN
VIN
50
45
1
40
10P
100P
Load Current [A]
VOUT = 1.1 V
1m
10m
=
=
=
=
=
1.8V
2.5V
3.3V
3.8V
5.0V
100m
1
Load Current [A]
Auto Power Save Mode
Figure 9-18. Efficiency
VOUT = 0.7 V
Auto Power Save Mode
Figure 9-19. Efficiency
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10 Power Supply Recommendations
The power supply must provide a current rating according to the supply voltage, output voltage, and output
current of the TPS6286x.
28
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11 Layout
11.1 Layout Guidelines
The pinout of TPS6286x has been optimized to enable a single top layer PCB routing of the IC and its
critical passive components such as CIN, COUT, and L. Furthermore, this pin out allows you to connect tiny
components such as 0201 (0603) size capacitors and 0402 (1005) size inductor. A solution size smaller than 5
mm2 can be achieved with a fixed output voltage.
•
•
•
•
As for all switching power supplies, the layout is an important step in the design. Care must be taken in board
layout to get the specified performance.
It is critical to provide a low inductance, low impedance ground path. Therefore, use wide and short traces for
the main current paths.
The input capacitor must be placed as close as possible to the VIN and GND pins of the IC. This is the most
critical component placement.
The VOS line is a sensitive, high impedance line and must be connected to the output capacitor and routed
away from noisy components and traces (for example, SW line) or other noise sources.
11.2 Layout Example
GND
VOUT
VIN
Figure 11-1. PCB Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
DCS-Control™ and TI E2E™ are trademarks of Texas Instruments.
I2C™ is a trademark of NXP Semiconductors.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
30
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS628600YCHR
ACTIVE
DSBGA
YCH
8
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
S
TPS628601YCHR
ACTIVE
DSBGA
YCH
8
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
T
TPS628610YCHR
ACTIVE
DSBGA
YCH
8
12000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 125
U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
